KR101512089B1 - Output current control circuit for power converters - Google Patents

Abstract

The control circuit can be applied to a power conversion device that controls the input current of the power conversion device, so that the power conversion device outputs the predetermined amount of output charge in each line cycle. The control circuit includes an input current control circuit, an output charge detection circuit, and a gating logic circuit. The input current control circuit generates a pulse width modulation (PWM) signal to control the input current of the power converter. After the amount of output charge output by the power converter in a single line cycle reaches a predetermined amount, the output charge detection circuit generates the corresponding gating logic signal. The gating logic circuit controls the switch of the power conversion device according to the gating logic signal and the pulse width modulation signal so that the power conversion device outputs the predetermined amount of output charge in each line cycle.

Description

TECHNICAL FIELD [0001] The present invention relates to an output current control circuit for a power converter,

The present invention relates to a control circuit for a power conversion apparatus, and more particularly to a control circuit for a power conversion apparatus that outputs a predetermined amount of charge in each line cycle.

The power converter is used to convert AC current to DC current (AC / DC) or DC current to DC current (DC / DC). The power conversion device can convert input power to output power and adjust the output voltage or output current of the system.

The switch mode power conversion device is a kind of power conversion device. The efficiency of a switched mode power converter is better than that of a linear regulator. Switch mode power converters convert input power into output power by storing and releasing energy. To store and discharge energy, an electric energy storage device, such as a magnetic energy storage device or a capacitor, such as a transformer, may be used.

Typically, switch mode power converters have switches. The switch controls the power conversion of the power conversion device. The control circuit for the power converter is mainly used to control the switch. Related technology is disclosed in U. S. Patent Application No. < RTI ID = 0.0 > No. < / RTI > 2012 / 0,146,607; and U.S. Pat. 8,139,384.

When the control circuit for the power converter is applied to the dimmer circuit of the mono-stage LED driver, there are usually some problems such as flicker due to misfiring or line power distribution.

In order to solve the above-mentioned flickering problem due to the silent or line power distribution, the present application discloses a control circuit for a power conversion device. The control circuit can control the power conversion device to output the predetermined amount of output charge in each line cycle.

According to one embodiment of the invention, the control circuit for the power converter comprises an input current control circuit, an output charge detection circuit and a gating logic circuit. The input current control circuit generates a pulse width modulation signal according to the first reference voltage and the input current to control the input current of the power conversion device. The output charge detection circuit converts the output current into a representative voltage representing the amount of output charge. The output charge detection circuit further generates a gating logic signal in accordance with the representative voltage and the second reference voltage. The gating logic circuit does not selectively send or send the pulse width modulated signal according to the gating logic signal.

According to one embodiment of the present application, the control circuit further comprises a cutoff line voltage detector. The cutoff line voltage detector generates the feedback voltage according to the gating logic signal, the input voltage, and the third reference voltage. The input current control circuit generates a pulse width modulation signal according to the first reference voltage and the feedback voltage to control the input current.

Consequently, the output charge detection circuit detects the total amount of charge output by the power converter in each line cycle. The gating logic circuit stops the output of the pulse width modulation signal when the amount of charge reaches the predetermined amount to stop the power converter from outputting the energy. Thus, the total amount of charge output by the power converter is equal to the predetermined amount in each line cycle. Furthermore, the input current control circuit controls the input current of the power conversion device by adjusting the pulse width modulation signal.

Are included in the scope of the present invention.

This disclosure is more fully understood from the following detailed description, given by way of example only, and not by way of limitation.
1 is a circuit block diagram of a control circuit applied to a power conversion apparatus according to an embodiment of the present invention.
2 is a detailed structural circuit diagram of the control circuit of FIG.
FIG. 3 is a circuit block diagram of the input filter in FIG. 2; FIG.
Figure 4 is a time sequence diagram of the control circuit in Figure 1;
5 is a circuit block diagram of a control circuit applied to the power conversion apparatus according to the second embodiment of the present application.
6 is a detailed structural circuit diagram of the control circuit in Fig.
FIG. 7 is a time sequence diagram of the cutoff line voltage detector in FIG. 5; FIG.

The detailed features and advantages of the invention are set forth in more detail in the specification that follows, and the detailed description is sufficient to enable those skilled in the art to understand the technical details of the invention and to practice the invention accordingly. Based on the contents of the description, claims and drawings, those skilled in the art can easily understand the related objects and advantages of the present invention.

1, which is a circuit block diagram of a control circuit applied to the power conversion apparatus according to the first embodiment of the present application.

The control circuit 80 can be applied to the power inverter 90. [ The control circuit 80 is electrically connected to the input port 91a and the output port 91b of the power inverter 90 to detect the states of the input port 91a and the output port 91b.

An alternating current (AC) power supply 96 provides an AC voltage (V _AC ) to the dimmer circuit 94. The AC voltage V _AC is regulated by the dimmer circuit 94 and rectified by the bridge rectifier 92 to form a full wave rectified signal V _{in as} shown in FIG. The full wave rectification signal V _in is supplied to the input port 91a of the power inverter 90. [ In accordance with the control signal output by the control circuit 80, the switch 93 of the power inverter 90 outputs the corresponding output signal V _out . The output signal V _out can be applied to any type of load, for example, a light emitting diode (LED).

The dimmer circuit 94 described above is also referred to as a bidirectional triode thyristor, also referred to as TRIAC (Triode for Alternating Current). While the AC voltage V _AC is applied to the TRIAC, the AC voltage a predetermined phase of V _AC) is cut. then, the dimming phase-cut (dimming phase-cut) AC voltage form a full wave rectified signal (V _in) as shown in Figure 4 is rectified by a bridge rectifier 92 do.

The power conversion device 90 described above is, for example, a bulk converter, a boost converter, a step-up converter, a flyback converter, or a forward converter.

2, which is a detailed structural circuit diagram of the control circuit of Fig. The control circuit 80 includes an input current control circuit 10, an output charge detection circuit 20, and a gating logic circuit 30.

The input current control circuit 10 generates a pulse width modulation (PWM) signal according to the first reference voltage V _ref1 and the input current I _in to control the input current of the power inverter 90. The output charge detection circuit 20 converts the output current I _out into a representative voltage V _Qout representing the amount of output charge. The output charge detection circuit 20 further generates a gating logic signal V _logic in accordance with the second reference voltage V _ref2 and the representative voltage V _Qout . The gating logic circuit 30 generates a switch control signal in accordance with the pulse width modulation signal and the gating logic signal ( _Vlogic ). In particular, the gating logic circuit 30 controls the switch 93 to deliver the pulse width modulated signal to the switching gate 34 when the gating logic signal (V _logic ) is at a high logic level. The gating logic circuit 30 stops transferring the pulse width modulation signal to the switching gate 34 when the gating logic signal V _logic is at a low logic level so that the power conversion device 90 converts the input energy into output energy Thereby stopping the conversion.

The signal output from the gating logic circuit 30 is referred to as a switch control signal. The switch control signal is used to control the switch 93 of the power inverter 90. [ When the other words, the gating logic signal ((V _logic) is at a high logic level, the switch control signal is equal to the pulse width modulation signal. If the gating logic signal ((V _logic) is at a low logic level, the switch control signal is at the low logic level The switch 93 is turned off.

The input current control circuit 10 includes an input filter 12, an error amplifier 14, an oscillator 18, a ramp generator 19, a first comparator 16 and a latch 17.

3, which is a circuit block diagram of the input filter in Fig. The input filter 12 has an input current sensor 120 and a filter 122. The input filter 12 generates an average input voltage signal V _Iin corresponding to the average input current according to the input current I _in . The average input voltage signal (V _Iin ) is directly proportional to the average input current. The order of the input current sensor 120 and the filter 122 may be alternated.

See FIGS. 1 and 2 again. The error amplifier 14 generates an error signal EA _out in accordance with the average input voltage signal V _Iin and the first reference voltage V _ref1 . That is, the error amplifier 14 derives the difference between the average input voltage signal V _Iin and the first reference voltage V _ref1 , and amplifies the difference to generate the error signal EA _out . A timing sequence diagram of the error signal EA _{out is} shown in FIG. The positive input port of the error amplifier 14 is used to receive the first reference voltage V _ref1 and the negative input port of the error amplifier 14 is used to receive the average input voltage signal V _Iin . The first reference voltage V _ref1 described above is directly proportional to the input current of the power _inverter 90.

The oscillator 18 is used to generate the clock signal CLK. A timing sequence diagram is shown in Fig. The switching cycle of the clock signal CLK represents the switching cycle T _sw of the power converter 90 as shown in Figs. The switching cycle is the switching cycle of the pulse width modulation signal (PWM).

The ramp generator 19 generates the ramp signal Ramp in accordance with the clock signal CLK. A timing sequence diagram is shown in Fig. The first comparator 16 compares the ramp signal Ramp with the error signal EA _out and generates a comparison signal Comp_out. A timing sequence diagram is shown in Fig. The negative input port of the first comparator 16 is used to receive the error signal EA _out and the positive input port of the first comparator 16 is used to receive the ramp signal Ramp. As shown in FIG. 4, when the voltage of the ramp signal Ramp is larger than the voltage of the error signal EA _out , the comparison signal Comp_out is at a high logic level. Otherwise, the comparison signal Comp_out is at a low logic level.

The latch 17 generates the pulse width modulation signal PWM in accordance with the comparison signal Comp_out and the clock signal CLK. The latch 17 is, for example, an SR latch. In the example of the SR latch, the set port of the SR latch is used to receive the clock signal CLK, and the reset port of the SR latch is used to receive the comparison signal Comp_out. Therefore, as shown in Fig. 4, the duty cycle of the pulse width modulation signal PWM, also referred to as a switching duty cycle, starts at the rising edge of the clock signal CLK and ends at the rising edge of the comparison signal Comp_out.

As described above, the pulse width modulation signal PWM output by the input current control circuit 10 is related to the first reference voltage V _ref1 and the input current I _in . Input current control circuit 10 to be maintained at a value that is the input current (I _in) to control the input current (I _in) to the first reference voltage (V _ref1) value. The input current I _in is the current supplied to the power inverter 90. Thus, the input current control circuit 10 ensures that the input current I _in is equal to or greater than the predetermined current value. The predetermined current value may be related to the holding current (I _holding ) of the dimmer circuit 94. For example, if the dimmer circuit 94 is TRIAC, the predetermined current value is set to the minimum value of the holding current I _holding of TRIAC.

Next, see FIGS. 2 and 4. The output charge detection circuit 20 includes an output filter 22, an integrator 24, and a second comparator 26. In this specification, the output filter 22 may be formed integrally with the integrator 24. [

The output filter 22 generates an average output voltage signal V _Iout in accordance with the output current I _out . The output filter 22 is similar to the input filter 12 described above.

The integrator 24 represents the representative voltage V _Qout by integrating the average input voltage signal V _Iout . A timing sequence diagram of the representative voltage V _{Qout is} shown by a broken line in Fig. The representative voltage V _Qout is directly proportional to the total amount of charge output by power converter 90 in a single line cycle.

The positive input port of the second comparator 26 is used to receive the second reference voltage V _ref2 and the negative input port of the second comparator 26 is used to receive the representative voltage V _Qout . The second comparator 26 compares the second reference voltage V _ref2 with the representative voltage V _Qout to generate a gating logic signal V _logic to stop the switching of the power converter so that the switching power conversion device is activated and is stopped at a cut-off time during which the V _Qout equal to V _ref2. The second reference voltage V _ref2 is related to the predetermined total charge output by the power inverter 90 in a single line cycle and the predetermined amount is defined by the control circuit 80. In this specification, the line cycle is the same as the line cycle of the full wave rectification signal (V _in ). 1, when the frequency of the AC voltage V _AC is 60 Hz, the frequency of the full-wave rectified signal V _in is 120 Hz and the line cycle of the full-wave rectified signal V _in is 1/120 second. That is, the above-described second reference voltage V _ref2 relates to the total amount of charge that is output by the power inverter 90 in each line cycle.

Here, when the second reference voltage V _ref2 is greater than the representative voltage V _Qout , the gating logic signal V _logic is at a high logic level. When the second reference voltage V _ref2 is less than the representative voltage V _Qout , the gating logic signal V _logic is at a low logic level.

The gating logic circuit 30 generates a switch control signal in accordance with the gating logic signal (V _logic ) and the pulse width modulation signal (PWM) to control the switch 93 of the power conversion device 90. The gating logic circuit 30 sends a pulse width modulation signal PWM when the gating logic signal V _logic is at a high logic level and a pulse width modulation signal PWM when the gating logic signal V _logic is at a low logic level, PWM). In other words, when the gating logic signal (V _logic ) is at a high logic level, the switch control signal is the same as the pulse width modulated signal (PWM). When the gating logic signal (V _logic ) is at a low logic level, the switch control signal is at a low logic level. The gating logic circuit 30 is, for example, an AND gate 32. The AND gate 32 is used to receive the pulse width modulation signal PWM and the gating logic signal V _logic . The gating logic circuit 30 may be any other digital circuit capable of stopping sending or sending the pulse width modulated signal PWM.

Next, see FIGS. 5 to 7. 5 is a circuit block diagram of a control circuit applied to the power conversion apparatus according to the second embodiment of the present application; Fig. 6 is a detailed structural circuit diagram of the control circuit in Fig. 5; Fig. And FIG. 7 is a timing sequence diagram of the cut-off line voltage detector in FIG.

The control circuit 82 includes an input current control circuit 10 ', an output charge detection circuit 20, a gating logic circuit 30, and a cutoff line voltage detector 40. The output charge detection circuit 20 converts the output current I _out into a representative voltage V _Qout representing the amount of output charge. The output charge detection circuit 20 further generates a gating logic signal V _logic in accordance with the second reference voltage V _ref2 and the representative voltage V _Qout . The cutoff line voltage detector 40 generates the feedback voltage V _ERROR according to the gating logic signal V _logic , the full wave rectified signal V _in , and the third reference voltage V _ref3 . The input current control circuit 10 'generates the pulse width modulation signal PWM according to the first reference voltage V _ref1 , the feedback voltage V _ERROR and the input current I _in to generate the input current I _in , . The gating logic circuit 30 does not selectively send the pulse width modulation signal PWM according to the gating logic signal V _logic and the pulse width modulation signal PWM.

The cutoff line voltage detector 40 includes a sample and hold circuit 42 and an error amplifier 44. In Fig example 7 example, K <1, the sample-and-hold circuit 42 is full-wave rectified signal (V _in), the sampled-and-hold was sampled the cut-off line voltage signal according to a gating logic signal (V _logic) (V _{S / H} ). It is noted that the sampled cutoff line voltage signal (V _{S / H} ) remains unchanged when the gating logic signal (V _logic ) is at a high logic level. The sampled cutoff line voltage signal (V _{S / H} ) is equal to the full wave rectified signal (V _in ) when the gating logic signal (V _logic ) is at a low logic level. The negative input port of the error amplifier 44 is used to receive the third reference voltage V _ref3 and the positive input port of the error amplifier 44 receives the sampled cutoff line voltage signal V _{S /} Is used. The error amplifier 44 compares the sampled cutoff line voltage signal V _{S / H} with the third reference voltage V _ref3 and generates a feedback voltage V _ERROR , also referred to as an error signal.

When the input current control circuit 10 'is applied to the power converter 90 together with the dimmer circuit 94, the feedback voltage V _ERROR is set so that the sampled cutoff line voltage signal V _{S / Lt} ; / RTI &gt; is used to adjust the _nominal input current level to be close to the voltage V _ref3 . For example, when the sampled cutoff line voltage signal V _{S / H} is greater than the third reference voltage V _ref3 , the input current I _in is downgraded so that the cutoff line voltage is lower than the third reference voltage V _ref3 ), And vice versa.

The input current control circuit 10 'includes an input filter 12, a summing circuit 13, an error amplifier 14, an oscillator 18, a ramp generator 19, a first comparator 16, and a latch 17, Respectively. The input filter 12 generates an average input voltage signal V _Iin according to the input current I _in . The average input voltage signal (V _Iin ) is directly proportional to the average of the input current (I _in ). The summing circuit 13 generates the regulated voltage signal V _{adj by} adding the average input voltage signal V _Iin and the feedback voltage V _ERROR . The negative input port of the error amplifier 14 is used to receive the regulated voltage signal V _adj and the positive input port of the error amplifier 14 is used to receive the first reference voltage V _ref1 . The error amplifier 14 generates an error signal EA _out in accordance with the adjustment voltage signal V _adj and the first reference voltage V _ref1 . In other words, the error amplifier 14 derives the difference by comparing the regulated voltage signal V _adj with the first reference voltage V _ref1 , and amplifies the difference to generate the error signal EA _out . A timing sequence diagram of the error signal EA _{out is} shown in FIG. Thus, in this embodiment, the summation circuit 13 and the cutoff line voltage detector 40 are used to ensure that the total amount of charge output by the power inverter 90 in a single line cycle is equal to the predetermined value.

As described above, the output charge detection circuit 20 detects the total amount of charge output by the power conversion device 90 in a single line cycle. When the amount of charge reaches the predetermined value, the gating logic circuit 30 stops outputting the pulse width modulation signal PWM and stops outputting the output port 91b of the output conversion device 90 to output the power . Thus, the total amount of charge output by the power inverter 90 is controlled. When the power inverter 90 is applied to a plurality of light emitting diodes (LEDs), the output current is maintained. Further, with the pulse width modulation signal PWM output by the input current control circuit 10 or 10 ', the input current of the power inverter 90 is controlled such that the light control device of the dimmer circuit 94, such as TRIAC, (94).

10 or 10 ': input current control circuit
12: Input filter
13: summing circuit
14: Error amplifier
16: first comparator
17: Latch
18: Oscillator
19: Lamp generator
20: Output charge detection circuit
22: Output filter
24: integrator
26: second comparator
30: Gating logic circuit
32: AND gate
40: Cutoff line voltage detector
44: Error amplifier
80: control circuit
90: output conversion device
91b: input port
91b: output port
92: Bridge rectifier
93: Switch
94: dimmer circuit
96: Power supply

Claims (8)

An input current control circuit used to generate a pulse width modulated signal according to a first reference voltage, a feedback voltage, and an input current to control an input current of the power conversion apparatus;
An output charge detection circuit which converts the output current into a representative voltage representing the amount of output charge and generates a gating logic signal in accordance with the representative voltage and the second reference voltage,
A gating logic circuit used to send a pulse width modulated signal in accordance with a gating logic signal,
And a cutoff line voltage detector used to generate the feedback voltage according to the gating logic signal, the input voltage and the third reference voltage. The method according to claim 1,
The input current control circuit
An input filter used to generate an average input voltage signal according to an input current,
An error amplifier used to generate an error signal according to an average input voltage signal and a first reference voltage,
An oscillator used to generate a clock signal,
A ramp generator used to generate a ramp signal in response to a clock signal,
A first comparator used to generate a comparison signal by comparing the ramp signal and the error signal,
And a latch used for generating a pulse width modulated signal by comparing the ramp signal and the error signal. 3. The method of claim 2,
The input filter
An input current sensor used to generate a voltage signal in accordance with the input current,
A control circuit that can be applied to a power conversion device having a filter used to generate an average input voltage signal in accordance with a voltage signal. The method according to claim 1,
The output charge detection circuit
An output filter used to generate an average output voltage signal in accordance with the output current,
An integrator used to integrate an average output voltage signal to output a representative voltage,
And a second comparator used to generate a gating logic signal by comparing the representative voltage with a second reference voltage. 5. The method of claim 4,
The output filter
An output current sensor used to generate a voltage signal in accordance with the output current,
A control circuit that can be applied to a power conversion apparatus having a filter used to generate an average output voltage signal in accordance with a voltage signal. delete The method according to claim 1,
The cutoff line voltage detector
A sample and hold circuit used to sample and hold an input voltage in accordance with a gating logic signal to generate a sample and hold signal,
A control circuit that can be applied to a power conversion apparatus having an error amplifier used to generate a feedback voltage by comparing the sample and hold signal with a third reference voltage. 8. The method of claim 7,
The input current control circuit
An input filter used to generate an average input voltage signal according to an input current,
A summation circuit used to add the average input voltage signal and the feedback voltage to generate the regulated voltage signal,
An error amplifier used to generate an error signal in accordance with the regulated voltage signal and the first reference voltage,
An oscillator used to generate a clock signal,
A ramp generator used to generate a ramp signal in response to a clock signal,
A first comparator used to generate a comparison signal by comparing the ramp signal with an error signal,
And a latch used for generating a pulse width modulated signal in accordance with the comparison signal and the clock signal.

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