KR101478352B1 - Abnormal switching monitoring device and abnormal switching monitoring method - Google Patents

Abstract

The present invention relates to an abnormal switching monitoring apparatus and a monitoring method.

The turn-on time of each of the upper switch including the first electrode to which the input voltage is input and the lower switch connected to the second electrode of the upper switch is compared with the time when the charge current starts not to flow and the start time of the flow starts, Thereby determining whether the abnormal zero voltage is switched. The power supply unit supplies the operating current to the gate driver for controlling the switching operation of the upper switch.

Zero voltage switching

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an abnormal switching monitoring apparatus and an abnormal monitoring apparatus,

The present invention relates to a monitoring apparatus and a monitoring method for detecting an abnormal switching operation. More specifically, the present invention relates to a monitoring apparatus for monitoring a non-zero voltage switching and a method for monitoring an abnormal voltage switching.

The MOSFET switch controlling the operation of the converter is preferably controlled to operate at zero voltage switching. Turning on when the voltage across the switch is '0' reduces the switching loss and prevents damage to the switch.

For example, in an LLC resonant converter, when the overload is applied or the input voltage is low, the phase of the drain current of the MOSFET switch may be ahead of the phase of the gate input signal. Then, when the switch of the converter switches, hard switching and shoot-through occur. Hard switching is a phenomenon that turns on before the voltage across the switch drops to zero. Shoot-through is a phenomenon in which a high peak current occurs in the switch due to reverse recovery of the body diode.

This phenomenon not only increases the switching loss, but also causes damage to the switch. Therefore, if the switch fails in zero voltage switching, that is, in the case of non-zero voltage switching, continuing to operate the converter causes power loss due to switching loss and switch damage.

In order to solve such problems, an object of the present invention is to provide an abnormal switching monitoring apparatus and an abnormal switching monitoring method capable of detecting an ideal voltage switching.

An abnormal switching monitoring apparatus according to one aspect of the present invention monitors a non-zero voltage switching of a lower switch connected to a second electrode of an upper switch including a first electrode to which an input voltage is input do. The abnormal switching monitoring apparatus includes a power supply unit for supplying an operation current to a gate driving unit for controlling the switching operation of the upper switch and comparing a time point at which a current starts flowing to the power supply unit and a time point at which the lower switch is turned on It is determined whether or not the abnormal switch of the lower switch is switched over. The power supply unit may include a bootstrap capacitor connected to the gate driving unit to supply an operation current, a diode for allowing current to flow through the bootstrap capacitor, and a current sensing unit to which a power supply voltage is applied at one end, Device. The current sensing element is a resistor. The bootstrap capacitor has one end connected to the cathode electrode of the diode, the other end of the bootstrap capacitor connected to the second electrode of the upper switch, the anode electrode of the diode connected to the other end of the current sensing device . The voltage of each of the current sensing elements is compared with each other, and the comparison result and the lower gate signal controlling the lower switch are logically operated to determine whether the abnormal zero voltage switching is performed. The abnormal switching monitoring apparatus includes a comparator including an inverting terminal to which the power supply voltage is input and a non-inverting terminal connected to the other end of the current sensing device, and a comparator connected to an output terminal of the comparator, ≪ / RTI > The abnormal switching monitoring apparatus determines that the abnormal zero voltage switching is performed when the time when the charging current starts flowing is later than the time when the lower switch is turned on.

The abnormal switching monitoring apparatus according to another aspect of the present invention monitors non-zero voltage switching of an upper switch including a first electrode to which an input voltage is input. Wherein the abnormal switching monitoring apparatus includes a power supply unit for supplying an operating current to a gate driving unit for controlling the switching operation of the upper switch and comparing a time point at which no current flows to the power supply unit and a time point at which the upper switch is turned on And determines whether the abnormal switch of the upper switch is switched to the abnormal zero voltage. The power supply unit may include a bootstrap capacitor connected to the gate driving unit to supply an operation current, a diode for allowing current to flow through the bootstrap capacitor, and a current sensing unit to which a power supply voltage is applied at one end, . The current sensing element is a resistor. The bootstrap capacitor has one end connected to the cathode electrode of the diode, the other end of the bootstrap capacitor connected to the second electrode of the upper switch, the anode electrode of the diode connected to the other end of the current sensing device . The abnormal switching monitoring apparatus compares the voltages of both ends of the current sensing element and performs logic operation on the comparison result and the upper gate signal for controlling the upper switch to determine whether the abnormal zero voltage switching is performed. The abnormal switching monitoring apparatus includes a comparator including a non-inverting terminal to which the power supply voltage is inputted and an inverting terminal connected to the other end of the current sensing device, and a comparator connected to an output terminal of the comparator, And further includes an AND gate. The abnormal switching monitoring apparatus determines that the abnormal zero voltage switching is performed when the time when the charging current starts not to flow is later than the time when the upper switch is turned on.

According to another aspect of the present invention, there is provided an abnormal switching monitoring method comprising: monitoring an abnormal voltage switching of a lower switch connected to a second electrode of an upper switch including a first electrode to which an input voltage is input; Detecting a charging current flow for charging a bootstrap capacitor for supplying an operating current to a gate driving unit for controlling a switching operation; comparing a time point at which the lower switch is turned on and a point at which the charging current starts flowing; And determining whether or not the abnormal switch of the lower switch is switched according to the result. The step of determining whether or not the abnormal switch of the lower switch is abnormal may be determined as the abnormal zero voltage switching if the start of the flow of the charge current is later than the lower switch turn on time.

According to another aspect of the present invention, there is provided an abnormal switch monitoring method comprising: monitoring an abnormal voltage switching of an upper switch including a first electrode to which an input voltage is input; and controlling a switching operation of the upper switch, Detecting a charging current flow for charging the bootstrap capacitor; comparing a time point at which the upper switch is turned on and a point at which the charging current starts not flowing; And determining whether the voltage is switched. The step of determining whether or not the abnormal switch of the upper switch is abnormal may be determined to be abnormal zero voltage switching when the time when the charging current starts not to flow is later than the upper switch turn on time.

As described above, according to an aspect of the present invention, there is provided an abnormal switching monitoring apparatus and a zero voltage switching monitoring method capable of detecting a zero voltage switching operation failure.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention in the drawings, parts not related to the description are omitted, and like parts are denoted by similar reference numerals throughout the specification.

Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "electrically connected" with another part in between . Also, when an element is referred to as "comprising ", it means that it can include other elements as well, without departing from the other elements unless specifically stated otherwise.

Hereinafter, an abnormal switching monitoring apparatus according to an embodiment of the present invention monitors an abnormal zero voltage switching, and a converter including the monitoring apparatus will be described in detail with reference to the drawings.

1 is a block diagram of a converter to which an abnormal switching monitoring apparatus according to an embodiment of the present invention is applied. FIG. 1 shows only a configuration for explaining an abnormal switching monitoring apparatus.

As shown in FIG. 1, the converter includes a switch unit 100, a switch driving unit 200, a resonant network unit 300, and an abnormal switching monitoring device 400. The bootstrap capacitor CH supplies the operating current so that the upper gate driver 210 can operate. The capacitor CVcc smoothes the power supply voltage Vcc. The resistor RD stabilizes the charge current flowing to the bootstrap capacitor CH by the supply voltage Vcc by a damping resistor. The abnormal switching monitoring apparatus 400 includes a power supply circuit 430 of an upper gate driver constituted by a resistor RD, a bootstrap capacitor CH and a diode DB.

The switch unit 100 includes an upper switch M1 and a lower switch M2. The switch unit 100 generates the input DC voltage Vin as a square wave by the switching operation of the upper switch Ml and the lower switch M2. Specifically, each of the upper switch Ml and the lower switch M2 is turned on / off alternately. The resonant input voltage VR between the node N1 and the node N2 is a peak value and a square wave having the same level as the voltage Vin and the lowest value 0V. The upper switch M1 is controlled by the gate control signal VG1 transmitted from the upper gate driver 210 of the switch driver 200 and the lower switch M2 is controlled by the switch driver 200, The gate control signal VG2 transmitted from the low-side gate driver 220 of FIG. The upper switch M1 and the lower switch M2 according to the embodiment of the present invention are implemented as a metal oxide semiconductor field-effect transistor (MOSFET), and are n-channel type NMOSFETs.

The resonant network unit 300 includes a resonant capacitor Cr, a leakage inductor Lk and a magnetizing inductor Lm. Resonance is controlled in accordance with the switching operation of the upper switch Ml and the lower switch M2. When the upper switch M1 is turned off and the lower switch M2 is turned on, the input current Ip increases in the form of a sine wave while the current flows in a direction larger than 0 and the voltage of the resonant capacitor Cr increases do. Conversely, when the upper switch M1 is turned on and the lower switch M2 is turned off, the input current Ip decreases in the form of a sine wave, but becomes less than zero, and the flow direction thereof changes. Then, the voltage of the resonant capacitor Cr decreases.

The switch driver 200 includes an upper gate driver 210 and a lower gate driver 220. The upper gate driver 210 generates the gate signal VG1 for controlling the switching operation of the upper switch M1 and the lower gate driver 220 generates the gate signal VG2 for controlling the switching operation of the lower switch M2. . The upper switch Ml and the lower switch M2 according to the embodiment of the present invention are turned on / off alternately according to a predetermined duty. There is a predetermined dead time period in which both the upper switch M1 and the lower switch M2 are turned off. Therefore, the gate signal VG1 and the gate signal VG2 alternately become high-level signals, and there is a dead-time period in which both signals are low-level. The upper gate driver 210 is connected to both ends of the bootstrap capacitor CH and receives power required for operation from the bootstrap capacitor CH. The upper gate driver 210 receives the one end voltage HV of the bootstrap capacitor CH and the other end voltage VCTR of the bootstrap capacitor CH and generates the gate signal VG1. The switch driver 200 and the lower gate driver 220 are supplied with power necessary for operation from the power supply voltage Vcc. The abnormal switching monitoring apparatus 400 determines whether the zero voltage switching of the lower switch M2 has been normally performed using the voltage across the resistor RD and the gate signal VG2. The abnormal switching monitoring apparatus 400 determines abnormal zero voltage switching when the time when the charging current ID begins to flow into the bootstrap capacitor CH is later than the turn-on time of the lower switch M2. In order for the charge current (ID) to start flowing to the bootstrap capacitor (CH), the diode (DB) must be turned on. The diode (DB) is also turned on when the voltage (HV) is lower than the power supply voltage (Vcc). Since the voltage HV is higher than the voltage charged in the bootstrap capacitor CH from the voltage VCTR, if the voltage VCTR is high, the voltage HV is also high. Therefore, in order for the voltage HV to be lower than the power supply voltage Vcc, the voltage VCTR must first be lower than the voltage obtained by subtracting the voltage VCH of the capacitor CH from the power supply voltage Vcc. Then, the voltage HV becomes lower than the power supply voltage Vcc and the diode DB is turned on. The voltage VCTR is equal to the drain-source voltage VDS of the lower switch M2. Zero voltage switching occurs when the drain-source voltage (VDS) is zero. However, even when the voltage VCTR is higher than the voltage (Vcc-VCH) obtained by subtracting the voltage VCH from the power supply voltage Vcc, the lower switch M2 may be turned on, indicating abnormal zero voltage switching. The present invention uses this to determine whether the abnormal switch of the lower switch M2 is switched.

Specifically, the abnormal switching monitoring apparatus 400 includes a comparator 410, an AND gate 420, and a power supply circuit 430 for supplying power to the upper gate driver 210. The power supply circuit 430 includes a resistor RD, a diode DB and a bootstrap capacitor CH. The resistor RD, the diode DB and the bootstrap capacitor CH are connected in series, the power supply voltage Vcc is transmitted to the resistor RD, the bootstrap capacitor CH is connected to the upper switch M1, And is connected to the switch M2. The inverting terminal (-) of the comparator 410 is connected to one end of the resistor RD, and the power supply voltage Vcc is input. The other end of the resistor RD is connected to the non-inverting terminal (+) of the comparator 410. The anode electrode of the diode DB is connected to the other end of the resistor RD and the cathode electrode of the diode DB is connected to one end of the bootstrap capacitor CH. Therefore, current flows only in the direction of charging the bootstrap capacitor CH. When the charge current flows through the bootstrap capacitor CH, a voltage drop occurs across the resistor RD. If the charge current does not flow into the bootstrap capacitor CH, no voltage drop occurs in the resistor RD. Then, the voltage at the other end of the resistor RD is equal to the power supply voltage Vcc. The comparator 410 according to the embodiment of the present invention outputs a high level signal when the voltage of the non-inverting terminal (+) is equal to or higher than the voltage of the inverting terminal (-). The output signal of the comparator 410 is hereinafter referred to as a charge pulse CP. When the charge current ID flows through the bootstrap capacitor CH, the charge pulse CP does not occur and a charge pulse CP having a high level is generated during a period in which no charge current flows through the bootstrap capacitor CH do. The AND gate 420 generates an anomaly detection signal NZS informing abnormal zero voltage switching in a section where the gate signal VG2 and the charge pulse CP are both at the high level. That is, when the lower switch M2 is turned on during a period in which the charging current (ID) does not flow, the abnormal switching monitoring apparatus 400 determines that the abnormal zero voltage switching is performed.

2 and 3 are views showing signals generated in the converter and the switch driver 200 according to the embodiment of the present invention. 2 is a diagram showing signals generated in the converter and the switch driver 200 when zero voltage switching is performed. 3 is a diagram showing signals generated in the converter and the switch driver 200 in the case of abnormal zero voltage switching. The voltages VCTR1 and VCTR2 are the same as the drain-source voltage VDS of the lower switch M2.

In FIG. 2, VCTR1, ID1, VCH1 and CP1 normally occur when zero voltage switching is performed, and VCTR2, ID2, VCH2 and CP2 occur when zero voltage switching fails. First, the normal case will be explained.

When the voltage VCTR1 reaches the voltage obtained by subtracting the voltage VCH1 of the bootstrap capacitor CH from the power supply voltage Vcc at the time point T1, the voltage HV also reaches the power supply voltage Vcc, And the charging current ID1 starts flowing to the diode DB. The bootstrap capacitor CH starts to be charged by the charge current ID1, and the voltage VCH1 of the bootstrap capacitor CH starts to increase. When the charging current ID1 starts flowing, the voltage of the inverting terminal (-) of the comparator 410 becomes higher than the voltage (+) of the non-inverting terminal, and the charging pulse CP1 becomes low level.

When the lower gate signal VG2 becomes a high level at a time point T2 and the lower gate signal VG2 becomes a low level at a time point T3, the lower switch M2 is turned off . The voltage VCTR1 starts to increase from the time point T3 and the voltage VCTR1 reaches the voltage obtained by subtracting the voltage VCH1 of the bootstrap capacitor CH from the power source voltage Vcc at the time point T4. During the period from the time point T1 to the time point T4, the bootstrap capacitor CH is charged by the charge current ID1, and the voltage VCH1 increases. As the voltage VCH1 increases, the charging current ID1 gradually decreases as the voltage HV increases and the difference from the power supply voltage Vcc decreases. When the voltage VCTR1 that has increased from the time point T3 after the lower switch M2 is turned off becomes larger than the voltage Vcc-VCH1 after reaching the voltage Vcc-VCH1 at the time point T4, the diode DB is turned And the charging current ID1 no longer flows. Then, the voltage VCTR1 rises after the time point T3 and rises to a predetermined voltage, and remains at a constant level until the upper switch M1 is turned off. Since the charging current ID1 does not flow at the time point T4, the voltage of the non-inverting terminal of the comparator 410 becomes equal to the voltage of the inverting terminal, and the charging pulse CP1 becomes the high level.

When the upper switch Ml is turned off at the time point T5, the voltage VCTR1 starts to decrease and reaches the voltage Vcc-VCH1 at the time point T6. Since the charging current ID1 flows at the time point T6, the voltage of the inverting terminal (-) of the comparator 410 becomes higher than the voltage of the non-inverting terminal (+), and the charging pulse CP becomes the low level. When the lower gate signal VG2 becomes high level at the time point T7, the lower switch M2 is turned on again.

In this way, when the zero voltage switching is normally performed, the time when the lower switch M2 is turned on is later than the time when the voltage VCTR1 reaches the voltage Vcc-VCH1 and the charging current ID1 is generated. Therefore, since the lower gate signal VG2 and the charge pulse CP1 input to the AND gate 420 are not simultaneously at a high level, the AND gate 420 outputs a low level abnormality detection signal NZS). If the anomaly detection signal NZS is at a low level, it means that zero voltage switching is performed.

Next, the case of zero voltage switching failure will be described with reference to FIG.

When the lower gate signal VG2 becomes high level at the time T11, the lower switch M2 is turned on. At time T12, when the voltage VCTR2 reaches a voltage obtained by subtracting the voltage VCH2 of the bootstrap capacitor CH from the power supply voltage Vcc and then decreases, the voltage HV reaches the power supply voltage Vcc at the time T12. And becomes smaller than the power supply voltage Vcc thereafter. Then, the diode (DB) is turned on, and the charging current (ID2) starts flowing from the time point T12 to the diode (DB). The bootstrap capacitor CH starts to be charged by the charge current ID2, and the voltage VCH2 of the bootstrap capacitor CH starts to increase. When the charging current ID2 starts to flow, the voltage of the inverting terminal (-) of the comparator 410 becomes higher than the voltage of the non-inverting terminal (+), and the charging pulse CP2 becomes the low level at the time T12. Since the charging pulse CP2 and the lower gate signal VG2 are both at the high level during the period T11-T12, the AND gate 420 generates the high level abnormality sensing signal NZS. That is, it means abnormal zero voltage switching.

As described above, the rising edge timing of the charge current ID2 charging the lower gate signal VG2 and the bootstrap capacitor CH can be compared to determine whether the abnormal zero voltage switching is performed.

Although the abnormal switching monitoring apparatus and monitoring method of the lower switch have been described so far, the abnormal switching monitoring apparatus and monitoring method of the upper switch will be described below with reference to FIG. 4 and FIG.

FIG. 4 is a diagram illustrating an abnormal switching monitoring apparatus 400 'of an upper switch M1 according to another embodiment of the present invention. The same reference numerals are used for the same components as those of the previous embodiment.

When the time point at which the charge current ID` for charging the bootstrap capacitor CH` does not flow is later than the time point when the upper switch M1 is turned on, the upper switch M1 switches the abnormal zero voltage. That is, the time point at which the voltage VCTR 'rises from the power supply voltage Vcc to the voltage (Vcc-VCH`) obtained by subtracting the voltage VCH' of the capacitor CH` is lower than the turn- In this case, the upper switch M1 is subjected to abnormal zero voltage switching. The voltage across the upper switch M1 is a voltage corresponding to the difference between the input voltage Vin and the voltage VCTR` and the voltage VCTR` is the voltage obtained by subtracting the capacitor voltage VCH` from the power supply voltage Vcc Vcc-VCH`), the voltage across the upper switch M1 is higher than the zero voltage.

The abnormal switching monitoring apparatus 400 'has a function of comparing a signal inputted to the inverting terminal (-) and the non-inverting terminal (+) of the comparator 410' and the signal inputted to the AND gate 420 ', as compared with the abnormal switching monitoring apparatus 400, Only the signal inputted to the input terminal is different, but the other configurations are the same. When the voltage of the non-inverting terminal (+) of the comparator 410 'is equal to or lower than the voltage of the inverting terminal (-), the comparator 410' generates a low level charging pulse CP ' . A description that is the same as the above-described embodiment will be omitted.

The inverting terminal (-) of the comparator 410 'is connected to the anode electrode of the diode DB and one end of the resistor RD', and the non-inverting terminal (+) is connected to the other end of the resistor RD ' . Therefore, when the charging current ID 'flows in the resistor RD', the voltage of the inverting terminal (-) becomes lower than the voltage of the non-inverting terminal (+) due to the voltage drop, and the high level charging pulse CP 'is outputted. The voltage of the non-inverting terminal (+) and the inverting terminal (-) of the comparator 410 'is set to be the same as the voltage of the non-inverting terminal (+) of the comparator 410' same. Then, the comparator 410 'outputs a low level signal. The AND gate 420` generates an anomaly detection signal NZS` indicating an abnormal zero voltage switching in a section where the upper gate signal VG1 and the charging pulse CP` are both at a high level. That is, when the upper switch M1 is turned on during the period in which the charge current (Id`) flows, the abnormal switch monitoring apparatus 400 'determines that the abnormal zero voltage switching is performed.

5 is a diagram illustrating a case where an abnormal switching monitoring apparatus 400 'according to another embodiment of the present invention detects a zero voltage switching failure and generates an anomaly detection signal NZS' having a high level pulse. The voltage VCH` charged in the bootstrap capacitor CH` is set to `VCH3` and the voltage VCTR` at the other end of the bootstrap capacitor CH` is set to` VCTR3` in order to distinguish it from the previous embodiment , And the charging current (ID`) is indicated by "ID3".

As shown in Fig. 5, when the upper gate signal VG1 becomes high level at the time point T21, the upper switch M1 is turned on. When the voltage VCTR3 becomes greater than the voltage Vcc-VCH3 obtained by subtracting the voltage VCH3 of the bootstrap capacitor CH` from the power supply voltage Vcc at the time T22, the voltage HV ' (Vcc). Then, after the time point T22, the diode (DB`) is shut off and the charging current (ID3) flows to the diode (DB`) to the time point T22. Therefore, the charge pulse CP 'occurs up to the time point T22. During the periods T21-T22, both the charge pulse CP 'and the upper gate signal VG1 are at the high level, so that the AND gate 420` generates the high level abnormality sensing signal NZS'. That is, it means abnormal zero voltage switching.

As described above, whether or not the zero voltage switching fails can be determined by using the upper gate signal VG1 and the charging current ID '.

While the resistors (RD, RD) have been used to detect the current flowing through the bootstrap capacitor, the present invention is not limited thereto, and other devices capable of sensing the current can be used.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It belongs to the scope of right.

1 is a block diagram of a converter to which an abnormal switching monitoring apparatus according to an embodiment of the present invention is applied.

2 is a diagram showing signals generated in the converter and the switch control unit when zero voltage switching is performed.

3 is a diagram showing signals generated in the converter and the switch control unit in the case of abnormal zero voltage switching.

4 is a diagram illustrating an upper switch abnormal monitoring apparatus according to another embodiment of the present invention.

5 is a diagram illustrating a case where an abnormal switching monitoring apparatus according to another embodiment of the present invention detects abnormal voltage switching and generates an anomaly detection signal having a high level pulse.

Claims (18)

An abnormal switching monitoring apparatus for monitoring a non-zero voltage switching of a lower switch connected to a second electrode of an upper switch including a first electrode to which an input voltage is input, And a power supply for supplying an operating current to a gate driver for controlling the switching operation of the upper switch, Wherein the controller determines whether the abnormal switch of the lower switch is switched by comparing a time point at which a current starts to flow to the power supply unit and a time point at which the lower switch is turned on. The method according to claim 1, The power supply unit, A bootstrap capacitor connected to the gate driver for supplying an operation current, A diode that causes current to flow to the bootstrap capacitor, and And a current sensing element having one end connected to a power supply voltage and the other end connected to the diode. 3. The method of claim 2, Wherein the current sensing device is a resistor. 3. The method of claim 2, The bootstrap capacitor has one end connected to the cathode electrode of the diode, the other end of the bootstrap capacitor connected to the second electrode of the upper switch, the anode electrode of the diode connected to the other end of the current sensing device Abnormal switching monitoring device. 3. The method of claim 2, And comparing the voltage of each of the two ends of the current sensing element and logic operation of the comparison result and the lower gate signal controlling the lower switch to determine whether the abnormal zero voltage is switched. 6. The method of claim 5, A comparator including an inverting terminal to which the power supply voltage is inputted and a non-inverting terminal connected to the other end of the current sensing device; And an AND gate connected to the output terminal of the comparator and receiving the lower gate signal. The method according to claim 1, And when the time point at which the charging current begins to flow is later than the time point when the lower switch is turned on, the abnormal switching monitoring device determines the abnormal zero voltage switching. An abnormal switching monitoring apparatus for monitoring a non-zero voltage switching of an upper switch including a first electrode to which an input voltage is input, And a power supply for supplying an operating current to a gate driver for controlling the switching operation of the upper switch, The abnormal switching monitoring device judges whether or not the abnormal switch of the upper switch is switched by comparing a time point when the current does not start flowing to the power supply unit and a time point when the upper switch is turned on. 9. The method of claim 8, The power supply unit, A bootstrap capacitor connected to the gate driver for supplying an operation current, A diode that causes current to flow to the bootstrap capacitor, and And a current sensing element having one end connected to a power supply voltage and the other end connected to the diode. 10. The method of claim 9, Wherein the current sensing device is a resistor. 10. The method of claim 9, The bootstrap capacitor has one end connected to the cathode electrode of the diode, the other end of the bootstrap capacitor connected to the second electrode of the upper switch, the anode electrode of the diode connected to the other end of the current sensing device Abnormal switching monitoring device. 10. The method of claim 9, And comparing the voltage of each of the current sensing elements with the voltage of each of the current sensing elements to logically compare the comparison result and an upper gate signal for controlling the upper switch to determine whether the abnormal zero voltage is switched. 13. The method of claim 12, A comparator including a non-inverting terminal to which the power supply voltage is inputted and an inverting terminal connected to the other end of the current sensing device; And an AND gate connected to the output terminal of the comparator and receiving the upper gate signal. 9. The method of claim 8, The abnormal switching monitoring device judges the abnormal zero voltage switching if the time when the charging current starts not to flow is later than the time when the upper switch is turned on. An abnormal switching monitoring method for monitoring abnormal voltage switching of a lower switch connected to a second electrode of an upper switch including a first electrode to which an input voltage is input, Sensing a charge current flow for charging a bootstrap capacitor for supplying an operating current to a gate driver for controlling a switching operation of the upper switch; Comparing a time point at which the lower switch is turned on and a point at which the charging current starts flowing; And And determining whether the abnormal switch of the lower switch is switched according to the comparison result. 16. The method of claim 15, Wherein the step of determining whether the abnormal switch of the lower switch is abnormal may include: And when the time point at which the charging current starts flowing is later than the time of the lower switch turn-on time, the abnormal switching control is performed. An abnormal switching monitoring method for monitoring abnormal voltage switching of an upper switch including a first electrode to which an input voltage is input, Sensing a charge current flow for charging a bootstrap capacitor for supplying an operating current to a gate driver for controlling a switching operation of the upper switch; Comparing a time when the upper switch is turned on and a time when the charging current starts not flowing; And And determining whether the abnormal switch of the upper switch is abnormal according to a result of the comparison. 18. The method of claim 17, Wherein the step of determining whether the abnormal switch of the upper switch is abnormal may include: And determining that the abnormal zero voltage switching is performed when the time when the charging current starts not flowing is later than the upper switch turn-on time.

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