KR101456268B1 - Light emitting diode chip capable of being packaged without wire bonding, light emitting diode package using same, manufacturing method of light emitting diode chip, and manufacturing method of light emitting diode package - Google Patents

Abstract

An LED chip capable of being packaged without wire bonding is disclosed. Such an LED chip includes an LED cell including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, and a second conductive semiconductor layer disposed apart from one side of the LED cell so as to be parallel to a stacking direction of the LED cell, An LED cell including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, and a second conductive semiconductor layer disposed apart from one side of the LED cell so as to be parallel to a stacking direction of the LED cell, And a second via which is disposed on the other side of the LED cell where the first via is not disposed and is electrically connected to the second conductive semiconductor layer so as to be parallel to the stacking direction of the LED cell. Thus, the present invention can prevent the problem of package failure due to wire bonding, and it is possible to manufacture a white LED through application of a phosphor after attaching a die in a package.

LED, Package, Wire, Bonding, Via

Description

TECHNICAL FIELD [0001] The present invention relates to a light emitting diode chip package capable of being packaged without wire bonding, a light emitting diode package using the light emitting diode package, a method of manufacturing the light emitting diode chip, and a method of manufacturing the light emitting diode package. THE LIGHT EMITTING DIODE CHIP AND FABRICATING METHOD OF THE LIGHT EMITTING DIODE PACKAGE}

More particularly, the present invention relates to a light emitting diode (LED) chip that can be packaged without wire bonding, a light emitting diode package using the same, a method of manufacturing the light emitting diode chip, and a method of manufacturing the light emitting diode package.

A light emitting diode is a semiconductor PN junction device, which is a typical light emitting device that converts electrical energy into light energy. When a current is applied, it is a PN junction (P-N junction) or an element in which electrons and holes meet and emit light in the active layer. Such a light emitting diode is usually fabricated as a package in which a light emitting diode chip (hereinafter referred to as "LED chip") is mounted, which is often referred to as an "LED package".

Looking at a conventional LED package in which an LED chip is mounted, the connection between the terminal of the LED package and the LED chip has conventionally been achieved through wire bonding. For example, one electrode of the LED chip is directly connected to the chip attaching portion of the LED package and connected to the first terminal portion of the LED package, and the other electrode of the LED chip is connected to the second terminal portion of the LED package through wire bonding (Here, it is defined as a "vertical LED chip"), and a chip in which both electrodes of the LED chip are connected to the first terminal and the second terminal portion of the LED package by wire bonding Quot; horizontal LED chip ").

However, in the case of designing a package using wire bonding in this way, there are many problems caused by defects of the wire bonding itself, and it is inconvenient when a phosphor is applied in a package state.

Accordingly, it is an object of the present invention to provide a method of manufacturing a light emitting diode package, in which wire bonding is used to electrically connect an LED chip and a package when mounted on a package, And to provide a package that can be packaged.

Another object of the present invention is to provide a light emitting device capable of being packaged without wire bonding to improve the difficulty in applying a phosphor after attaching a die in a package in case of using wire bonding for electrically connecting an LED chip and a package when mounted on a package And a diode chip.

According to an aspect of the present invention, there is provided an LED chip comprising: an LED cell including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; And vias electrically connected to the second conductive semiconductor layer, the first conductive semiconductor layer being disposed on one side of the LED cell so as to be parallel to the stacking direction of the LED cells.

Here, an insulating layer may be interposed between the LED cell and the via, and the second conductive semiconductor layer and the via may be electrically connected through the first metal electrode.
And a second metal electrode disposed on a lower surface of the first conductive semiconductor layer.
The via may be a conductive metal such as Ag or graphite or a non-metallic conductive material.
The insulating layer may be a non-conductive material such as a metal oxide or a polymer organic material.
The present invention also provides an LED cell including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; A first via disposed on one side of the LED cell so as to be parallel to the stacking direction of the LED cells, the first via being electrically connected to the first conductive semiconductor layer; And a second via electrically isolated from the other side of the LED cell so as to be parallel to the stacking direction of the LED cell and electrically connected to the second conductive semiconductor layer.
A first insulating layer interposed between the LED cell and the first via; A second insulating layer interposed between the LED cell and the second via; A first metal electrode for electrically connecting the first conductive semiconductor layer and the first via; And a second metal electrode for electrically connecting the second conductive semiconductor layer and the second via.
And a third metal electrode located under the first conductive semiconductor layer, wherein the third metal electrode is electrically connected to the first via.
The first and second vias may be a conductive metal such as Ag or graphite or a non-metallic conductive material.
The first and second insulating layers may be nonconductive materials such as a metal oxide or a polymer organic material.
A package substrate including first and second electrodes spaced apart from each other by a predetermined distance; And an LED cell including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer mounted on the substrate, wherein the first conductive semiconductor layer is located on the first electrode, And the via is electrically connected to the second conductive semiconductor layer, the via being spaced apart from the LED cell at one side of the LED cell so as to be parallel to the stacking direction of the LED cell, Respectively.
An insulating layer is interposed between the LED cell and the via, and the second conductive semiconductor layer and the via are electrically connected through the first metal electrode.
And a second metal electrode disposed between the first conductive semiconductor layer and the first electrode.
The via may be a conductive metal such as Ag or graphite or a non-metallic conductive material.
The insulating layer may be a non-conductive material such as a metal oxide or a polymer organic material.
The present invention also relates to a package substrate comprising first and second electrodes spaced apart from each other by a predetermined distance; And an LED cell including a substrate, a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer disposed on the package substrate, wherein the LED cell is arranged in parallel with the stacking direction of the LED cells, A first via disposed on one side of the first conductive semiconductor layer and electrically connected to the first conductive semiconductor layer; And a second via disposed on the other side of the LED cell so as to be parallel to the stacking direction of the LED cell, the second via being electrically connected to the second conductive semiconductor layer, wherein the first via is electrically connected to the first electrode And the second via is electrically connected to the second electrode.
A first insulating layer interposed between the LED cell and the first via; A second insulating layer interposed between the LED cell and the second via; A first metal electrode for electrically connecting the first conductive semiconductor layer and the first via; And a second metal electrode for electrically connecting the second conductive semiconductor layer and the second via.
And a third metal electrode located below the substrate, wherein the third metal electrode is electrically connected to the first via.
The first and second vias may be a conductive metal such as Ag or graphite or a non-metallic conductive material.
The first and second insulating layers may be nonconductive materials such as a metal oxide or a polymer organic material.
The present invention also provides a method of manufacturing an epitaxial wafer, comprising: preparing an epitaxial wafer; Forming holes at predetermined intervals so that the first conductive semiconductor layer, the active layer, and the second conductive semiconductor layer on the epitaxial wafer are exposed to the inside; Forming an insulating layer on side walls in the hole; Filling the hole in which the insulating layer is formed with a conductive material to form a via; Forming a metal electrode for electrically connecting the second conductive semiconductor layer and the via; And cutting along the vias.
Preparing an epitaxial wafer; Forming holes at predetermined intervals so that the first conductive semiconductor layer, the active layer, and the second conductive semiconductor layer on the epitaxial wafer are exposed to the inside; Forming an insulating layer on side walls in the hole; Filling the hole in which the insulating layer is formed with a conductive material to form a via; Etching the first conductive semiconductor layer so that the first conductive semiconductor layer is exposed stepwise compared to the second conductive semiconductor layer by etching the insulating layer adjacent to the via and the adjacent region of the adjacent insulating layer by etching the vias one by one; A first metal electrode for electrically connecting the stepped-exposed first conductive semiconductor layer and the etched via, and a second metal electrode electrically connecting the unetched via and the second conductive semiconductor layer to each other, ; And cutting the etched vias and the etched vias along the centerline of each via.
A hole is formed at a predetermined interval so that the first conductive semiconductor layer, the active layer, and the second conductive semiconductor layer on the epitaxial wafer are exposed to the inside, an insulating layer is formed on the side wall in the hole, Filling the material to form a via, forming a metal electrode for electrically connecting the second conductive semiconductor layer and the via, and cutting the via along the via; Mounting the LED chip on a package substrate; And applying a phosphor on the LED chip.
A hole is formed at a predetermined interval so that the first conductive semiconductor layer, the active layer, and the second conductive semiconductor layer on the epitaxial wafer are exposed to the inside, an insulating layer is formed on the side wall in the hole, Filling the material to form vias, etching the insulating layer adjacent to the vias to be etched and etched one by one and the adjacent regions of the adjacent insulating layer so that the first conductive semiconductor layer is exposed to the second conductive semiconductor layer A first metal electrode for electrically connecting the stepped exposed first conductive semiconductor layer and the etched via is formed, and the unetched vias and the second conductive semiconductor layer are electrically connected to each other Forming a second metal electrode connecting the etched vias and the etched vias, Preparing an LED chip including the step of cutting such nutrients along the center line O of; Mounting the LED chip on a package substrate; And applying a phosphor on the LED chip.

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As described above, the present invention provides an LED chip that can be packaged without wire bonding, so that when wire bonding is used to electrically connect an LED chip and a package when mounted on a package, a wire short- the problem of package failure due to short or open can be solved.

Further, the present invention provides an LED chip that can be packaged without wire bonding, thereby improving the inconvenience caused by conventional wire bonding when a phosphor is applied in a packaged state, thereby manufacturing a white LED using various phosphor coating methods .

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed and will become apparent to persons skilled in the art upon a reading of the present disclosure. It will not be used. In addition, the relative sizes of the individual components on the drawings are exaggerated for ease of explanation and understanding.

1 is a schematic cross-sectional view of an LED chip 10 that can be packaged without wire bonding according to an embodiment of the present invention. 1, an LED chip 10 includes an LED cell 12 including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; a plurality of LED cells 12 parallel to the stacking direction of the LED cells 12; And a via 16 electrically connected to the second conductive semiconductor layer.

The LED cell 10 may include a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer in order from the bottom to the top in FIG. 1, although the LED cell 10 is not detailed in the drawing. For example, the first conductive semiconductor layer may be a layer doped with an N-type impurity, and the second conductive semiconductor layer may be a layer doped with a P-type impurity. The active layer is a layer in which light is emitted by the combination of electrons and holes. Further, the LED cell 10 may further include a substrate, a buffer layer, and the like, but is not an important element in describing the present invention, and thus will not be described in detail below.

The vias 16 are arranged in parallel to the direction in which the LED cells 12 are stacked, wherein the direction of stacking the LED cells 12 is the direction in which the first conductive semiconductor layer, the active layer, Direction is generally perpendicular to the direction. The via 16 may be a conductive metal, but it is not limited to metal, but may be any conductive material. For example, the via 16 may be silver (Ag) or graphite.

An insulating layer 14 may be further interposed between the via 16 and the LED cell 12 to insulate the LED cell 12 from the via 16. More specifically, the insulation herein means insulation of the LED cell 12 with the first conductive semiconductor layer and the active layer. The insulating layer 14 is sufficient for the insulating material of the nonconductive material to effectively isolate the LED cell 12 and the via 16. [ For example, the insulating layer 14 may be made of a metal oxide or a polymer organic material, but is not limited thereto.

The second conductive semiconductor layer of the LED cell 12 and the via 16 may be electrically connected through the metal electrode 18.

The lower end of the LED cell 12 (shown in FIG. 1) is connected to one of the electrode terminals (also shown in FIG. 1) of the LED package through the metal electrode 19, 5), and the lower end of the via 16 is connected to the other electrode terminal (see 54 in Fig. 5) of the LED package.

Accordingly, by providing the LED chip capable of being packaged without wire bonding according to an embodiment of the present invention, wire bonding between the metal electrode 18 and the electrode terminal of the LED package is inevitable in the case of the conventional vertical LED chip, The problem of a package failure that has occurred due to the occurrence of a failure can be solved.

2A to 2E are process cross-sectional views schematically illustrating a method of manufacturing an LED chip that can be packaged without wire bonding according to an embodiment of the present invention. 2A to 2E, a method of manufacturing an LED chip that can be packaged without wire bonding according to an embodiment of the present invention includes the steps of preparing an epi-epitaxial wafer (FIG. 2A) A step (FIG. 2B) of forming holes at predetermined intervals such that the first conductive semiconductor layer, the active layer, and the second conductive semiconductor layer are exposed inward; a step (FIG. 2C) (FIG. 2E) filling the conductive material in the via hole (FIG. 2E) to form a via, forming a metal electrode (FIG. 2E) for electrically connecting the second conductive semiconductor layer and the via, ).

2A schematically shows a cross section of a portion 22 of an epi-epitaxial wafer. The epitaxial wafer refers to a wafer on which a P layer, an active layer and an N layer are formed on a substrate (for example, GaAs) under specific conditions. Such an epitaxial wafer may be a wafer, Since it is well known, further detailed description is omitted.

FIG. 2B is a view showing a state in which a hole is formed in the epitaxial wafer of FIG. 2A, wherein a plurality of holes 23a, 23b, 23c and 23d are formed at predetermined intervals. In each of the plurality of holes 23a, 23b, 23c, and 23d, a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer (each layer is not specifically divided, but collectively referred to as 22a, 22b, 22c, 22d, and 22e, each of which is defined as one LED cell) is exposed to the inside of each of the plurality of holes 23a, 23b, 23c, and 23d.

Fig. 2C is a drawing showing a part of the state in which the insulating layer is formed on the side wall in the hole of Fig. 2B. Fig. 2C is a plan view of the insulating layer on the side of the LED cell exposed to the inner side wall of each of the plurality of holes 23a, 23b, 23c, By forming the layers 24a and 24b, the sides of the LED cell are not exposed to the respective holes. These insulating layers 24a and 24b serve to insulate the conductive material filled in the holes from the LED cells.

FIG. 2 (d) illustrates a state in which vias 26a and 26b are formed by filling a conductive material into the holes formed with the insulating layers 24a and 24b in FIG. 2c. After filling the conductive material, the LED cell 22a and the The LED cell 22a, the insulating layer 24a, the via 26a, the insulating layer 24a, and the LED cell 22b are sequentially viewed in cross section between the LED cells 22b.

2E shows a state in which metal electrodes 28a, 28b, 29a and 29b for electrically connecting the second conductive semiconductor layer and the vias 26a and 26b of the LED cells 22a and 22b are formed in FIG. 2D The metal electrodes 28a and 28b are not specifically defined but the metal electrodes 28a and 28b are not specifically defined but are electrically connected to the second conductive semiconductor layers of the LED cells 22a and 22b via the insulating layers 24a and 24b, And the upper portion is electrically connected.

After the metal electrodes 28a, 28b, 29a and 29b are formed, a step of cutting along the cutting lines C1 and C2 substantially parallel to the vias 26a and 26b is performed. The cutting process is preferably performed within the range of the insulating layer 24a between the via 26a and the LED cell 22b. Then, a step of removing the cut portion between the insulating layers 26a and 22b may be added after the cutting process.

Thus, the present invention makes it possible to manufacture a packageable LED chip (10 in FIG. 1) without requiring wire bonding by including the above-described processes.

3 is a schematic cross-sectional view of a packageable LED chip without wire bonding according to another embodiment of the present invention. 3, the LED chip 30 includes an LED cell 35 including a first conductive semiconductor layer 32, an active layer 33 and a second conductive semiconductor layer 34, A first via 37a which is disposed on one side of the LED cell 35 and is electrically connected to the first conductive semiconductor layer 32 so as to be parallel to the direction of the LED cell 35, And a second via 37b disposed on the other side of the LED cell 35 on which the first conductive semiconductor layer 37a is not disposed and electrically connected to the second conductive semiconductor layer 34. [

The LED cell 35 includes the first conductive semiconductor layer 32, the active layer 33, and the second conductive semiconductor layer 34, and may include the substrate 31 as shown in FIG. The first conductive semiconductor layer 32 may be a layer doped with an n-type impurity, and the second conductive semiconductor layer 34 may be a layer doped with a p-type impurity, for example, And the active layer 33 is a layer in which light is emitted by the combination of electrons and holes.

The first vias 37a are arranged so as to be parallel to the stacking direction of the LED cells 35. The direction in which the LED cells 35 are stacked is the direction in which the substrate 31, the first conductive semiconductor layer 32, the active layer 32 And the direction of the surface on which the second conductive semiconductor layer 34 is arranged. The first vias 37a are electrically connected to the first conductive semiconductor layer 32 of the LED cell 35 and the other portions (the substrate 31, the active layer 33, and the second conductive semiconductor layer 34) Should be insulated. 3, the length of the first via 37a arranged along the stacking direction of the LED cells 35 does not exceed the length up to the first conductive semiconductor layer 32 of the LED cell 35 .

In addition, a first metal electrode 38a for electrically connecting the first conductive semiconductor layer 32 and the first via 37a is further provided. The first metal electrode 38a electrically connects one end of the first via 37a and the exposed portion of the first conductive semiconductor layer 32, which is exposed stepwise upwardly as compared with the second conductive semiconductor layer 34, do.

Further, a first insulating layer 36a may be further interposed between the LED cell 35 and the first via 37a to insulate the LED cell 35 from the first via 37a.

The second vias 37b are arranged so as to be parallel to the direction in which the LED cells 35 are stacked, and the positions are arranged on the other side of the LED cell 35 in which the first vias 37a are not disposed. Also, the electrical connection between the second conductive semiconductor layer 34 and the second via 37b is made through the second metal electrode 38b. Therefore, it is preferable that a second insulating layer 36b is interposed between the second vias 37b and the LED cell 35.

As the material used for the first via 37a and the second via 37b, a conductive material such as a conductive metal or a conductive nonmetal can be used. For example, it may be silver (Ag) or graphite.

Each of the first insulating layer 36a and the second insulating layer 36b may be formed of a material capable of effectively insulating the LED cell 35 and the first via 37a and between the LED cell 35 and the second via 37b An insulator of nonconductive material is sufficient. For example, the insulating layers 36a and 36b may be made of a metal oxide or a polymer organic material, but are not limited thereto.

An electrode pad 39 is further formed on the lower end of the LED cell 35 so that the second via 37b is electrically connected to the electrode terminal 64 of the LED package.

3 is a horizontal LED chip as previously categorized. The lower end of the via 37a (shown in Fig. 3) is connected to a first terminal portion (not shown) of the LED package, (Not shown) of the LED package through the electrode pad 39. The second terminal portion 37b is connected to the second terminal portion (not shown)

Accordingly, by providing the LED chip that can be packaged without wire bonding according to an embodiment of the present invention, wire bonding between the metal electrodes 38a and 38b and terminal portions of the LED package in the conventional horizontal type LED chip is inevitable This makes it possible to solve the problem of package failure which has occurred frequently.

4A to 4F are process cross-sectional views schematically illustrating a method of manufacturing a LED chip that can be packaged without wire bonding according to another embodiment of the present invention. 4A to 4F, a method of manufacturing an LED chip that can be packaged without wire bonding according to another embodiment of the present invention includes the steps of preparing an epitaxial wafer (FIG. 4A), forming a first conductive semiconductor layer Forming a hole at a predetermined distance so as to expose the active layer and the second conductive semiconductor layer inward (FIG. 4B), forming an insulating layer on the side wall of the hole (FIG. 4C), forming a conductive material (FIG. 4D). The insulating layer adjacent to the vias to be etched and etched, and the adjacent region of the adjacent insulating layer are etched so that the first conductive semiconductor layer is in contact with the second conductive semiconductor layer (FIG. 4E), a first metal electrode for electrically connecting the stepped exposed first conductive semiconductor layer and the etched via is formed, and etching (FIG. 4F) for electrically connecting the non-etched vias and the second conductive semiconductor layer (FIG. 4F), cutting the etched vias and the etched vias along the centerline of each via (Fig. 4F).

4A shows a portion of an epitaxial wafer. The epitaxial wafer includes a substrate 41, a first conductive semiconductor layer 42, an active layer 43, and a second conductive semiconductor layer 44. The first conductive semiconductor layer 42 may be a layer doped with an n-type impurity and the second conductive semiconductor layer 44 may be a layer doped with a p-type impurity.

FIG. 4B is a view showing a state where holes are formed in the epitaxial wafer of FIG. 4A, and a state in which a plurality of holes 45a, 45b, 45c, and 45d are formed at predetermined intervals is shown. In each of the plurality of holes 45a, 45b, 45c and 45d, the first conductive semiconductor layers 42a, 42b, 42c, 42d and 42e on the epitaxial wafer, the active layers 43a, 43b, 43c, 43d and 43e, The conductive semiconductor layers 44a, 44b, 44c, 44d, and 44e are exposed to the inside of the plurality of holes 45a, 45b, 45c, 45d, and 45e. The substrates 41a, 41b, 41c, 41d, and 41c are also exposed to the inside of each of the plurality of holes 45a, 45b, 45c, and 45d.

4C is a view showing a state in which an insulating layer is formed on the side wall in the hole of FIG. 4B. The insulating layers 46a, 46b, and 46c are formed on the sides of the LED cell exposed to the inside of each of the plurality of holes 45a, 45b, 45c, 46c, 46d, 46e are formed so that the sides of the LED cell are not exposed to the respective holes. These insulating layers 46a, 46b, 46c, 46d and 46e serve to insulate the LED cells from the conductive material filled in the respective holes 45a, 45b, 45c, 45d and 45e.

4D is a view showing a state in which vias 47a, 47b, 47c, 47d and 47e are formed by filling a conductive material into holes in which the insulating layers 46a, 46b, 46c, 46d and 46e are formed The LED cell, the insulating layer 46a, the via 47a, the insulating layer 46b, and the LED cell are shown in the order of a section, for example, a cross section between the LED cell and the neighboring LED cell. have.

FIG. 4E is a cross-sectional view of the vias 47a, 47b, 47c, 47d, and 47e in FIG. 4d. The insulating layers 51a and 51b are adjacent to the vias 47a, 47c, and 47e, A portion of the first conductive semiconductor layers 42a, 42b, 42c, 42d and 42e adjacent to the insulating layers 46a, 46c and 46e, a part of the active layer, and a part of the second conductive semiconductor layer The first conductive semiconductor layers 42a, 42b, 42c, 42d, and 42e are etched so as to be exposed to the upper portion of the second conductive semiconductor layer 42a1, 42b1, 42c1, 42d1, and 42e1.

4F is a plan view of the first metal electrodes 42a, 42b, 42c, 42d, and 42e exposed stepwise in FIG. 4E and the first metal electrodes 42b, 42c, 42d, and 42e for electrically connecting the etched vias 47a, 47c, Second metal electrodes 48b and 48d for electrically connecting the non-etched vias 47b and 47d to the second conductive semiconductor layers are formed on the first conductive semiconductor layers 48a and 48b, 39b, and 39c for electrically connecting one of the vias 47b and 47d to one electrode of the package.

After the first metal electrodes 48a, 48c, 48e and the second metal electrodes 48b, 48d and the electrode pads 39a, 39b, 39c are formed, the unetched vias 47b, C5, C6, and C7 of the etched vias 48a, 48c, and 48e, respectively. It is preferred that the center lines C3, C4, C5, C6 and C7 are equally divided along the centers of the vias 47a, 47b, 47c, 47d and 47e, respectively, none. The direction of each of the center lines C3, C4, C5, C6 and C7 is also preferably substantially parallel to each of the vias 47a, 47b, 47c, 47d and 47e.

By including the above-described processes, the present invention makes it possible to manufacture a packageable LED chip (30 in FIG. 3) without the necessity of wire bonding.

FIG. 5 is a view for explaining connection between the package electrodes and the LED chip when the LED chip of FIG. 1 is packaged. Referring to FIG. 5, when the LED chip 10 of FIG. 1 is mounted on a package, the bottom surface of the LED cell 12 is connected to the first electrode 52 of the package, and the via 16 is connected to the second And is connected to the electrode 54. Reference numeral 56 denotes a space between the first electrode 52 and the second electrode 54 of the package, and reference numeral 58 denotes a package substrate or a mounting sub-mount.

As described above, in the case of the conventional vertical LED chip, the electrical connection between the LED chip and the second electrode of the package is performed by wire bonding. However, in the case of packaging the LED chip according to the present invention, And the LED chip are electrically connected, thereby eliminating the need for wire bonding. Thus, the problems of the conventional package due to the wire bonding can be solved.

FIG. 6 is a view for explaining the connection between the package electrodes and the LED chip when the LED chip of FIG. 3 is packaged. Referring to FIG. 6, when the LED chip 30 of FIG. 3 is mounted on a package, the LED chip 30 is electrically connected to the first substrate 62 of the package and the first conductive semiconductor layer 32 are electrically connected and the second substrate 64 of the package and the second conductive semiconductor layer 34 are electrically connected through the second via 37b. Reference numeral 66 denotes a space between the first electrode 62 and the second electrode 64 of the package, and reference numeral 68 denotes a package substrate or a mounting submount.

As described above, in the case of the conventional horizontal type LED chip, the electrical connection between the LED chip and the package is made by wire bonding. However, when the LED chip according to the present invention is packaged, the first and second electrodes Since the LED chip is electrically connected, wire bonding is not necessary. Thus, the problems of the conventional package due to the wire bonding can be solved.

In addition, the LED chip which can be packaged without the need of wire bonding according to the present invention can form a white LED package through phosphor coating or coating in the pre-cutting step to the LED chip to convert the wavelength of light emitted from the LED chip, It has an advantage that a white LED package can be formed by applying a phosphor after die attach to the package.

The LED chip and the LED chip manufacturing method according to the present invention are not limited to the above-described embodiments, but various designs and applications can be made without departing from the basic principles of the present invention. It is obvious to those who have ordinary knowledge in.

1 is a schematic cross-sectional view of an LED chip packageable without wire bonding according to an embodiment of the present invention;

FIGS. 2A to 2E are process cross-sectional views schematically illustrating a method of manufacturing an LED chip that can be packaged without wire bonding according to an embodiment of the present invention.

3 is a schematic cross-sectional view of an LED chip package capable of being packaged without wire bonding according to another embodiment of the present invention;

FIGS. 4A to 4F are cross-sectional views schematically showing a method of manufacturing an LED chip that can be packaged without wire bonding according to another embodiment of the present invention. FIG.

5 is a view for explaining the connection between the package electrodes and the LED chip when the LED chip of FIG. 1 is packaged, and FIG.

FIG. 6 is a view for explaining the connection between the package electrodes and the LED chip when the LED chip of FIG. 3 is packaged.

Claims (24)

delete delete delete delete delete An LED cell including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; A first via disposed on one side of the LED cell so as to be parallel to the stacking direction of the LED cells, the first via being electrically connected to the first conductive semiconductor layer; And And a second via electrically connected to the second conductive semiconductor layer, the second via being spaced apart from the other side of the LED cell so as to be parallel to the stacking direction of the LED cells. The method of claim 6, A first insulating layer interposed between the LED cell and the first via; A second insulating layer interposed between the LED cell and the second via; A first metal electrode for electrically connecting the first conductive semiconductor layer and the first via; And And a second metal electrode for electrically connecting the second conductive semiconductor layer and the second via. The method of claim 7, And a third metal electrode located below the first conductive semiconductor layer, wherein the third metal electrode is electrically connected to the first via. The method of claim 7, Wherein the first and second vias are Ag or a conductive material of graphite or non-metal. The method of claim 7, Wherein the first and second insulating layers are non-conductive materials of a metal oxide or a polymer organic material. delete delete delete delete delete A package substrate comprising first and second spaced apart spaced apart electrodes; And And an LED cell including a substrate, a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer on the package substrate, The LED cell being disposed on one side of the LED cell so as to be parallel to the stacking direction of the LED cell, the first via being electrically connected to the first conductive semiconductor layer; And a second via disposed on the other side of the LED cell so as to be parallel to the stacking direction of the LED cell and electrically connected to the second conductive semiconductor layer, The first via is electrically connected to the first electrode, and the second via is electrically connected to the second electrode. 18. The method of claim 16, A first insulating layer interposed between the LED cell and the first via; A second insulating layer interposed between the LED cell and the second via; A first metal electrode for electrically connecting the first conductive semiconductor layer and the first via; And And a second metal electrode for electrically connecting the second conductive semiconductor layer and the second via. 18. The method of claim 17, Further comprising a third metal electrode located below the substrate, wherein the third metal electrode is electrically connected to the first via. 18. The method of claim 17, Wherein the first and second vias are Ag or a conductive material of graphite or non-metal. 18. The method of claim 17, Wherein the first and second insulating layers are non-conductive materials of a metal oxide or a polymer organic material. delete Preparing an epitaxial wafer; Forming holes at predetermined intervals so that the first conductive semiconductor layer, the active layer, and the second conductive semiconductor layer on the epitaxial wafer are exposed to the inside; Forming an insulating layer on side walls in the hole; Filling the hole in which the insulating layer is formed with a conductive material to form a via; Etching the first conductive semiconductor layer so that the first conductive semiconductor layer is exposed stepwise compared to the second conductive semiconductor layer by etching the insulating layer adjacent to the via and the adjacent region of the adjacent insulating layer by etching the vias one by one; A first metal electrode for electrically connecting the stepped-exposed first conductive semiconductor layer and the etched via, and a second metal electrode electrically connecting the unetched via and the second conductive semiconductor layer to each other, ; And And cutting the etched vias and the etched vias so that they are bisected along the centerline of each via. delete A hole is formed at a predetermined interval so that the first conductive semiconductor layer, the active layer, and the second conductive semiconductor layer on the epitaxial wafer are exposed to the inside, an insulating layer is formed on the side wall in the hole, Filling the material to form vias, etching the insulating layer adjacent to the vias to be etched and etched one by one and the adjacent regions of the adjacent insulating layer so that the first conductive semiconductor layer is exposed to the second conductive semiconductor layer A first metal electrode for electrically connecting the stepped exposed first conductive semiconductor layer and the etched via is formed, and the unetched vias and the second conductive semiconductor layer are electrically connected to each other Forming a second metal electrode connecting the etched vias and the etched vias, Preparing an LED chip including the step of cutting such nutrients along the center line O of; Mounting the LED chip on a package substrate; And And applying a phosphor on the LED chip.

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