KR101449484B1 - Direct conversion receiver - Google Patents

Abstract

The present invention relates to a direct conversion receiver, and more particularly, to a direct conversion receiver that includes a sampler for charge sampling an input current according to a sampling frequency, and a buffer for receiving and amplifying an output signal of the sampler with a low input impedance, And a filter device for decimating and FIR filtering the output signal of the mixer device, wherein the filter device delays the input signal by a different sampling period from each other and assigns the same or a different weight to each other, And an adder for adding a plurality of delay signals output from the signal transmitter and outputting a result.

Description

[0001] DIRECT CONVERSION RECEIVER [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct conversion receiver, and more particularly, to a structure of a discrete time direct conversion receiver having excellent adaptability to a wireless communication terminal.

The present invention has been derived from the research carried out as part of the IT original technology development project of the Ministry of Knowledge Economy [Task Control Number: 2008-F-008-02, Project: Development of Advanced Digital RF Technology for Next Generation Wireless Fusion Terminals].

Generally, a charge sampling receiver has a sampler that performs the functions of frequency downconversion and signal sampling. The sampler performs signal sampling using voltage sampling or charge sampling.

The Charge Sampling Mixer has its own built in aliasing and noise folding elimination characteristics and has a superior effect as a sampler compared to a voltage sampling mixer.

The conversion gain of the direct conversion downsampling mixer is expressed as Equation 1. " (1) "

Where G _m is the transconductance of the transconductor, f _s is the sampling frequency, and C _s is the capacitance of the sampling capacitor.

According to this equation, the conversion gain of the aliasing removal filter in the form of a first-order sink filter built in the charge sampling mixer is frequency dependent. Because the conversion gain of the anti-aliasing sink filter built into the charge sampling mixer has a frequency dependent nature, the conventional charge sampling receiver has a frequency band ranging from tens MHz to several GHz It is difficult to apply it to broadband applications such as digital TV tuners.

Another disadvantage of the charge sampling mixer is the linearity characteristic. In broadband applications, linearity is one of the most important specifications because it relates to blocking interferences. The output of the transconductance amplifier and the sampling mixer are limited in their swing due to the linearity of the receiver.

In order to solve the above problems, it is an object of the present invention to provide a structure in which a broadband characteristic and a linearity (swing range) of a mixing stage and a sampling filter are improved under conditions of low power and low supply voltage.

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According to an aspect of the present invention, there is provided a direct conversion receiver including a sampler unit for charge sampling an input current according to a sampling frequency, a demodulator for receiving and amplifying an output signal of the sampler unit and having a low input impedance, And a filter device for decimating and FIR filtering the output signal of the mixer device, wherein the filter device delays the input signal by a different sampling period from each other and outputs the same or different And a multiplier for multiplying a plurality of delay signals output from the signal transmitter and outputting a result of the multiplication, .

As described above, according to the high linearity mixer and the direct conversion receiver of the present invention, the frequency dependency characteristic of the conversion gain can be eliminated by using the analog passive mixer, thereby obtaining the wide band characteristic.

Also, according to the direct conversion receiver of the present invention as described above, the linearity of the mixer can be improved by further providing a buffer unit.

1 is a functional block diagram of a direct conversion receiver including a high linearity mixer of the present invention.
2 is a functional block diagram of a mixer device used in the direct conversion receiver of the present invention.
Figures 3a and 3b are exemplary implementations at the circuit level of the sampler portion of the mixer device of the present invention.
Figures 4A-4D illustrate one implementation at the circuit level of the buffer portion of the direct conversion receiver of the present invention.
Figures 5A and 5B are timing diagram diagrams of an embodiment of a filter device of the present invention and a clock for device operation.
6A and 6B are timing diagrams of a clock for another implementation of the filter device of the present invention and device operation.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the detailed description of known functions and configurations incorporated herein will be omitted when it may unnecessarily obscure the subject matter of the present invention.

In order to clearly illustrate the present invention, parts not related to the description are omitted, and like parts are denoted by similar reference numerals throughout the specification.

Also, when a part is referred to as "including " an element, it does not exclude other elements unless specifically stated otherwise.

1 is a functional block diagram of a direct conversion receiver including a high linearity mixer apparatus of the present invention.

Referring to FIG. 1, the direct conversion receiver of the present invention may include a high linearity mixer device 200 and a filter device 300. The local oscillator 400 may further include a local oscillator 400 for supplying a sampling signal to the high linearity mixer 200 and the filter 300. In addition, the receiving end may further include an amplifying device 100 for amplifying the received signal.

Generally, in order to operate the mixer and filter in the charge region, the input signal must be a current signal, not a voltage signal. Therefore, it is preferable to provide the transconductance amplifier 120 at the front end of the high linearity mixer device 200.

In addition, it is a typical receiver to place a low noise amplifier 110 in front of the transconductance amplifier 120. The received RF signal has a low signal strength and strong noise.

The high linearity mixer apparatus 200 of the present invention uses a form of a current commutating passive mixer or a form of a charge sampler instead of a conventional mixer for outputting a voltage signal, It is preferable to implement the mixer.

When the mixer apparatus 200 is designed in the above-described manner, the conversion gain of the mixer is expressed by Equation (2).

Where G _m is the transconductance of the transconductor and R _eq is the equivalent resistance of the switched capacitor network. The equivalent resistance R _eq is a constant when the sampling rate (Rate) and the capacitance of the sampling capacitor are constant.

Therefore, when the mixer device 200 is designed in the above-described manner, the frequency characteristic is excellent because the frequency characteristic is independent of the sampling frequency.

In addition, instead of terminating the mixer stage using a transimpedence amplifier generally used to achieve high linearity, the present invention uses a buffer that performs current amplification with a low input impedance to terminate the mixer stage . An example of a buffer having such characteristics is a common-gate amplifier.

To this end, the mixer apparatus 200 of the present invention may include a sampler unit 210 and a buffer unit 220.

The filter unit 300 performs FIR filtering to remove high frequency components from the signal output from the mixer unit 200 and decimation to lower the high sampling rate.

The filter device 300 is preferably designed with a charge region decimation filter to meet the conditions of low power and low supply voltage. When designing the filter device 300 as a charge region decimation filter, it is desirable to design the filter device 300 as a decimation filter composed of a switch and a capacitor in order to reduce the complexity of the circuit. In this case, however, the clock that controls the switch must be generated with the correct timing.

The signal passed through the filter device 300 is transmitted to a device (ADC, DSP, etc.) for digital signal processing.

2 is a functional block diagram of a mixer device used in the direct conversion receiver of the present invention.

Referring to FIG. 2, the mixer apparatus 200 of the present invention may include a sampler unit 210 and a buffer unit 220.

Transconductance amplifier 120 receives voltage inputs (Vi +, Vi-) and outputs a current signal. The bypass capacitor 121 removes the DC component of the signal output from the transconductance amplifier 120.

The sampler unit 210 mixes the input signal and the local oscillation signal to generate a discrete time current signal. For this, the sampler unit 210 may be implemented as a switch element and performs sampling according to a clock controlling the switching operation. It is preferable that the period of the clock for controlling the switching operation be a sampling frequency.

In the case of a switch device, it is preferable to use a MOSFET in consideration of integration degree and design convenience. The MOSFET inputs the control clock to the gate and the current signal to the source, and performs the operation of sampling the input current signal according to the control clock. That is, the MOSFET performs an operation as a switching element. In addition, the MOSFET is an integrated circuit, which is advantageous in terms of cost because of its simple structure in designing, and can be easily implemented by changing only the design width-to-length (W / L) such as allowable current and gain. The sampler unit 210 shown in FIG. 2 is a double balanced mixer implemented using a MOSFET, which is a switching device. The detailed operation will be described with reference to Fig.

In addition, if the sampler unit 210 is designed as a charge sampling type mixer, the frequency characteristic can be improved as described in the description of FIG.

However, when the sampler unit 210 is implemented as a switching device as described above (in particular, an amplifying device such as a MOSFET), the larger the swing range of the input / output stage, the worse the linearity is due to the characteristics of the device. Therefore, in order to enable signal processing in the linear section, the impedance of the input / output stage must be set low. Also, the swing range of the output terminal of the transconductance amplifier 100 should be set so as not to be high. Therefore, the circuit of the next stage of the sampler unit 210 is required to have a low input impedance.

The buffer unit 220 has a low impedance due to the reason described above, and performs a function of amplifying the signal because the swing range of the output of the sampler unit 210 is narrow and the signal characteristic is bad.

Generally, a mixer stage is terminated by a transimpedance amplifier (TIA), but the output characteristic of the transimpedance amplifier does not function as a current source but functions as a voltage source. Accordingly, there is a problem that a baseband transconductance amplifier is additionally required for connection with the filter device 300 that performs filtering using a current signal.

Therefore, the mixer apparatus of the present invention includes a buffer unit 220 that supplies a current to the filter device 300 through a current amplification while having a low input impedance instead of a transimpedance amplifier.

An example of a circuit capable of implementing such characteristics is a common gate amplifier. When the common gate amplifier is used, the current and impedance characteristics of the input and output stages can be easily controlled by implementing it in a cascode form, thereby providing the convenience of design. The buffer unit 220 shown in FIG. 2 is an example in which the common gate amplifier is implemented in the form of a cascode code. The detailed operation will be described with reference to Fig.

Figures 3a and 3b are exemplary implementations at the circuit level of the sampler portion of the mixer device of the present invention.

Referring to FIG. 3A, the sampler unit 210 may be implemented in the form of a double balanced mixer using two MOSFETs.

An input current signal is applied to the source terminal and a control signal is applied to the gate terminal. When the MOSFET used as the switching device is an NMOS, if the gate terminal is 'high', the signal at the source terminal can be transferred to the drain terminal, and current flows.

Since the MOSFET operates as a switching element, the input signal i _in is an analog signal and the output signals I _{in +} and I _{in -} are discrete-time signals.

Referring to FIG. 3B, the sampler unit 210 may implement a double-balanced mixer as a current switching quad, which is a differential circuit type, using four MOSFETs. In the case of a differential circuit, it is preferable to implement the sampler unit 210 in the form of a differential circuit because common mode noise can be removed and the noise characteristic can be improved.

The control signals (LO +, LO-) input to the gates of the MOSFETs are the sampling signals generated by the local oscillator 400. LO + and LO- are clock signals having a phase difference of 180 degrees with each other.

Since the switch element is implemented as a MOSFET, there is a problem that the linearity is deteriorated when the swing range of the input signal or the output signal is large due to the characteristics of the element. Therefore, in order to improve the linearity of the input / output stage, a signal with a narrow swing range is input, . To do this, the output stage needs to be terminated with a load with a low impedance of about 50 to 100 ohms.

Figures 4A-4D illustrate one implementation at the circuit level of the buffer portion of the direct conversion receiver of the present invention.

4A, the buffer unit 220 includes an amplifying transistor 222, a current source 221 at the source terminal, and a current source 223 at the drain terminal. The buffer unit 220 includes an input terminal connected to the source terminal, And is designed as an output common-gate amplifier. Current sources 221 and 223 are connected to the source and drain terminals, and a bias voltage is applied to the gate terminal to bias the amplifier. Biasing should be set so that the swing range of the output stage is sufficient for the subsequent stages of driving.

In order to improve the linearity of the sampler unit 210, the size of the signal input to the buffer unit 220 is sufficiently small, so that the amplification of the input signal in the buffer unit 220 can be understood through a small signal analysis.

The input impedance seen at the input stage is expressed as Equation (3) as the parallel connected impedance of the current source 221 and the amplification transistor 222 impedance.

Since the value of g _m of the general amplifying transistor is large, the input impedance seen from the side of the small signal of the common gate amplifier becomes sufficiently low to satisfy the characteristics required by the sampler unit 210.

In addition, since the output impedance of the common gate amplifier depends only on the configuration of the current source, it is easy to design a desired output impedance.

One of the important characteristics required in a direct conversion receiver is the noise characteristic, which is particularly important in the flicker noise characteristic. In order to remove this, the design area of the amplifying transistor 222 may be increased. _Gm that determines the amplification characteristics and input impedance can be readily determined by adjusting the width-to-length ratio (W / L) of the amplifying transistor 222. [

Since the output of the buffer portion of the present invention has a form of discrete time output, it is preferable that the amplification performance of the amplification transistor is excellent. Therefore, it is desirable to determine the width-to-length ratio so that g _m is sufficiently large in order to lower the input impedance and to improve the amplification characteristics.

That is, the buffer unit 220 in the form of a common gate amplifier of the present invention is an example of a circuit configuration in which the sampler unit 210 can simultaneously satisfy a desired impedance characteristic, an impedance characteristic and an amplification characteristic necessary for driving at a subsequent stage.

Therefore, the mixer apparatus 200 having high linearity characteristics can be realized by using the sampler unit 210 and the buffer unit 220 of the present invention in combination.

Referring to FIG. 4B, the buffer unit 220 of the present invention may be implemented as a differential type common gate amplifier. Furthermore, the drain current source 223 can be implemented using a current mirror structure, and when implemented with a current reflection structure, a current feedback function between the differential stages can be performed.

The input impedance and amplification characteristics of the buffer unit 220 of FIG. 4B are similar to those of FIG. 4A. The output impedance is the impedance of the current reflection structure.

Referring to FIG. 4C, the source-stage current source 221 of the buffer unit 220 of the present invention shown in FIG. 4B can be replaced with a load resistor having a small impedance.

4C, the bias condition of the buffer portion and the low supply voltage requirement can be satisfied only when the size of the load resistor 221 is sufficiently small. This is because when the magnitude of the current to be processed in the buffer unit 220 is large and the magnitude of the load resistance is large, the voltage drop becomes large in the load resistor 221, so that the bias condition can not be met under the low supply voltage requirement.

Referring to FIG. 4D, the buffer unit 220 shown in FIG. 4B may be modified into a folded cascode mixing OTA (operational transconductance amplifier).

In order to improve the output impedance characteristic of the buffer unit 220, the current source 223 at the drain end is changed to the cascode types 223 and 224. This results in improved output impedance characteristics.

Also, the source-stage current source 221 of the buffer unit 220 is implemented using a current reflecting structure.

5A is an embodiment of the filter device of the present invention.

Referring to FIG. 5A, the filter device 300 of the present invention is implemented with a charge region decimation filter and may include a plurality of banks including a switch and a capacitor, and an output stage including a switch and a capacitor.

5A shows four banks 310 to 340 having three capacitor stages 314 to 316, three input switch pairs 311, 312 and 313 and three output switch pairs 317, 318 and 319; And an output terminal 350 having a capacitor 352 for adding a current signal, a switch 351 for controlling the charge output and a switch 353 for discharging the charge charged in the capacitor 352, Fig.

The filter device 300 is an FIR filter that operates in a time interleaved manner. Particularly, when the input signal is a current signal, the advantage of the sampler unit 210 of the present invention having the aliasing removal characteristic can be utilized. In the output stage capacitor, IIR filtering is performed.

The three input switch pairs 311, 312, and 313 are controlled in operation by a clock signal having a different delay time and the same period, respectively.

The three capacitor stages 314, 315, and 316 each include two charge-charging capacitors and two charge-discharge switches. The operation of the charge discharge switch is controlled by the Ra clock.

The three output switch pairs 317, 318, and 319 control transfer of the charged charge to the output terminal of each connected capacitor stage, and are controlled by the same clock.

The bank also has two charge paths for the transfer of charge. An input switch and an output switch are disposed on the charge path, and a charging capacitor and a discharging switch are connected on the respective charge paths between the both switches.

The configuration and operation of the other banks 320 to 340 are the same as described above.

The amounts of charges charged in the capacitor stages 314 to 316 through the banks 310 to 340 and output to the output stage 350 are the same for each capacitor stage. That is, it is a circuit configuration for the first-order sync filter.

5B is a timing diagram of the control clock of each of the switches shown in FIG. 5A for operation of the filter device of the present invention.

Referring to FIG. 5B, S1 to S6 are delayed by one sampling period, respectively, and AS and BS are turned on by three sampling periods. Therefore, the filter of FIG. 5A operates as an FIR filter with a decimation ratio of 3. 5B, the sampling period (or the integration window, Ti = Ts = 1 / fs) provides a null at m * fs (m is a natural number ) necessary for the anti-aliasing function .

Hereinafter, only the operation for the positive input signal Iout + will be described taking the capacitor bank Ap 310 as an example. The operation for the negative input signal Iout- is symmetrical with the operation for the positive input signal.

In the initial state, the charge amount of all the capacitors is zero.

When the switching signal As is initially turned off, the circuit operates in the sampling mode. The output switches 317, 318 and 319 are opened and the input switching signals S1, S2 and S3 are turned on so that the input switches 311, 312 and 313 are sequentially closed. By this switching signal, three charge samples are sequentially charged in the sampling capacitors 314, 315, and 316.

Subsequently, when the switching signal As is turned on, the output switches 317, 318 and 319 are closed to enter the charge sharing mode. At this time, when the switching signal RD is turned on so that the switch 351 at the output terminal is closed, the circuit operates in the lead-out mode. In this mode, the sampling capacitors 314, 315 and 316 and the capacitor 352 of the output stage are connected at the same time so that the charges charged in the sampling capacitors 314, 315 and 316 are transferred to the capacitor 352 of the output stage. On the other hand, the IIR filtering effect occurs in the capacitor 352 at the output stage.

Next, when the reset signal Ra applied to the reset switches in the sampling capacitors 314, 315, and 316 is turned on, the circuit enters the reset mode and charges the charge remaining in the sampling capacitors 314, 315, and 316 . If necessary, in the reset mode, instead of the local reset signal Ra, the global reset switch 453 can be closed to discharge the residual charge in the sampling capacitors 314, 315, and 316.

Meanwhile, while the capacitor bank Ap 310 performs the operation in the charge sharing mode, the capacitor bank Bp 320 performs the operation in the sampling mode.

The capacitor bank Ap 310 performs the operation in the reset mode and then performs the operation in the sampling mode again, and the capacitor bank Bp 320 performs the operation in the charge sharing mode after performing the operation in the sampling mode. That is, each of the capacitor banks 310 and 320 of the filter device 300 performs an operation for filtering repeatedly and cyclically.

When the filter device 300 shown in FIG. 5A is operated according to the timing chart of FIG. 5B, since the weighting factor is constant and one output sample can be obtained for every three input samples, A filter is implemented.

6A is another embodiment of the filter device of the present invention.

Referring to FIG. 6A, it can be seen that the output switches 317 to 319 are not all connected to the current path as compared to the circuit of FIG. 5A. The capacitor stages 314 and 316 are configured such that one capacitor is discharged by the output switches 317 and 319.

Referring to the timing diagram of FIG. 6B, since the input switches S1 to S3 generate a sequential delay signal, when a sequential delay signal is output to the output stage 350, the weight ratio is 1: 2: 1. Therefore, a second-order sink filter having a decimation ratio of 3 is implemented because each delay signal has a symmetrical shape with different weights.

The secondary sink filter is superior in anti-aliasing characteristics due to its wide width and deep depth in terms of frequency characteristics as compared with the primary sink filter.

Therefore, the primary sink filter can be used when a flat passband characteristic and a relatively low noise figure and linearity specification are required. The secondary sink filter can be used when strong anti-aliasing characteristics are required even though the chip area and power consumption are required .

Referring to the timing diagram of FIG. 6B, the operation of the filter device 300 will be described, and only the operation on the positive input signal Iout + will be described taking the capacitor bank Ap 310 as an example.

When the switching signal As is initially turned off, the circuit operates in the sampling mode. The output switches 317, 318 and 319 are opened and the input switching signals S1, S2 and S3 are turned on so that the input switches 311, 312 and 313 are sequentially closed. By this switching signal, three charge samples are sequentially charged in the sampling capacitors 314, 315, and 316. In particular, the two capacitors constituting the sampling capacitors 314, 315 and 316 accumulate the same amount of charge.

Subsequently, when the switching signal As is turned on, the output switches 317, 318 and 319 are closed to enter the charge sharing mode. At this time, when the switching signal RD is turned on so that the switch 351 at the output terminal is closed, the circuit operates in the lead-out mode. In this mode, the sampling capacitors 314, 315 and 316 and the capacitor 352 of the output stage are connected at the same time so that the charges charged in the sampling capacitors 314, 315 and 316 are transferred to the capacitor 352 of the output stage. However, in this case, an operation different from that of the filter device 300 of FIGS. 5A and 5B is performed. Both of the capacitors constituting the second sampling capacitor 315 are connected to the capacitor 352 of the output stage while each of the two capacitors constituting the first and third sampling capacitors 314 and 316 is connected to only one of the capacitors 352 5A and 5B in that the capacitors 352 of the output stage are connected to the common voltage Vcm and the other capacitors not connected to the capacitor 352 of the output stage are connected to the common voltage Vcm.

Through the above switching control, the FIR filter coefficient of the filter device 300 becomes 1: 2: 1 in the form of a triangular window, and through this, Sink filters can be implemented

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. To those skilled in the art.

100: amplifier
110: low noise amplifier 120: transconductance amplifier
200: Mixer device
210: Sampler unit 220: Buffer unit
300: Filter device
310 to 340: Signal transferring unit 350:
400: local oscillator

Claims (27)

delete delete delete delete delete delete delete delete A high linearity mixer device including a sampler for charge sampling an input current according to a sampling frequency and a buffer for receiving and amplifying an output signal of the sampler with a low input impedance and outputting a current signal; And
And a filter device for decimating and FIR-filtering the output signal of the mixer device,
Wherein the filter device comprises:
A signal transmitter for delaying input signals by different sampling periods and generating and outputting a plurality of delay signals by assigning the same or different weights to each other and outputting a plurality of delay signals output from the signal transmitter; And an adder for outputting an output of the direct conversion receiver.
delete delete delete delete 10. The method of claim 9,
The buffer unit includes:
And a common gate amplifier for terminating an output signal of the sampler unit.
delete delete delete delete delete delete 10. The method of claim 9,
Wherein the signal transfer unit comprises:
And four banks for performing an operation of a sampling mode for charging the charge and an operation of a charge sharing mode for outputting the charged charge in the operation of the sampling mode,
Wherein each of the four banks comprises:
A bank Ap connected to a positive output signal of the mixer unit for sequentially and repeatedly performing the operation of the sampling mode and the operation of the charge sharing mode;
The operation of the charge sharing mode is performed while the operation of the sampling mode of the bank Ap is performed, and the operation of the sampling mode is performed while the operation of the charge sharing mode of the bank Ap is performed Bank Bp;
A bank A connected to the negative output signal of the mixer device for sequentially and repeatedly performing the operation of the sampling mode and the operation of the charge sharing mode; And
An operation of the charge sharing mode is performed while the operation of the sampling mode of the bank An is performed and an operation of the sampling mode is performed while the operation of the charge sharing mode of the bank An is performed And a bank Bn.
22. The method of claim 21,
The bank Ap, the bank Bp, the bank An, and the bank Bn, respectively,
Three capacitor stages each including a charge-charge capacitor pair for charging the charge and a charge-discharge switch pair connected in parallel to each of the charge-charge capacitor pairs in the operation of the sampling mode;
Three input switch pairs for opening and closing connections of the mixer device and each of the three capacitor stages; And
And three output switch pairs for opening and closing connections between each of the three capacitor stages and an output stage for storing charges output from the plurality of banks during operation of the charge sharing mode.
23. The method of claim 22,
The three input switch pairs are sequentially turned on by a delay of one sampling period to sequentially charge the charge-charging capacitor pairs of the three capacitor stages,
Wherein the three output switch pairs are turned on during three sampling periods to transfer charge to the output stage thereby to operate the charge region decimation filter device as a primary sink filter with a data rate of 3.
23. The method of claim 22,
And a common voltage is connected to one switch included in each of the two pairs of the three output switch pairs.
25. The method of claim 24,
The three input switch pairs are sequentially turned on by a delay of one sampling period to sequentially charge the charge-charging capacitor pair,
Wherein the three output switch pairs are turned on for three sampling periods to transfer charge to the output stage thereby to operate the charge region decimation filter device as a secondary sink filter with a data rate of 3.
23. The method of claim 22,
Wherein,
A capacitor in an output stage for receiving and storing the charge stored in the charge-charging capacitor pair in the charge sharing mode of operation;
An output terminal switch for opening / closing a connection between the capacitor at the output terminal and the bank Ap, the bank Bp, the bank An, or the bank Bn; And
And a global reset switch for discharging the charge stored in the charge-charging capacitor pair of the three capacitor stages.
23. The method of claim 22,
The bank Ap, the bank Bp, the bank An, and the bank Bn each have two charge paths for transferring the charges,
Two charge paths of the bank Ap and two charge paths of the bank Bp are cross-connected to each other. Two charge paths of the bank An and two charge paths of the bank Bn are cross-
Three capacitor stages of the bank Ap and the bank An, three input switch pairs and three output switch pairs are connected to one of the two cross-coupled charge paths,
Three capacitor stages of the bank Bp and the bank Bn, three input switch pairs and three output switch pairs are respectively connected to the remaining lines of the two cross-coupled charge paths.

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