KR101426844B1 - Nonvolatile memory element - Google Patents

Abstract

The present invention provides a nonvolatile memory element. The device includes a tunnel insulating film formed on a semiconductor substrate, a charge storage film formed on the tunnel insulating film, a blocking insulating film formed on the charge storage film, and a control gate electrode formed on the blocking insulating film, A first blocking insulating film, a second blocking insulating film, and a third blocking insulating film, wherein an energy band gap of the second blocking insulating film is larger than an energy band gap of the first blocking insulating film and the third blocking insulating film.

Flash memory, charge storage film, blocking insulating film

Description

[0001] The present invention relates to a nonvolatile memory device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more specifically to a nonvolatile memory device.

The present invention relates to a semiconductor memory element, and more particularly, to a non-volatile memory element.

A nonvolatile memory element is a semiconductor device in which stored information is maintained without disappearance even when power supply is interrupted. The flash memory device, which is a representative nonvolatile memory element, can store information according to whether charge is charged in the floating gate interposed between the control gate and the semiconductor substrate.

In the case of an erase operation of a nonvolatile flash memory having a SONOS (Doped Silicon / Oxide / Nitride / Oxide / Silicon) structure and a floating gate, a back tunneling current flows, . In the erase operation, it is necessary to reduce the back tunneling current and increase the retention time of the nonvolatile memory element in the programmed state.

SUMMARY OF THE INVENTION The present invention provides a nonvolatile memory device with reduced back tunneling current.

According to another aspect of the present invention, there is provided a nonvolatile memory device having increased retention time.

A nonvolatile memory device of the present invention includes: a tunnel insulating film formed on a semiconductor substrate;

A charge storage film formed on the tunnel insulating film, a blocking insulating film formed on the charge storage film, and a control gate electrode formed on the blocking insulating film,

Wherein the blocking insulating film includes a first blocking insulating film, a second blocking insulating film, and a third blocking insulating film which are sequentially stacked, wherein an energy band gap of the second blocking insulating film is larger than an energy of the first blocking insulating film and the third blocking insulating film Band gap.

In one embodiment of the present invention, the charge storage film may be an insulator or a conductive floating gate holding a charge trap site.

In one embodiment of the present invention, the dielectric constant of the second blocking insulating film may be smaller than the dielectric constant of the first blocking insulating film and the third blocking insulating film.

In one embodiment of the present invention, the trap density of the second blocking insulating layer may be smaller than the trap density of the first blocking insulating layer and the third blocking insulating layer.

In one embodiment of the present invention, the blocking insulating layer may further include at least one fourth blocking insulating layer on the third blocking insulating layer so as to alternate the materials having different energy band gaps.

In one embodiment of the present invention, the first blocking insulating layer and the third blocking insulating layer may include at least one of a metal oxide layer, a metal nitride layer, and a metal oxide nitride layer.

In one embodiment of the present invention, the second blocking insulating layer may include at least one of a silicon oxide layer, a metal oxide layer, a metal nitride layer, and a metal oxide nitride layer.

In one embodiment of the present invention, the charge storage layer may include at least one of a silicon nitride layer, a metal quantum dot, a silicon quantum dot, a metal, highly doped silicon, and doped germanium.

In one embodiment of the present invention, the floating gate may include at least one of an N-type conductivity polysilicon, a P-type conductivity polysilicon, a metal, and doped germanium.

In one embodiment of the present invention, the metal may comprise at least one of a pure metal and a metal mixture.

In one embodiment of the present invention, the control gate electrode may have a structure of a barrier metal and a high work function metal which in turn are stacked.

In one embodiment of the present invention, the high work function metal may have a work function of 4.5 eV or higher.

In one embodiment of the present invention, the barrier metal may include at least one of a metal nitride layer, a silicon nitride layer, and a combination thereof for preventing a reaction between the high work function metal and the blocking insulating layer.

In one embodiment of the present invention, the control gate electrode may further include at least one of a high-function metal and a doped polysilicon interposed between the barrier metal and the blocking insulating film.

In one embodiment of the present invention, the control gate electrode may comprise at least one of doped silicon and metal, pure metal, and metal inclusions, which are stacked in turn.

In an embodiment of the present invention, the first blocking insulating layer may have the same energy bandgap as the third blocking insulating layer.

 According to the present invention, it is possible to extend the retention time of the nonvolatile memory element by inserting a region having a large energy band gap into the middle of the blocking insulating film composed of a plurality of blocking insulating films, and to reduce backtunneling current The speed can be increased.

According to an aspect of the present invention, there is provided a nonvolatile memory device.

A charge trap flash memory has a charge storage film which is an insulator interposed between a control gate and a semiconductor substrate. A tunnel insulating film may be provided between the charge storage film and the semiconductor substrate, and a blocking insulating film may be provided between the charge storage film and the control gate. The charge storage film has a trap site capable of storing charge, and whether or not the charge is charged in the capture spot determines information stored in the charge capture flash memory.

The charge trap flash memory has an advantage that the parasitic capacitance and the coupling coefficient of the control gate can be reduced as compared with a flash memory having a floating gate. Further, the charge capturing flash memory must maintain the state stored in the charge storage film for a predetermined time (retention time).

During the erase operation of the charge trapping flash memory of the SONOS (Silicon / Oxide / Nitride / Oxide / Silicon) cell structure, a back tunneling current may be generated through the blocking insulating film and the erase operation speed may be lowered. In order to solve this problem, it is possible to reduce the electric field applied to the high dielectric insulating film by using the high dielectric insulating film as the blocking insulating film. Specifically, a charge trapping flash memory having a TANOS (TaN / Al 2 O 3 / Nitride / Oxide / Silicon) cell structure has been proposed. The back tunneling current flowing through the high dielectric insulating film can control the amount of FN tunneling by properly controlling the energy band.

As the aluminum oxide film (Al 2 O 3) is used as the high dielectric insulating film, the electric field applied to the high dielectric insulating film is reduced, and the back tunneling current flowing through the high dielectric insulating film can be reduced. Further, the back tunneling current can be further reduced by using a conductive material having a high work function (for example, TaN, WN, TiN, CoSix, polysilicon) of 4.5 eV or more as the control gate electrode .

On the other hand, the high dielectric insulating film as the blocking insulating film may include a bulk trap density, so that the bulk trap density can reduce the retention time of the charge storage film and reduce the reliability of the charge trap flash memory. To overcome this, a plurality of blocking insulating films are used. Specifically, the back tunneling current can be controlled by appropriately adjusting the energy band gap of the plurality of blocking insulating films.

A flash memory having a floating gate structure has a charge storage film as a conductive interposed between a control gate and a semiconductor substrate. A tunnel insulating film may be provided between the charge storage film and the semiconductor substrate, and a blocking insulating film may be provided between the charge storage film and the control gate. The charge storage film may comprise a floating gate. The floating gate may be a conductive material. Whether or not the charge is stored in the floating gate determines the information stored in the flash memory. The back tunneling current can be controlled by appropriately adjusting the energy band gap of the plurality of blocking insulating films.

 Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are being provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, the thicknesses of the layers and regions are exaggerated for clarity. Also, where a layer is referred to as being "on" another layer or substrate, it may be formed directly on another layer or substrate, or a third layer may be interposed therebetween. Like numbers refer to like elements throughout the specification.

1A and 1B are diagrams showing a NAND nonvolatile memory element according to embodiments of the present invention. 1B is a cross-sectional view taken along the line I-I 'in FIG. 1A.

Referring to FIGS. 1A and 1B, a NAND nonvolatile memory device according to embodiments of the present invention includes a semiconductor substrate 100 having a cell region. A device isolation film 300 is disposed on the semiconductor substrate 100. The device isolation film 100 defines active regions (ACT). The active regions ACT are arranged side by side in the first direction. A string selection line SSL and a ground selection line GSL traverse the active spots ACT and a plurality of word lines WL are formed between the string selection line SSL and the ground selection line GSL Of active regions (ACT). The string selection line SSL, the ground selection line GSL, and the word lines WL extend in parallel along a second direction orthogonal to the first direction. The string selection line SSL, the word lines WL, and the ground selection line GSL may be included in the cell string group. The cell string group may be repeatedly arranged in mirror symmetry along the first direction.

The impurity regions 200 corresponding to the source and the drain are arranged in the active region ACT on both sides of the string selection line SSL, the plurality of word lines WL and the ground selection line GSL . The impurity region 200 on both sides of the word line WL and the word line WL constitutes a cell transistor and the impurity region 200 on both sides of the ground selection line GSL and the ground selection line GSL Configure the ground select transistor. The string selection line SSL and the impurity region 200 on both sides of the string selection line SSL constitute a string selection transistor.

The word line WL includes a tunnel insulating layer 110, a charge storage layer 120, a blocking insulating layer 150, and a control gate electrode 160 sequentially stacked on the semiconductor substrate 100. A hard mask pattern (not shown) may be disposed on the control gate electrode 160. The ground selection line GSL and the string selection selection line SSL may have the same structure as the word line WL. However, the line width of the string selection line SSL and the ground selection line GSL may be different from the line width of the word line WL. In particular, the line width of the string selection line SSL and the ground selection line GSL may be larger than the word line WL. Layers in the ground and string select lines GSL and SSL corresponding to the tunnel insulating film 110, the charge storage film 120 and the blocking insulating film 150 can be used as gate insulating films of the ground and string select transistors .

The tunnel insulating layer 110, the charge storage layer 120, and the blocking insulating layer 150 may extend on the adjacent semiconductor substrate. The plurality of word lines WL may share the tunnel insulating layer 110, the charge storage layer 120, and the blocking insulating layer 150. Also, the ground and string select lines GSL and SSL may share the extended tunnel insulating film 110, the charge storage film 120, and the blocking insulating film 150. A cell spacer (not shown) may be disposed on the sidewall of the control gate electrode 160. The cell spacers (not shown) may be located on the extended blocking insulating layer 150.

The blocking insulating layer 150 may include a first blocking insulating layer 150a, a second blocking insulating layer 150b, and a third blocking insulating layer 150c.

2A and 2B are diagrams showing a NOR nonvolatile memory element according to embodiments of the present invention. 2B is a cross-sectional view taken along the line III-III 'in FIG. 1A.

2A and 2B, a NOR nonvolatile memory device according to embodiments of the present invention includes a semiconductor substrate 100 having a cell region. The device isolation film 300 is formed on a semiconductor substrate 100 . The device isolation layer 300 defines active regions 500, 510, and 520. The first active regions 500 are arranged side by side in the first direction. The source-strapping active regions 510 are regularly arranged in the first direction regularly between the first active regions 500. And second active regions 520 crossing the first active region 500 are arranged side by side in the second direction. The second active regions 520 serve as source lines.

A pair of word lines (WL) traversing the first active regions (500) and the source strapping active regions (510) and extending in the second direction are disposed. The active regions located on both sides of the pair of word lines are the drains of the transistor and the active region between the pair of word lines becomes the source of the transistor. The drain of the transistor is electrically connected through the bit line contact plug 540 to the bit line.

In addition, the sources of the transistors are electrically connected to the neighboring sources in the second direction through the second active region 520. Accordingly, the second active region 520 plays a role of a source line. A source contact 530 is formed at a position where the second active region 520 and the source-strapping active region 510 intersect.

The word line WL includes a tunnel insulating film 110, a charge storage film 120, a blocking insulating film 150, and a control gate electrode 160 sequentially stacked on the semiconductor substrate 100.

The tunnel insulating layer 110, the charge storage layer 120 and the blocking insulating layer 150 may extend in a second direction and the word line WL may extend through the tunnel insulating layer 110, the charge storage layer 120, And the blocking insulating film 150, as shown in FIG. A spacer (not shown) may be placed on the extended blocking insulating film 150.

The blocking insulating layer 150 may include a first blocking insulating layer 150a, a second blocking insulating layer 150b, and a third blocking insulating layer 150c.

3 is a cross-sectional view taken along line II-II 'of FIG. 1A for explaining a charge trapping nonvolatile memory element according to an embodiment of the present invention. 4A to 4D are views showing a flat band energy band diagram of a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIGS. 3 and 4A to 4D, the device includes a tunnel insulating film 110 formed on a semiconductor substrate 100, a charge storage film 120 formed on the tunnel insulating film 110, And a control gate electrode 160 formed on the blocking insulating layer 150. The blocking insulating layer 150 is formed on the insulating layer 150, In addition, an isolation layer 300 may be formed on the semiconductor substrate 100 to define an active region ACT. The charge storage layer 120 may not be separated per unit cell. The blocking insulating layer 150 includes a first blocking insulating layer 150a, a second blocking insulating layer 150b, and a third blocking insulating layer 150c which are sequentially stacked. The first blocking insulating layer 150a and the third blocking insulating layer 150c may be formed of the same material. Further, the second blocking the energy band gap of the insulating film (150b) (energy band gap, E g2) is the first blocking insulating film (150a) and the third blocking insulating film (150c) energy band gap (E _g1, E _g3 of ). An isolation layer 300 is disposed on the semiconductor substrate 100 to define active regions ACT. The device may have a structure in which the charge storage film 120 is not separated per unit cell.

The semiconductor substrate 100 may include one selected from the group consisting of a single crystal silicon film, a silicon on insulator (SOI), a silicon film on a silicon germanium (SiGe) film, a silicon single crystal film on an insulating film, have.

The tunnel insulating layer 110 may include at least one of a silicon oxide layer, a silicon oxynitride layer (SiON), and a high dielectric constant material. The high dielectric material may include at least one of an aluminum oxide film (Al 2 O 3), a hafnium oxide film (HfO 2), a hafnium aluminum oxide film (HfAlO), a hafnium silicon oxide film (HfSiO), a zirconium oxide film (ZrO 2), or a tantalum oxide film . The silicon oxide film may be a thermal oxide film.

The charge storage layer 120 may be formed of a material having traps capable of storing charge. The charge storage layer 120 may include a dielectric layer. The charge storage layer 120 may include at least one of a silicon nitride layer, a metal quantum dot, a silicon quantum dot, a metal, doped silicon, and doped germanium. The metal may comprise at least one of a pure metal and a metal mixture. The charge storage layer 120 may be formed of one or more materials selected from the group consisting of nano crystalline silicon, nano crystalline silicon germanium, nano crystalline metal, Ge quantum dot, metal quantum dot metal quantum dot, silicon quantum dot, or a laminated structure thereof. The charge storage layer 120 may have a metal trap site through metal doping. Alternatively, the charge storage layer 120 may form a deep trap site in the energy band of the charge storage layer through the wet oxidation process after forming the charge storage layer.

The blocking insulating layer 150 includes a first blocking insulating layer 150a, a second blocking insulating layer 150b, and a third blocking insulating layer. The first blocking insulating layer 150a is disposed on the charge storage layer 120. The second blocking insulating layer 150b is disposed on the first blocking insulating layer 150a and the third blocking insulating layer 150c Is disposed on the second blocking insulating film 150b. The first blocking insulating layer 150a and the third blocking insulating layer 150c are formed of the same material. The energy bandgaps E _g1 and E _{g3 of} the first blocking insulating layer 150a and the third blocking insulating layer 150c are smaller than the energy band gap E _g2 of the second blocking insulating layer 150b . The blocking insulating layer 150 may have a dielectric constant and a charge trap. The charge trap density of the blocking insulating layer 150 may increase in proportion to the dielectric constant.

  The dielectric constant of the second blocking insulating layer 150b may be smaller than the dielectric constant of the first blocking insulating layer 150a and the third blocking insulating layer 150c and the dielectric constant of the second blocking insulating layer 150b May be smaller than the charge trap density of the first blocking insulating layer 150a and the third blocking insulating layer 150c. The charge trap density of the first blocking insulating layer 150a, the second blocking insulating layer 150b, and the third blocking insulating layer 150c may be proportional to the dielectric constant.

The first blocking insulating layer 150a and the third blocking insulating layer 150c may include at least one of a metal oxide layer, a metal nitride layer, and a metal oxide nitride layer. The metal oxide film may include at least one of a hafnium silicon oxide film (HfSiO), a zirconium oxide film (ZrO2), a hafnium aluminum oxide film (HfAlO), a hafnium oxide film (HfO2), and an aluminum oxide film (Al2O3).

The second blocking insulating layer 150b may include at least one of a silicon oxide layer, a metal oxide layer, a metal nitride layer, and a metal oxide nitride layer. The metal oxide film may include at least one of a hafnium silicon oxide film (HfSiO), a zirconium oxide film (ZrO2), a hafnium aluminum oxide film (HfAlO), a hafnium oxide film (HfO2), and an aluminum oxide film (Al2O3) May be formed by an ALD, CVD, or PVD process.

An annealing process or a plasma process process including at least one of O2, N2, and NH3 after forming the first blocking insulating layer 150a, the second blocking insulating layer 150b, and the third blocking insulating layer 150c Can be performed. For example, the charge trap density of the first blocking insulating layer 150a, the second blocking insulating layer 150b, and the third blocking insulating layer 150c may be reduced by the above process.

 The control gate electrode 160 may be a conductive material having a work function greater than 4.5 eV. For example, at least one of TaN, polysilicon, W, WN, TiN, and CoSix. The control gate electrode 160 may include another conductive material. In particular, the control gate electrode 160 may have a structure of a barrier metal and a high work function metal, which are stacked in sequence. The high work function metal may have a work function of 4.5 eV or higher. The barrier metal may include at least one of a metal nitride layer, a silicon nitride layer, and a combination thereof to prevent a reaction between the high work function metal and the blocking insulating layer. The control gate electrode 160 may further include at least one of a high dielectric constant metal and a doped polysilicon interposed between the barrier metal and the blocking insulating layer 150. The control gate electrode 160 may comprise at least one of sequentially stacked doped silicon and metal, pure metal, and metal inclusions.

4A, the energy band gap E _g2 of the second blocking insulating layer 150b is greater than the band gaps E _g1 and E _{g3 of} the first and third blocking insulating layers 150a and 150c, The conduction band of the second blocking insulating layer 150b is higher than the conduction band of the first and third blocking insulating layers 150a and 150c and the valence band of the second blocking insulating layer 150b is higher than the conduction band of the first and second blocking insulating layers 150b. 3 blocking insulating films 150a and 150c, respectively.

Referring to FIG. 4B, the energy band gap E _g2 of the second blocking insulating layer 150b is greater than the band gap E _g1 and E _{g3 of} the first and third blocking insulating layers 150a and 150c, The conduction band of the second blocking insulating layer 150b is higher than the conduction band of the first and third blocking insulating layers 150a and 150c and the valence band of the second blocking insulating layer 150b is higher than the conduction band of the first and third blocking insulating layers 150a and 150b. And 150c, respectively.

Referring to FIG. 4C, the energy band gap E _g2 of the second blocking insulating layer 150b is greater than the band gaps E _g1 and E _{g3 of} the first and third blocking insulating layers 150a and 150c, The conduction band of the second blocking insulating layer 150b is lower than the conduction band of the first and third blocking insulating layers 150a and 150c and the valence band of the second blocking insulating layer 150b is lower than the conduction band of the first and third blocking insulating layers 150a and 150b. And 150c, respectively.

Referring to FIG. 4D, the blocking insulating layer 150 may further include a fourth blocking insulating layer 150d so that two materials having different energy band gaps are alternated. The fourth blocking insulating layer 150d is the same material as the second blocking insulating layer 150b. Accordingly, the energy band gap E _g4 of the fourth blocking insulating film is equal to the energy band gap E _g2 of the second blocking insulating film. In addition, according to a modified embodiment of the present invention, the blocking insulating layer 150 may further include the fourth blocking insulating layer 150d and the fifth blocking insulating layer (not shown). The fourth blocking insulating layer 150d may be formed of the same material as the second blocking insulating layer 150b and the fifth blocking insulating layer may be formed of the same material as the first blocking insulating layer 150a.

5 is a diagram showing an energy band diagram when a negative erase voltage (V ₀ ) is applied to a nonvolatile memory device according to the present invention. However, the charge accumulated in the charge storage film 120 is removed by the externally applied erase voltage V ₀ .

Specifically, when a negative erase voltage is applied to the control gate electrode 160 with respect to the semiconductor substrate 100, an electric field is generated in the tunnel insulating film 110, the charge storage film 120, and the blocking insulating film 150, respectively . Each electric field can be calculated by a capacitor voltage distribution model. The back tunneling current flowing through the blocking insulating layer 150 may depend on the electric field of the blocking insulating layer 150. Specifically, the back tunneling current can be controlled by adjusting the structure, band gap, thickness, and dielectric constant of the blocking insulating layer 150.

Each electric field can be given as follows.

은 유전율을 의미한다. Here, subscripts i and j may be from 1 to 5. Subscript 1 denotes a tunnel insulating film 110. Subscript 2 denotes a charge storage film 120. Subscript 3 denotes a first blocking insulating film 150a. Subscript 4 denotes a second blocking insulating film 150b. Subscript 5 denotes a third blocking And an insulating film 150d. t represents the thickness,

Means the dielectric constant.

For example, when the first blocking insulating layer 150a and the third blocking insulating layer 150c having a large dielectric constant are increased in thickness, the electric field of each of the first blocking insulating layer 150a and the third blocking insulating layer 150c is reduced . However, the first blocking insulating layer 150a and the third blocking insulating layer 150c may have a high charge trap density due to a high dielectric constant. Further, the charges trapped in the trap can easily move to an external electric field. Accordingly, the thickness of the first and third blocking insulating films 150a and 150c having a large dielectric constant is limited.

On the other hand, if the difference between the work function of the third blocking insulating layer 150c and the control gate electrode 160 is increased, the threshold energy for causing the back tunneling phenomenon is increased and the back tunneling current can be reduced. Unlike the present invention, if the energy band gap of the second blocking insulating film 150b is smaller than the energy band gap of the third blocking insulating film 150c and the first blocking insulating film 150c, Can be accumulated in the energy well of the insulating film 150b. Therefore, the energy band gap of the second blocking insulating layer 150b is preferably larger than the energy band gap of the third blocking insulating layer 150c and the first blocking insulating layer 150a.

According to an embodiment of the present invention, the first blocking insulating layer 150a and the third blocking insulating layer 150c may have a larger dielectric constant and a larger trap density than the second blocking insulating layer 150b. The electric charge trapped in the first blocking insulating layer 150a can not easily pass through the second blocking insulating layer 150b due to an external electric field, thereby improving reliability.

6 is a cross-sectional view taken along line II-II 'of FIG. 1A for explaining a floating gate type nonvolatile memory device according to another embodiment of the present invention. In the present embodiment, the description of the parts that are the same as those in the embodiment described with reference to FIG. 3 and FIG. 4 will be omitted.

6, the device includes a tunnel insulating layer 110 formed on a semiconductor substrate 100, a charge storage layer 120 formed on the tunnel insulating layer 110, a blocking layer 120 formed on the charge storage layer 120, An insulating layer 150, and a control gate electrode 160 formed on the blocking insulating layer 150. In addition, an isolation layer 300 may be formed on the semiconductor substrate 100 to define an active region ACT. The charge storage layer 120 may have a structure that is separated for each unit cell.

The charge storage layer 120 may be a floating gate, and the charge storage layer 120 may include a conductive material. The floating gate may include at least one of an N-type conductivity polysilicon, a P-type conductivity polysilicon, a metal, doped silicon, and doped germanium.

The control gate electrode 160 may include at least one of polysilicon doped with a conductive material, a metal, a metal silicide, a metal compound, and a stacked structure thereof.

7A to 7C are diagrams showing a flat band energy band diagram of a nonvolatile memory device according to another embodiment of the present invention. 7A to 7C are energy band diagrams when polysilicon doped with the charge storage film 120 is used and polysilicon doped with the control gate electrode 160 is used.

7A, the energy band gap E _g2 of the second blocking insulating layer 150b is greater than the band gaps E _g1 and E _{g3 of} the first and third blocking insulating layers 150a and 150c, The conduction band of the second blocking insulating layer 150b is higher than the conduction band of the first and third blocking insulating layers 150a and 150c and the valence band of the second blocking insulating layer 150b is higher than the conduction band of the first and third May be higher than the valence band of the blocking insulating films 150a and 150c.

7b, the energy band gap E _g2 of the second blocking insulating layer 150b is greater than the band gaps E _g1 and E _{g3 of} the first and third blocking insulating layers 150a and 150c, The conduction band of the second blocking insulating layer 150b is higher than the conduction band of the first and third blocking insulating layers 150a and 150c and the valence band of the second blocking insulating layer 150b is higher than the conduction band of the first and third blocking insulating layers 150a and 150b. And 150c, respectively.

Referring to FIG. 7C, the energy band gap E _g2 of the second blocking insulating layer 150b is greater than the band gap E _g1 and E _{g3 of} the first and third blocking insulating layers 150a and 150c, The conduction band of the second blocking insulating layer 150b is lower than the conduction band of the first and third blocking insulating layers 150a and 150c and the valence band of the second blocking insulating layer 150b is lower than the conduction band of the first and third blocking insulating layers 150a and 150b. And 150c, respectively.

Referring again to FIG. 7A, according to a modified embodiment of the present invention, the blocking insulating layer 150 may further include a fourth blocking insulating layer (not shown) so that materials having different energy band gaps are alternated. The fourth blocking insulating layer may be formed of the same material as the second blocking insulating layer 150b. Accordingly, the energy band gap of the fourth blocking insulating layer may be equal to the energy band gap E _g2 of the second blocking insulating layer. In addition, according to another modified embodiment of the present invention, the blocking insulating layer 150 may further include the fourth blocking insulating layer and the fifth blocking insulating layer (not shown). The fourth blocking insulating layer may be formed of the same material as the second blocking insulating layer 150b and the fifth blocking insulating layer may be formed of the same material as the first blocking insulating layer 150a.

Meanwhile, according to one embodiment of the present invention, the nonvolatile memory element disclosed in the above embodiments can be included in an electronic system. The electronic system will be described in detail with reference to the drawings.

8 is a block diagram illustrating an electronic system having a non-volatile memory device according to embodiments of the present invention.

9, the electronic system 1300 may include a controller 1310, an input / output device 1320, and a storage device 1330. The controller 1310, the input / output device 1320, and the storage device 1330 are coupled to each other via a bus 1350. The bus 1350 corresponds to a path through which data is moved. The controller 1310 may include at least one of at least one microprocessor, a digital signal processor, a microcontroller, and logic elements capable of performing similar functions. The input / output device 1320 may include at least one selected from a keypad, a keyboard, and a display device. The storage device 1330 is a device for storing data. The storage device 1330 may store data and / or instructions that may be executed by the controller 1310. The storage device 1330 may include at least one of the non-volatile storage elements described in the above embodiments. The electronic system 3100 may further comprise an interface 1340 for transferring data to or receiving data from the communication network. The interface 1340 may be in wired or wireless form. For example, the interface 1340 may include an antenna or a wired or wireless transceiver.

The electronic system 1300 may be implemented as a mobile system, a personal computer, an industrial computer, or a system that performs various functions. For example, the mobile system may be a personal digital assistant (PDA), a portable computer, a web tablet, a mobile phone, a wireless phone, a laptop computer, a memory card A digital music system, or an information transmission / reception system. When the electronic system 1300 is a device capable of performing wireless communication, the electronic system 1300 may be used in a communication interface protocol such as a third generation communication system such as CDMA, GSM, NADC, E-TDMA, WCDAM, CDMA2000 .

Next, a memory card according to embodiments of the present invention will be described in detail with reference to the drawings.

9 is a block diagram showing a memory card having a nonvolatile memory element according to embodiments of the present invention.

9, the memory card 1400 includes a non-volatile memory device 1410 and a memory controller 1420. The non- The non-volatile memory device 1410 can store data or read stored data. The non-volatile memory device 1410 includes at least one of the non-volatile memory devices disclosed in the embodiments. The memory controller 1420 controls the flash memory 1410 to read stored data or to store data in response to a host read / write request.

1A and 1B are views showing a NAND nonvolatile memory element according to an embodiment of the present invention. 1B is a cross-sectional view taken along the line I-I 'in FIG. 1A.

2A and 2B are diagrams illustrating a NOR nonvolatile memory element according to an embodiment of the present invention. 2B is a cross-sectional view taken along the line III-III 'in FIG. 1A.

3 is a cross-sectional view taken along line II-II 'of FIG. 1A for explaining a nonvolatile memory device according to an embodiment of the present invention.

4A to 4D are views showing a flat band energy band diagram of a nonvolatile memory device according to an embodiment of the present invention.

5 is a diagram showing an energy band diagram when a negative erase voltage (V ₀ ) is applied to a nonvolatile memory device according to the present invention.

6 is a cross-sectional view taken along line II-II 'of FIG. 1A for explaining a nonvolatile memory device according to an embodiment of the present invention.

 7A to 7C are diagrams showing a flat band energy band diagram of a nonvolatile memory device according to an embodiment of the present invention.

8 is a block diagram illustrating an electronic system having a non-volatile memory device according to embodiments of the present invention.

9 is a block diagram showing a memory card having a nonvolatile memory element according to embodiments of the present invention.

Claims (17)

A tunnel insulating film formed on a semiconductor substrate; A charge storage film formed on the tunnel insulating film; A blocking insulating film formed on the charge storage film; And And a control gate electrode formed on the blocking insulating film, Wherein the blocking insulating film includes a first blocking insulating film, a second blocking insulating film, and a third blocking insulating film which are sequentially stacked, Wherein an energy band gap of the second blocking insulating film is larger than an energy band gap of the first blocking insulating film and the third blocking insulating film and a dielectric constant of the second blocking insulating film is larger than a dielectric constant of the first blocking insulating film and the third blocking insulating film Wherein the nonvolatile memory element is a nonvolatile memory element. The method according to claim 1, Wherein the charge storage film is an insulator or a conductive floating gate holding a charge trap site. delete 3. The method of claim 2, Wherein a trap density of the second blocking insulating film is smaller than a trap density of the first blocking insulating film and the third blocking insulating film. 3. The method of claim 2, The blocking insulating film  Further comprising at least one fourth blocking insulating layer on the third blocking insulating layer to alternate the materials having different energy band gaps. 3. The method of claim 2, Wherein the first blocking insulating film and the third blocking insulating film comprise at least one of a metal oxide film, a metal nitride film, and a metal oxide nitride film. 3. The method of claim 2, Wherein the second blocking insulating film comprises at least one of a silicon oxide film, a metal oxide film, a metal nitride film, and a metal oxide nitride film. 3. The method of claim 2,  Wherein the charge storage film comprises at least one of a silicon nitride film, a metal quantum dot, a silicon quantum dot, a metal, doped silicon, and doped germanium. 3. The method of claim 2, Wherein the floating gate includes at least one of an N-type conductivity-type polysilicon, a P-type conductivity-type polysilicon, a metal, and doped germanium. 9. The method of claim 8, Wherein the metal comprises at least one of a pure metal and a metal mixture. delete delete delete delete delete delete A semiconductor substrate; An insulating film defining a first active region on the semiconductor substrate, the insulating film being spaced apart from the first active region and defining a second active region on the semiconductor substrate; A first tunnel insulating film formed on the first active region of the semiconductor substrate; A first charge storage pattern formed on the first tunnel insulating film; A first interface layer pattern formed on the first charge storage pattern; (HfSiO), a zirconium oxide film (ZrO2), or a tantalum oxide film (Ta2O5), which is formed on the first interface film pattern and is formed of at least one of an aluminum oxide film (Al2O3), a hafnium oxide film (HfO2), a hafnium aluminum oxide film (HfAlO), a hafnium silicon oxide film A blocking insulating pattern comprising a material different from said first interface film pattern; A control gate electrode formed on the blocking insulating pattern; A second tunnel insulating film formed on the first active region of the substrate; A second charge storage pattern formed on the second tunnel insulating film; And And a second interface film pattern formed on the second charge storage pattern, Wherein the first and second interface film patterns comprise a conductive or semiconductive material, the first and second interface film patterns being spaced apart, Wherein the control gate electrode continuously extends across the first and second active regions and a first charge storage pattern is disposed between the control gate electrode and the first active region, A control gate electrode, and the second active region.

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