KR101426558B1 - Method and appratus for transmitting and receiving data in a communication system using low density parity check code - Google Patents

Abstract

The data transmitting apparatus of the present invention is characterized in that when information data bits are input, the information data bits are encoded to generate an LDPC codeword, and the LDPC codeword is interleaved, and the interleaved LDPC codeword is converted into a signal constellation bit Modulates a signal constellation bit for outputting a mapping signal and outputs the modulated signal by higher-order modulating the mapping signal, and RF-processes the modulated signal and transmits the modulated signal to a receiver through a transmission antenna RF processing, and the signal constellation bit mapping is performed differently according to a modulation scheme.

Low density parity check (LDPC) code, higher order modulation, signal constellation bit mapping, interleaving

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a data transmission / reception apparatus and a data transmission method in a communication system using a low-

The present invention relates to an apparatus and method for transmitting and receiving data in a communication system, and more particularly, to an apparatus and method for transmitting and receiving data in a communication system using an LDPC code.

Generally, a general procedure of data transmission and reception in a communication system is as follows. That is, the data generated from the source of the transmission side is transmitted through a channel through Source Coding, Channel Coding, Interleaving, Modulation, and the like. In addition, the receiving side receives the wirelessly transmitted signal and performs demodulation, deinterleaving, channel decoding, and source decoding.

However, in a communication system, various noise, fading and inter-symbol interference (ISI) of a channel cause signal distortion. Especially, in high-speed digital communication systems requiring high data throughput and reliability such as next generation mobile communication, digital broadcasting, and portable Internet, techniques for overcoming signal distortion due to noise, fading and ISI are essential. The channel coding and interleaving correspond to typical techniques.

Interleaving is a technique for minimizing data transmission loss by preventing frequent occurrence of burst errors while passing through a fading channel by distributing the damaged bits of the bits to be transmitted to a plurality of places without being concentrated in one place, It is used to raise the effect.

In addition, channel coding is widely used as a method for improving the reliability of communication by allowing the receiver side to confirm the distortion of the signal due to noise, fading and ISI and to restore the signal efficiently. Code used for channel coding is called an error-correcting code (ECC) in the sense of correcting errors, and various types of error correction codes are actively studied.

Generally known error correction codes include a block code, a convolutional code, a turbo code, and a low density parity check code (LDPC code). Since the present invention described below relates to a communication system using an LDPC code, a brief description of an LDPC code will be given below.

An LDPC code can not guarantee complete transmission of a signal but is known as a code that minimizes the probability of information loss. That is, the LDPC code was first proposed in the 1960s as the first channel coding code capable of transmitting signals at a level close to the maximum data rate (Shannon limit) known in Shannon's channel coding theory. However, LDPC codes were difficult to implement at the level of technology at that time, so they were not actually used. However, with the development of information theory and technology in the future, studies on the characteristics and generation methods of codes that do not significantly increase complexity using iterative decoding since 1996 have been rediscovered. It is. This LDPC code is evaluated as a very good error correction code that can be used in a next generation mobile communication system in addition to the turbo code.

The LDPC codes are typically represented using graphical representations, and many features can be analyzed through graph theory, algebra, and probability-based methods. Generally, a graph model of a channel code is useful not only for describing codes but also to correspond information of encoded bits to a vertex in a graph and to correspond each bit relation to edges in a graph , It is possible to derive a natural decryption algorithm because each vertex can be regarded as a communication network for exchanging messages determined by each line. For example, trellis-derived decoding algorithms, which can be regarded as a kind of graph, include the well-known Viterbi algorithm and BCJR (Bahl, Cocke, Jelinek and Raviv) algorithms.

The LDPC code can be expressed using a bipartite graph, which is generally defined as a parity-check matrix and is collectively referred to as a Tanner graph. Herein, the half graph means that the vertices constituting the graph are divided into two different types. In the case of the LDPC code, a binary graph composed of a variable node and a vertex called a check node Is expressed. Here, the variable node corresponds one-to-one with the encoded bit.

Hereinafter, a graphical representation method of the LDPC code will be described with reference to FIGS. 1 and 2. FIG. 1 is an exemplary diagram of a parity check matrix H1 of an LDPC code. In FIG. 1, it is assumed that a parity check matrix of an LDPC code including four rows and eight columns is assumed. The matrix of FIG. 1 represents an LDPC code generating codeword of length 8 by having eight columns. That is, each column corresponds to the encoded 8 bits.

2 is a graphical representation of a parity check matrix H1 of an LDPC code. That is, FIG. 1 shows a Tanner graph corresponding to H1 in FIG. 2, the Tanner graph of the LDPC code includes eight variable nodes x ₁ (202), x ₂ (204), x ₃ (206), x ₄ (208), x ₅ (210) ₆ 212, x ₇ 214 and x ₈ 216 and four check nodes 218, 220, 222 and 224. Here, the i-th column and the j-th row of the parity check matrix H1 of the LDPC code correspond to the variable nodes x _i and j-th check nodes, respectively. The value of 1, that is, a value other than 0 at the intersection of the i-th column and the j-th row of the parity check matrix H1 of the LDPC code means that the variable nodes x _i and j And the edge is present between the first check node and the second check node.

In the Tanner graph of the LDPC code, the degree of the variable node and the check node means the number of line segments connected to the respective nodes. This means that in the parity check matrix of the LDPC code, It is equal to the number of nonzero entries. For example, in FIG. 2, variable nodes x ₁ 202, x ₂ 204, x ₃ 206, x ₄ 208, x ₅ 210, x ₆ 212, x ₇ 214 ), the order of the x ₈ (216) are each in sequence 4, 3, 3, 3, 2, 2, 2, and 2, the degree of the check nodes (218, 220, 222, 224) is 6, as each sequence , 5, 5, 5. In addition, the number of non-zero elements in each column of the parity check matrix H1 of FIG. 1 corresponding to the variable nodes of FIG. 2 corresponds to the order of 4, 3, 3, 2, 2, 2, And the number of non-zero elements in each row of the parity check matrix H1 of FIG. 1 corresponding to the check nodes in FIG. 2 is in the order of the above-mentioned orders 6, 5, 5, Match.

As described above, each bit encoded corresponds to a column of a parity check matrix one-to-one, and also corresponds to a variable node on the Tanner graph on a one-to-one basis. The degree of the variable node corresponding one-to-one with the encoded bit is also referred to as the degree of the encoded bit.

It is known that LDPC codes have better decoding performance than codeword bits having a high degree of codeword bits having a low degree. This is because the decoding performance can be improved as the higher-order variable node obtains more information through iterative decoding than the lower-order variable node.

So far, we have studied LDPC codes. Hereinafter, a signal constellation when a QAM (Quadrature Amplitude Modulation) scheme, which is a higher order modulation scheme used in a communication system, will be described. The modulated symbols in QAM are composed of real part and imaginary part, and various modulation symbols can be constructed by varying the size and sign of each real part and imaginary part. In order to examine the characteristics of the QAM, a QPSK modulation scheme will be described.

3A is a schematic diagram of a signal constellation of a general QPSK (Quadrature Phase Shift Keying) modulation scheme. y ₀ determines the sign of the real part and y ₁ determines the sign of the imaginary part. That is, when y ₀ is 0, the sign of the real part is positive (plus: +), and when y ₀ is 1, the sign of the real part is minus (-). The sign of the imaginary part is positive (+) when y ₁ is 0, and the sign of the imaginary part is negative (-) when y ₁ is 1. y ₀ , and y ₁ are the sign bits indicating the sign of the real part and the imaginary part, the error occurrence probability of y ₀ , y ₁ is the same. Therefore, in the case of the QPSK modulation method, (y ₀ , y ₁ ) The reliability of each bit is the same. Here, denoted by y _{0, q,} y _{1, q} , the second subscript index q indicates the q-th output of the modulated signal constituent bits.

3B is a schematic diagram of a signal constellation of a general 16-QAM modulation scheme. The meaning of (y ₀ , y ₁ , y ₂ , y ₃ ) corresponding to one modulation signal bit is as follows. The bits y ₀ and y ₂ determine the sign and magnitude of the real part, respectively, and the bits y ₁ and y ₃ respectively determine the sign and magnitude of the imaginary part. In other words, y ₀ and y ₁ determine the sign of the real and imaginary parts of the signal, and y ₂ and y ₃ determine the magnitude of the real and imaginary parts of the signal. Since it is easier to determine the sign than to determine the magnitude of the modulated signal, the probability of error for y ₂ and y ₃ is higher than y ₀ and y ₁ . Therefore, the probability or reliability that the errors of the bits do not occur is the order of R (y ₀ ) = R (y ₁ )> R (y ₂ ) = R (y ₃ ). Where R (y) represents the reliability for bit y. Unlike QPSK, the modulated signal constituent bits (y ₀ , y ₁ , y ₂ , y ₃ ) of the QAM differ in the reliability of each bit.

In the 16-QAM modulation scheme, two of the four bits constituting the signal determine the sign of the real part and the imaginary part of the signal, and two bits represent the size of the real part and the imaginary part of the signal (y ₀ , y ₁ , y ₂ , y ₃ ) and the role of each bit can be changed.

3C is a schematic diagram of a signal constellation of a general 64-QAM modulation scheme. Here, bits y ₀ , y _2, and y ₄ of (y ₀ , y ₁ , y ₂ , y ₃ , y ₄ , y ₅ ) corresponding to one modulation signal bit determine the sign and magnitude of the real part, ₁ , y ₃ and y ₅ determine the sign and magnitude of the imaginary part. Where y ₀ and y ₁ determine the sign of the real and imaginary parts, respectively, and y _2, y ₃ , y _{4 and} y ₅ determine the magnitude of the real and imaginary parts, respectively. The reliability of y ₀ and y ₁ is higher than the reliability of y _2, y ₃ , y _{4 and} y ₅ because it is easier to distinguish the code than to determine the size of the modulated symbol. y _{2 and} y ₃ are determined according to whether the size of the modulated symbol is larger or smaller than _{4 and} y _{4 and} y ₅ are determined based on whether the size of the modulated symbol is close to 4 and 0 based on 2, 6 < / RTI > Therefore _, the size of the determination range of y _{2 and} y ₃ is 4, and the determination range of y _{4 and} y ₅ is 2. Therefore _, the reliability of y _2, y ₃ is higher than y _4, y ₅ . Summarizing this, the probability that is, the reliability does not occur an error of each bit _{R (y 0) = R (} y 1)> R (y 2) = R (y 3)> R (y 4) = R (y ₅ ).

In the 64-QAM modulation scheme, two of the 6 bits constituting the signal determine the sign of the real part and the imaginary part of the signal, and the four bits are only required to indicate the size of the real part and the imaginary part of the signal. Therefore, the order of (y ₀ , y ₁ , y ₂ , y ₃ , y ₄ , y ₅ ) and the role of each bit may vary. In the case of a signal constellation of 256-QAM or higher, the role and reliability of the modulation signal constituting bits are changed in the same manner as described above. That is, one of the modulation signals as bits _{(y 0, y 1, y} 2, y 3, y 4, y 5, y 6, y 7) when _{called, R (y 0) = R} (y 1)> R ( _{y 2) = R (y 3} )> R (y 4) = R (y 5)> R (y 6) a = R (y ₇₎ is established.

Conventionally, when interleaving / deinterleaving is performed in a communication system using an LDPC code, an arbitrary interleaving / deinterleaving method may be used regardless of the reliability characteristics of the LDPC code or the modulation code bits of the higher order modulation, The interleaving / deinterleaving scheme considering only the order of the nodes or the check nodes is used, so that the distortion of the signals transmitted through the channels can not be minimized. In addition, since two consecutive bits y _2i and y _{2i + 1 in} the modulation symbol have the same reliability, the two bits are grouped into one bit group that is not two separate bits such as a real part and an imaginary part There is a problem in that the performance of the LDPC code can not be maximized.

Accordingly, the present invention provides a transmitting and receiving apparatus and method for reducing signal distortion in a communication system using an LDPC codeword.

The present invention also provides an interleaving apparatus and method for improving the performance of an LDPC codeword in a communication system using an LDPC codeword.

The present invention also provides a signal constellation bit mapping apparatus and method for improving the performance of an LDPC codeword in a communication system using an LDPC codeword.

A data transmission method of a communication system using a low density parity check (LDPC) matrix according to an exemplary embodiment of the present invention includes the steps of generating an LDPC codeword by encoding information data bits when information data bits are input Interleaving the generated LDPC codeword; outputting a mapping signal by mapping a signal constellation bit of the interleaved LDPC codeword; and outputting a modulation signal by performing higher-order modulation on the output mapping signal, And transmitting the modulated signal to a receiver through a transmission antenna, wherein the bits included in the generated LDPC codeword are arranged in descending order of order, The modulation signal is divided into groups of the same number as the number of bits included in the modulation signal, At least one bit included in the first group is mapped to at least one least reliable or least reliable bit among the bits contained in the modulation signal and at least one bit included in the first group At least one bit included in a second group including at least one bit subsequent to at least one bit included in the first group is mapped to at least one bit that is the most reliable, And when at least one bit included in the first group is mapped to at least one bit having the least reliability, the bit included in the modulated signal is mapped to at least one bit of the least reliable bit among the bits included in the modulated signal, At least one bit included in the second group is mapped to at least one bit having the highest reliability.
The data transmission apparatus of a communication system using a low density parity check (LDPC) matrix according to an embodiment of the present invention generates an LDPC codeword by encoding the information data bits when information data bits are input An interleaver for interleaving the LDPC codeword; a bit mapper for mapping the interleaved LDPC coders to a signal constellation bit map and outputting a mapping signal; and a high-order modulator for outputting a modulated signal And a transmitter for transmitting the modulated signal to a receiver through a transmission antenna, wherein the bits included in the generated LDPC codeword are arranged in order of the order and are included in the modulation signal. And the lowest order bits of the groups are included At least one bit included in the first group is mapped to at least one least reliable or least reliable bit among the bits contained in the modulation signal and at least one bit included in the first group At least one bit included in a second group including at least one bit subsequent to at least one bit included in the first group is mapped to at least one bit that is the most reliable, And when at least one bit included in the first group is mapped to at least one bit having the least reliability, the bit included in the modulated signal is mapped to at least one bit of the least reliable bit among the bits included in the modulated signal, At least one bit included in the second group is mapped to at least one bit having the highest reliability.

The effects according to the present invention are as follows.

First, using the present invention, the performance of an LDPC codeword can be maximized in a communication system using an LDPC codeword. Further, by using the method of the present invention, the decoding performance of the LDPC code is improved. In particular, the present invention improves the reliability of bits having low error correction capability among the bits constituting the LDPC code. In addition, the present invention can improve the reliability of data transmission and reception by enhancing the performance of a link especially in a radio channel environment in which the performance of a link is deteriorated due to noise, fading phenomenon and intersymbol interference (ISI). In addition, the transmission and reception of a reliable LDPC code in the present invention reduces the error probability of a signal in the entire communication system, thereby enabling high-speed communication.

The operation principle of the preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The following terms are defined in consideration of the functions of the present invention, and may be changed according to the intentions or customs of the user, the operator, and the like. Therefore, the definition should be based on the contents throughout this specification.

4 is a configuration diagram of a communication system using an LDPC code according to an embodiment of the present invention. Hereinafter, a configuration of a communication system using an LDPC code according to an embodiment of the present invention will be described with reference to FIG.

The transmitter 400 of the present invention includes an encoder 411, an interleaver 413, a constellation bit mapper (constellation bit mapping) 415 Quot; group "), and a modulator 417. The receiver 450 of the present invention may further include a demodulator 457, a signal constellation bit demapping 455 (hereinafter abbreviated as a "bit demapper"), a demodulator An interleaver 453, and a decoder 451. [

The operation of the transmitter and receiver of the present invention will be briefly described with reference to FIG. 4, and the configuration and operation of the interleaver and bit mapper proposed in the present invention will be described in detail with reference to FIG.

First, when i, which is an information data bit stream, is input to the transmitter 400, i is transmitted to an encoder 411. The encoder 411 encodes the information data bits in a predetermined manner, codeword x and outputs it to the interleaver 413. Here, the encoder 411 is an LDPC encoder and the codeword generated by the encoder 411 is an LDPC codeword.

The interleaver 413 interleaves the LDPC codeword output from the encoder 411 in a predetermined manner and outputs the interleaved signal constellation bit mapper 415. The interleaving operation of the interleaver 413 is performed according to the interleaving scheme proposed in the present invention. A detailed description of the interleaving method will be described later.

The bit mapper 415 maps the bits output from the interleaver 413, that is, the interleaved LDPC code word b, to a modulator 417 in a predetermined manner. The bit mapper 415 is mapped according to the mapping scheme proposed by the present invention. The mapping scheme maps the bits constituting the modulation symbol according to the degree characteristic of b, and a detailed description thereof will be described later.

The modulator 417 modulates the signal output from the bit mapper 415 in a predetermined manner and transmits the modulated signal through a transmission antenna (Tx.Ant). The interleaver 413 and the bit mapper 415 of the present invention minimize the bit error rate (BER) or the frame error rate (FER) when the modulator 417 modulates the b Interleaving and bit mapping to improve performance.

The interleaver 413 and the bit mapper 415 design the relation between the codeword bit, which is the input signal of the interleaver, and the modulation signal configuration bit, which is the output signal of the bit mapper, to satisfy the following rules. It is assumed that the number of bits of the LDPC codeword is N and the 2 ^2m -QAM modulation scheme is used.

Rule 1) N / 2m bits are mapped to the most reliable bit or the least reliable bit among the modulated signal constituent bits in descending order of the LDPC codeword bits.

Rule 2) When N / 2m bits are mapped to the most reliable bits in the rule 1), the order of the LDPC codeword bits is mapped to the lowest order bits excluding the bits corresponding to the rule 1) Mapped to the bits having the lowest reliability among the bits, and when the mapped bits are mapped to the least reliable bits in the rule 1), the mapped bits are mapped to the most reliable bits among the modulation signal configuration bits.

Rule 3) N / 2m bits are mapped to the least reliable bits among the modulated signal constituent bits in descending order of the LDPC codeword bits.

Rule 4) N / 2m bits of the LDPC codeword bits are mapped to the remaining bits of the modulated signal constituent bits in order of the next highest order in the rule 3).

Let's take a closer look at the methods that are mapped according to each rule below.

Rule 1), for example, code in the order are sorted from highest to lowest of air _{c = [c 1 c 2 c} 3 ... c N] from _{[c NN / 2m + 1 c} NN / 2m + 2 c NN / _{2m + 3} ... c _N ] are mapped to the bits having the highest reliability among the modulation signal configuration bits. _I. E., The most reliable y ₀ or y ₁ bits in the modulation signal configuration symbol.

For example, in the rule 2), N / 2m bits corresponding to c = [ _{cNN / m + 1cNN / m + 2cNN / m + 3} ... _{cNN / 2m} ] The mapped bits are mapped to the bits having the lowest reliability among the modulation signal configuration bits because they are mapped to the most reliable bits. That is, the use of 256-QAM as the modulation method, _{c = [c 6N / 4 +} 1 c 3N / 4 + 2 c 3N / 4 + 3 ... c 7N / 8] reliability is lowest y ₆ y or the ₇ bits. However, when mapping to y ₆ or y ₇ bits in Rule 1), rule 2) maps to y ₀ or y ₁ bits.

For example, in rule 3), N / 2m bits corresponding to [c ₁ c ₂ c ₃ ... c _{N / 2m} ] are mapped to the least reliable bits among the modulation signal configuration bits. That is, when 256-QAM is used as a modulation scheme, [c ₁ c ₂ c ₃ ... c _{N / 8} ] is mapped to the least reliable y ₆ or y ₇ bits. In this case, in the rule 2), y ₆ (y ₇ ) is mapped to y ₇ (y ₆ ) in the rule 3).

Rule 4), for _{example, [c N / 2m + 1} c N / 2m + 2 c N / 2m + 3 ... c N / m] N / 2m bits corresponding to the modulation signal are of the configuration bits And maps to the remaining bits. That is, when 256-QAM is used as a modulation scheme, [c _{N / 8 + 1} c _{N / 8 + 2} c _{N / 8 + 3} ... c _{N / 4} ] To the bits excluding the mapped bits.

By constructing the relationship between the LDPC codeword bits and the modulated signal constituent bits as described above, the decoding performance of the LDPC codeword can be improved. The most significant feature of the rule is that, although the reliability of the bits constituting the modulated signal is the same, the real part and the imaginary part are distinguished from each other by different bits.

In the prior art, only a simple mapping method which distinguishes only the error correction ability according to the order and the reliability according to the modulation signal configuration bit is found. However, according to the present invention, an optimized mapping method is further searched by dividing the bit having the same reliability into a real part and an imaginary part . The reason why the mapping method using the above rule can obtain excellent performance is as follows.

Since the high order bits of the LDPC codeword are superior to the low order bits, even if they are mapped to the low-reliability modulation signal configuration bits, they can be restored to the original signal sufficiently in the decoding process. However, if the ratio of the high order bits in the codeword bits is large, the influence of the bits having a high order in the decoding process becomes large. At this time, many bits of the higher order are mapped to lower reliability, and the adverse effect of low reliability is increased. Thus, mapping the modulated signal constituent bits, which all have a low degree of reliability to a higher order, to a constituent bit having only a low degree of reliability, rather than mapping the modulated signal constituent bits, makes it possible to improve performance.

The performance of LDPC codeword can be improved by mapping low order bits to modulated signal configuration bits that are small in capability of correcting errors during decoding but have high reliability. However, mapping low-order bits to high-reliability modulation signal configuration bits may result in a low reliability impact because all higher-order bits are mapped to low-reliability modulation signal configuration bits. Therefore, it is possible to improve the performance by mapping to a configuration bit having only a part of high reliability rather than mapping the modulation signal configuration bits having high reliability to all of the low order. However, mapping only the modulated signal constituent bits having low reliability to the low order bits can seriously degrade the error correcting ability of the low order bits and cause an error floor. do.

In order to obtain excellent performance when mapping as described above, the present invention can be suitably applied to a case where there are relatively many bits having a high degree.

Meanwhile, the receiver 450 receives the signal transmitted from the transmitter 400, and outputs the signal through a process reverse to that of the transmitter 400. That is, the signal input to the receiver 450 through the reception antenna Rx. Ant is transmitted to the demodulator 457. The demodulator 457 demodulates the received signal in a demodulation scheme corresponding to the modulation scheme of the modulator 417 of the transmitter 400 and outputs the demodulated signal to the bit demapper 455. The bit demapper 455 bit demaps the signal output from the demodulator 457 according to the mapping scheme performed by the bit mapper 415 of the transmitter 400 and outputs the bit demapper 453 to the de-interleaver 453 . The deinterleaver 453 deinterleaves the signal output from the bit demapper 455 to correspond to the interleaving scheme applied by the interleaver 413 of the transmitter 400 and outputs the deinterleaved signal to the decoder 451. The decoder 451 decodes the deinterleaved signal using the decoding scheme corresponding to the scheme applied by the encoder 411 of the transmitter 400 and restores the final information data bit.

4, the signal output from the modulator 417 is subjected to RF processing in an RF transmitter (not shown in FIG. 4) for transmitting a radio frequency (RF) signal, And a signal received from the receiving antenna is subjected to RF processing in an RF receiving section (not shown in FIG. 4) for RF signal receiving processing and input to the demodulator 457.

The transmitter of the present invention is characterized by an interleaver 413 and a bit mapper 415 that use a unequal reliability characteristic of a higher order modulation scheme and the receiver of the present invention has an unequal reliability Interleaver 453 and a bit demapper 455 using the characteristics. 5, the operation of the interleaver and signal constellation bit mapper proposed in the present invention will be described in detail.

5 is a configuration diagram of an interleaver and a signal constellation bit mapper according to an embodiment of the present invention.

As shown in FIG. 5, it can be seen that the bit mapper 415 of FIG. 4 is composed of a demultiplexer (DEMUX). 5 shows a method using a QPSK modulation signal. The second method shown in (2) is a method using a 16-QAM modulation signal. The third example shown in (3) -QAM modulated signal, and (4) shown in the fourth figure shows a method of using a 256-QAM modulated signal, respectively. In the following, we will discuss four methods together.

When the encoded signal x is input to the corresponding interleaver 511, 531, 551, and 571 according to each modulation method, the interleaved signal is interleaved to output the interleaved signal b. The interleaved signal b is input to the corresponding demultiplexing units 521, 541, 561 and 581, and separated into a plurality of streams. That is, (1) is divided into two streams because it is QPSK, (2) is divided into 4 streams because it is 16-QAM, (3) is divided into 6 streams because , And (4) are 256-QAM cases, so they are separated into 8 streams. That is, the signals input through the configuration of FIG. 5 are interleaved according to a corresponding scheme, and then separated into a plurality of streams and output.

Each of the demultiplexers 521, 541, 561, and 581 receives a stream and separates the stream into a plurality of streams to form bits of a modulated signal. In the present invention, interleaved codewords are divided into bits of a modulated signal It is important to know which bit is composed. Hereinafter, the case of using the (2) 16-QAM modulation signal, which is the second operation among the demultiplexing units 521, 541, 561 and 581, will be described in detail. In the case where other modulation signals are used, the same method as that in which the 16-QAM modulation signal is used can be applied, and a description thereof will be omitted.

First, LDPC codeword bits x ₀ , x ₁ , ..., x _N-2 , x _N-1 are input to the interleaver 531. The interleaving scheme is determined by simultaneously considering the bit mapping scheme of each modulated signal, the degree distribution of bits of the LDPC code, and the reliability of each signal constellation bit. Let's take a closer look at this.

The output bits b ₀ , b _1, ..., b _N-2 , b _N-1 of the interleaver 531 are input to a demultiplexer 541 and demultiplexed to the number of bits constituting the modulated signal. That is, in the case of 16-QAM, since the modulated signal is composed of 4 bits, the input bits of the demultiplexer 541 are demultiplexed into 4 bits and output. At this time, four consecutive bits b ₀ , b _1, b ₂ , b ₃ and y ₀ , y ₁ , y ₂ , the bit mapping method is determined according to a mapping relation with y ₃ . Hereinafter, the interleaving method and bit mapping method according to the present invention will be described in detail. The interleaver and bit mapper proposed by the present invention are designed according to the above-mentioned rules.

5, the output bits y ₀ , y ₁ , y ₂ of the demultiplexer 541, y ₂ , y ₃ of y ₀ , y ₂ constitute the real part and y ₁ and y ₃ constitute the imaginary part. Hereinafter, the design process of the interleaver according to the embodiment of the present invention will be described. The designing process of the interleaver according to the present invention follows the following steps.

First , the number of columns of the interleaver is determined so as to be equal to the number of bits used in the modulation symbol, that is, the number of modulation signal configuration bits.

Step 2 : The number of interleaver rows is determined by dividing the length of the codeword by the number of columns determined in the first step.

Step 3 : The LDPC codeword bits are written in the order of the columns in the determined interleaver.

Step 4: One bit is read out from each column in which a codeword bit is written.

In Table 1 below, the row and column sizes of the interleaver according to the respective modulation schemes are shown by taking the case where the codeword length is 16200 and 64800, for example.

Hereinafter, the design and operation of the interleaver will be described with reference to FIG. 6, for example. In the following description, it is assumed that the LDPC matrix is sequentially arranged from a row having a higher order. The reason for this assumption is as follows. That is, as described above, the higher the degree of the codeword bits corresponding to the variable nodes of the LDPC matrix, the better the decoding performance. Therefore, the corresponding bits of the codeword generated by assuming the LDPC matrix arranged in descending order are also arranged in descending order, and the codeword bits arranged in the descending order indicate the order of decoding performance between the respective bits.

6 is an exemplary diagram illustrating an operation of an interleaver according to an embodiment of the present invention. The interleaver of FIG. 6 uses a 256-QAM modulation scheme and assumes that the length of an LDPC codeword is 64,800. The description will be made in accordance with four steps of the design and operation of the above-described interleaver.

In the first step, eight columns are used as the number of bits used in 256-QAM, and in the second step, the number of bits of the row is determined as 64800/8 = 8100. In the third step, LDPC codeword bits are sequentially input to each column. When the input of each column is completed, input is performed to the next column as shown, and the number of bits input to each column at this time is 8100, which is the number of the rows calculated in the above. In accordance with the fourth step, one bit is sequentially output from each column. In the case of FIG. 6 (a), the data is sequentially output from the first bit of the column 1 to the first bit of the column 8, and then sequentially outputted from the second bit of the column 1 to the second bit of the column 8. Repeat the above procedure for the number of rows (8100).

The LDPC codeword is interleaved through the above process. In addition, in order to further enhance interleaving performance, arbitrary interleaving may be performed in each column. If there is a correlation between adjacent codeword bits, interleaving may be performed to be stronger for a burst error.

The interleaving method has been described so far. Hereinafter, the bit mapping method proposed by the present invention will be described. The bit mapping scheme described below maps the bit with the highest order based on the output of one row of the interleaving output of the LDPC codeword to one of the bits with the lowest reliability among the modulation signal configuration bits constituting the modulation signal, The bit having the lowest order is mapped to one of the bits having the highest reliability among the modulation signal configuration bits and the bit having the same order or the next bit is mapped to one of the bits having the lowest reliability among the modulation signal configuration bits, We propose a bit mapping method that minimizes the error rate.

Among the output values of the interleaver described in FIG. 6, column 1 is allocated to the least reliable bit among the modulation signal configuration bits, and bits output from column 7 and column 8 are allocated to bits having the lowest reliability among the modulation signal configuration bits And is assigned to the highest bit. As shown in FIG. 6A, when an interleaver sequentially outputs bits from column 1 to bits of column 8, an embodiment of a method in which the output bits of the interleaver are allocated to modulation signal configuration bits according to the 256-QAM modulation scheme As shown in Table 2 below.

<256-QAM - Method 1> b _{8k + 0} maps to y _{6, k}
b _{8k + 1} maps to y _{5, k}
b _{8k + 2} maps to y _{1, k}
b _{8k + 3} maps to y _{3, k}
b _{8k + 4} maps to y _{4, k}
b _{8k + 5} maps to y _{2, k}
b _{8k + 6} maps to y _{7, k}
b _{8k + 7} maps to y _{0, k} &Lt; 256-QAM - Method 2 > b _{8k + 0} maps to y _{6, k}
b _{8k + 1} maps to y _{3, k}
b _{8k + 2} maps to y _{5, k}
b _{8k + 3} maps to y _{4, k}
b _{8k + 4} maps to y _{2, k}
b _{8k + 5} maps to y _{1, k}
b _{8k + 6} maps to y _{7, k}
b _{8k + 7} maps to y _{0, k}

If the number of codeword bits is N, the output bits of the interleaver are b = {b ₀ , b ₁ , b ₂ , b ₃ , b ₄ , b ₅ , b ₆ ,. . . , b _N }. Also, the modulation signal constituent bits output from the k-th modulation signal constituting bits are denoted as y _{0, k} . (Y _{0, k} , y _{1, k} , y _{2, k} , y _{3, k} , y _{4, k} , y _{5, k} , y _{6, k} , y _{7, k} ) in the case of 256-QAM . Where k = 0, 1, ..., N / 8-1.

Referring to Table 2, it can be seen that bits corresponding to b0, b6, and b7 satisfy all of the rules 1), 2), 3) and 4). In the case of 256-QAM in Table 2, there are eight bits, two bits having the highest reliability, four bits having the middle reliability, and two bits having low reliability. Therefore, in the case of 256-QAM, there can be various interleavers which can be configured according to the design rule of the present invention. In other words, a modification of the interleaver conceptually equivalent to the < 256-QAM-method 1 > and the < 256-QAM-method 2 >

&Lt; 256-QAM - Method 1, Variant > b _{8k + 0} maps to y _{7, k}
b _{8k + 1} maps to y _{4, k}
b _{8k + 2} maps to y _{0, k}
b _{8k + 3} maps to y _{2, k}
b _{8k + 4} maps to y _{5, k}
b _{8k + 5} maps to y _{3, k}
b _{8k + 6} maps to y _{6, k}
b _{8k + 7} maps to y _{1, k} &Lt; 256-QAM - Method 2, Variant > b _{8k + 0} maps to y _{7, k}
b _{8k + 1} maps to y _{2, k}
b _{8k + 2} maps to y _{4, k}
b _{8k + 3} maps to y _{5, k}
b _{8k + 4} maps to y _{3, k}
b _{8k + 5} maps to y _{0, k}
b _{8k + 6} maps to y _{6, k}
b _{8k + 7} maps to y _{1, k}

In order to facilitate understanding, input and output of signals according to the interleaving and bit mapping method proposed in the present invention will be described with reference to FIG.

7 is an exemplary diagram illustrating an interleaving and bit mapping method according to an embodiment of the present invention. Assuming that the modulation scheme is 256-QAM and the length of the codeword is 24, the size of the column of the interleaver is 8 and the size of the row is 3. Assume that the bit mapping method applies the above < 256-QAM-method 1 >.

A code word output from the LDPC encoder _{X = [x 0, x 1} , x 2, x 3, x 4, x 5, x 6, x 7, x 8, x 9, x 10, x 11, x 12, _{x 13, x 14, x 15} , x 16, x 17, x 18, x 19, x 20, x 21, x 22, x 23] referred to the order of the respective bits [8, 8, 8, 8, 8 , 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2]. When the interleaver 551 writes the codeword bits in the column order, {x ₀ , x ₁ , x ₂ } is stored in column 1 of the interleaver 551 and {x ₃ , x ₄ , x ₅ } There _{{x 6, x 7, x} 8}, column 4 is _{{x 9, x 10, x} 11}, column 5 is _{{x 12, x 13, x} 14}, column 6 , the {x _15, x _16, x ₁₇ } for column 7, {x ₁₈ , x ₁₉ , x ₂₀ } for column 7, and {x ₂₁ , x ₂₂ , x ₂₃ } for column 8. B = b ₀ , b ₁ , b ₂ , b ₃ , b ₄ , b ₅ , b ₆ , b ₇ = x ₀ , x ₃ , x ₆ , x ₉ , x ₁₂ , x ₁₅ , x ₁₈ , x ₂₁ ].

If b is input to the demultiplexing unit 551 are mapped according to the mapping rule of _{y = {y 0,0, y 1,0} , y 2,0, y 3,0, y 4,0, y 5, _{0, y 6,0, y 7,0}} = {b 7, b 2, b 5, b 3, b 4, b 1, b 0, b 6} = {x 21, x 6, x 15, x ₉ , x ₁₂ , x ₃ , x ₀ , x ₁₈ }. That is, codewords mapped to y _0,0 and y _1,0 , which are the most reliable code determination bits, are x ₂₁ , x ₆ . It is also the most reliable low bit-size of y _6,0, y _7,0 a high-order codeword decoding performance x ₁₈ poor excellent bits x ₀ and the lower-order decoding performance is mapped on.

The interleaving and bit mapping schemes described so far are such that the output of the interleaver 551 is output in the direction of column 1 to column 8 and is bit mapped accordingly. Such interleaving scheme and bit mapping scheme will be referred to as 'forward interleaving' and 'forward bit mapping'. In the present invention, the forward direction is defined as 'direction of column 1 to column 8', but in some cases, 'direction of column 1 in column 8' may be defined as a forward direction.

However, the interleaver 551 does not need to output codeword bits only in the forward direction as shown in FIG. 6 (a). Therefore, if the interleaver 551 outputs the codeword bits in a direction opposite to that of FIG. 6A, which can be referred to as 'reverse direction' in the same sequence as FIG. 6B, the mapping method of the bit mapper 560 Can be changed in the manner shown in Table 4 below. This is defined as 'reverse interleaving' and 'reverse bit mapping'.

&Lt; 256-QAM - Method 1, Variation 2 > b _{8k + 0} maps to y _{0, k}
b _{8k + 1} maps to y _{7, k}
b _{8k + 2} maps to y _{2, k}
b _{8k + 3} maps to y _{4, k}
b _{8k + 4} maps to y _{3, k}
b _{8k + 5} maps to y _{1, k}
b _{8k + 6} maps to y _{5, k}
b _{8k + 7} maps to y _{6, k} &Lt; 256-QAM - Method 2, Variation 2 > b _{8k + 0} maps to y _{0, k}
b _{8k + 1} maps to y _{7, k}
b _{8k + 2} maps to y _{1, k}
b _{8k + 3} maps to y _{2, k}
b _{8k + 4} maps to y _{4, k}
b _{8k + 5} maps to y _{5, k}
b _{8k + 6} maps to y _{3, k}
b _{8k + 7} maps to y _{6, k}

An example of the mapping by the reverse bit mapping scheme according to the reverse interleaving shown in FIG. 6B is shown in FIG. 7B.

The output of FIG. 7 (b) is as follows.

_{y = {y 0,0, y 1,0} , y 2,0, y 3,0, y 4,0, y 5,0, y 6,0, y 7,0} = {b 0, b 5 b ₂ , b ₄ , b ₃ , b ₆ , b ₇ , b ₁ } = {x ₂₁ , x ₆ , x ₁₅ , x ₉ , x ₁₂ , x ₃ , x ₀ , x ₁₈ }

In the present invention, a bit mapper composed of an interleaver and a demultiplexer is used. However, the present invention can be implemented in software as in the case of storing the interleaver according to the above-described mapping method in a memory without configuring the mapping unit and the interleaver in hardware. And may also be implemented in some cases by directly mapping the codeword bits to the modulation signal configuration bits described above.

Hereinafter, the performance improvement during data transmission by the interleaving and bit mapping method of the present invention will be described.

8 is a view for explaining performance enhancement according to a data transmission method according to an embodiment of the present invention. 8 shows a bit error rate (BER) when an LDPC codeword having a length of 64800 is used. In addition, 256-QAM modulated signals are used and are the results of experiments on AWGN channels. The dotted line represents the error rate of the codeword of the interleaver designed in a random manner, and the solid line represents the error rate of the codeword when the interleaver and the bit mapping method according to the present invention are used. It can be seen that a performance gain of about 0.3 dB can be obtained at BER = 0.0002 in the present invention.

The interleaving method and the bit mapping method in the transmitter 400 have been described so far. The deinterleaving and bit demapping scheme used in the receiver 450 will be described below. It is apparent to those skilled in the art that the receiver 450 is configured to correspond to the transmitter 400, so that it will be briefly described. That is, the demodulator 457 of the receiver 450 high-order-demodulates the received signal to output a modulation signal configuration bit, and the constellation bit demapper 455 demodulates and demaps the output modulation signal configuration bit And outputs a signal. The demapping method used at this time corresponds to the bit mapping method of the transmitter 400. That is, two highly reliable bits in the modulated signal constituent bits are demapped to a low-order LDPC codeword, and two low-reliability bits are demapped into a high-order LDPC codeword. Also, the bit demapper 455 corresponds to the bit mapper 415 of the transmitter 400, and thus is composed of a multiplexer (not shown).

The bit demapped and output signal is input to the deinterleaver 453. The size of the deinterleaver is the same as the size of the interleaver of the transmitter. The bit-mapped signals are sequentially input to the deinterleaver in a row, and output in a forward direction (output from row 1) in the order of the columns. The deinterleaved LDPC codeword bits are output. The output LDPC codewords are input to a decoder 451, decoded and output. If the interleaving of the transmitter 400 was reverse interleaving, it is clear that the deinterleaving of the receiver is also performed in the reverse direction.

1 is an exemplary diagram of a parity check matrix H1 of an LDPC code,

2 is a graphical representation of a parity check matrix H1 of an LDPC code,

3A is a schematic diagram of a signal constellation of a general QPSK modulation scheme,

3B is a schematic diagram of a signal constellation of a general 16-QAM modulation scheme,

3C is a schematic diagram of a signal constellation of a general 64-QAM modulation scheme,

4 is a configuration diagram of a communication system using an LDPC code according to an embodiment of the present invention.

5 is a configuration diagram of an interleaver and a signal constellation bit mapper according to an embodiment of the present invention,

6 is a diagram illustrating an operation of an interleaver according to an embodiment of the present invention.

FIG. 7 is a diagram illustrating an interleaver and a bit mapping method according to an embodiment of the present invention. FIG.

8 is a diagram for explaining performance enhancement according to a data transmission scheme according to an embodiment of the present invention.

Claims (6)

A method of transmitting data in a communication system using a Low Density Parity Check (LDPC) matrix, Generating an LDPC codeword by encoding the information data bits when information data bits are input; Interleaving the generated LDPC codeword; Mapping the interleaved LDPC codewords to signal constellation bits and outputting a mapping signal; Performing a high-order modulation on the output mapping signal to output a modulation signal, Processing the output modulated signal by radio frequency (RF) processing and transmitting the modulated signal to a receiver through a transmission antenna, Wherein the bits included in the generated LDPC codeword are arranged in order of decreasing order and are divided into groups equal in number to the number of bits included in the modulated signal, At least one bit included in the first group including the lowest order bits among the groups is at least one bit most reliable or least reliable at least one bit among the bits included in the modulation signal Mapped, When at least one bit included in the first group is mapped to at least one bit having the highest reliability, the at least one bit included in the first group is included in a second group including a bit having a low degree next to the bit included in the first group Wherein at least one bit included in the first group is mapped to at least one bit having the least reliability among the bits included in the modulation signal and at least one bit included in the first group is mapped to at least one bit having the least reliability Wherein at least one bit included in the second group among the bits included in the modulation signal is mapped to at least one bit having the highest reliability. The method according to claim 1, Wherein at least one bit included in a third group including a bit of the highest order among the groups includes at least one bit of the least reliable bit among the bits of the modulated signal excluding the mapped bits, Bit, Wherein at least one bit included in a fourth group including bits having a lower order than at least one bit included in the third group is mapped to at least one remaining bit among the bits included in the modulated signal Data transmission method. 2. The method of claim 1, wherein the interleaving comprises: Generating an LDPC matrix so that bits included in the generated LDPC codeword are included in units of columns; And generating the interleaved LDPC codeword by outputting bits included in the LDPC matrix row by row, Wherein the LDPC matrix has a row having the same number as the number of bits included in the modulation signal and a row having the same number as the number obtained by dividing the length of the generated LDPC codeword by the number of columns. . A data transmitting apparatus in a communication system using a low density parity check (LDPC) matrix, An encoder for generating an LDPC codeword by encoding the information data bits when information data bits are input; An interleaver for interleaving the LDPC codeword; A bit mapper for mapping the constellation bits of the interleaved LDPC codewords and outputting a mapping signal, A modulator for higher-order modulating the mapping signal and outputting a modulated signal, And a transmitter for RF (Radio Frequency) processing the modulated signal and transmitting the modulated signal to a receiver through a transmission antenna, Wherein the bits included in the generated LDPC codeword are arranged in order of decreasing order and are divided into groups equal in number to the number of bits included in the modulated signal, At least one bit included in the first group including the lowest order bits among the groups is at least one bit most reliable or least reliable at least one bit among the bits included in the modulation signal Mapped, When at least one bit included in the first group is mapped to at least one bit having the highest reliability, the at least one bit included in the first group is included in a second group including a bit having a low degree next to the bit included in the first group Wherein at least one bit included in the first group is mapped to at least one bit having the least reliability among the bits included in the modulation signal and at least one bit included in the first group is mapped to at least one bit having the least reliability Wherein at least one bit included in the second group among the bits included in the modulation signal is mapped to at least one bit having the highest reliability. 5. The method of claim 4, Wherein at least one bit included in a third group including a bit of the highest order among the groups includes at least one bit of the least reliable bit among the bits of the modulated signal excluding the mapped bits, Bit, Wherein at least one bit included in a fourth group including bits having a lower order than at least one bit included in the third group is mapped to at least one remaining bit among the bits included in the modulated signal Data transmission device. 5. The apparatus of claim 4, wherein the interleaver comprises: Generates an LDPC matrix so that the bits included in the generated LDPC codeword are included in units of columns, outputs the bits included in the LDPC matrix row by row to generate the interleaved LDPC codeword, A row having the same number as the number of bits included in the modulation signal and a row having the same number as the number obtained by dividing the length of the generated LDPC codeword by the number of columns.

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