KR101411741B1 - Semiconductor device - Google Patents

Abstract

The present invention relates to a semiconductor device capable of electrically connecting at least one semiconductor die stacked on a substrate and reducing the size and thickness of the package.
A second wiring pattern formed on a lower surface of the first passivation layer; a second wiring pattern formed on the lower surface of the first wiring pattern; A second passivation layer formed on a lower surface exposed to the outside, and a through via for electrically connecting the first wiring pattern and the second wiring pattern; A first semiconductor die mounted on top of the substrate and electrically connected to the substrate; And a first rewiring layer that is seated on the first semiconductor die and electrically connects the second semiconductor die and a first penetrating electrode formed on a side of the second semiconductor die and the second semiconductor die and the first penetrating electrode, TMV semiconductor devices; And a first encapsulant encapsulating the first semiconductor die and the TMV semiconductor device, wherein the TMV semiconductor device has a first penetrating electrode on the outside of the first semiconductor die and a second penetrating electrode on the first wiring pattern A semiconductor device is disclosed which is electrically connected.

Description

Semiconductor device

The present invention relates to a semiconductor device.

Recently, various technologies have been researched and developed to provide a semiconductor device with a high capacity. As a method for providing a high-capacity semiconductor device, a semiconductor device can be manufactured by stacking a plurality of flip chips on a substrate. Here, in order to stack two or more flip chips, an interposer and an adhesive member for electrically connecting the flip chips to each other are required. However, such an interposer or an adhesive member causes an increase in the size and thickness of the semiconductor device. Therefore, there is a need for a method that can reduce the size and thickness of a semiconductor device while electrically connecting stacked flip chips to each other.

The present invention provides a semiconductor device capable of electrically connecting at least one semiconductor die stacked on a substrate and reducing the size and thickness of the package.

A semiconductor device according to the present invention includes: a first wiring pattern formed on an upper surface; a first passivation layer exposing a part of the first wiring pattern to the outside, a second wiring pattern formed on a lower surface, A second passivation layer formed on a lower surface of the substrate, a through-hole electrically connecting the first wiring pattern and the second wiring pattern; A first semiconductor die mounted on top of the substrate and electrically connected to the substrate; And a first rewiring layer that is seated on the first semiconductor die and electrically connects the second semiconductor die and a first penetrating electrode formed on a side of the second semiconductor die and the second semiconductor die and the first penetrating electrode, TMV semiconductor devices; And a first encapsulant encapsulating the first semiconductor die and the TMV semiconductor device, wherein the TMV semiconductor device has a first penetrating electrode on the outside of the first semiconductor die and a second penetrating electrode on the first wiring pattern And are electrically connected to each other.

Here, at least one bond pad is formed on the upper surface of the second semiconductor device, a protective layer is formed on the upper surface except for the bond pad, and the first re-wiring layer electrically connects the bond pad and the first penetrating electrode You can connect.

The TMV semiconductor device further includes a second encapsulant encapsulating a side of the second semiconductor die, wherein the first penetrating electrode is formed through the upper and lower surfaces of the second encapsulant .

The first rewiring layer may be formed to extend from an upper portion of the second semiconductor die to an upper portion of the second encapsulant.

The TMV semiconductor device further includes a third passivation layer formed on an upper surface of the second semiconductor die and the second encapsulant and exposing a part of the bond pad to the outside; A fourth passivation layer formed on the third passivation layer and covering the first redistribution layer; And a solder ball formed on the first penetrating electrode. The solder ball may be electrically connected to the first wiring pattern of the substrate. The first encapsulant may encapsulate the solder ball.

The semiconductor device may further include a lamination device stacked on top of the TMV semiconductor device, and the lamination device may be electrically connected to the first rewiring layer.

The semiconductor device according to the present invention includes a first wiring pattern formed on an upper surface, a first passivation layer formed on an upper surface of the first wiring pattern, the second wiring pattern formed on the lower surface, A second passivation layer formed on a lower surface of the second wiring pattern to expose a part of the second wiring pattern to the outside and a through via for electrically connecting the first wiring pattern and the second wiring pattern; And a first rewiring layer that is seated on the substrate and that electrically connects the second semiconductor die and the first penetrating electrode formed on the side of the second semiconductor die and the second semiconductor die and the first penetrating electrode, device; And a first semiconductor die mounted on the TMV semiconductor device and electrically connected to the substrate, wherein the TMV semiconductor device has the first penetrating electrode connected directly to the first wiring pattern.

Here, the first penetrating electrode may be formed at a position corresponding to the first wiring pattern.

At least one bond pad is formed on the upper surface of the second semiconductor device, a protective layer is formed on the upper surface except for the bond pad, and the first rewiring layer electrically connects the bond pad and the first penetrating electrode You can connect.

The TMV semiconductor device further includes a second encapsulant encapsulating a side of the second semiconductor die, wherein the first penetrating electrode is formed through the upper and lower surfaces of the second encapsulant . The first rewiring layer may be formed to extend from an upper portion of the second semiconductor die to an upper portion of the second encapsulant.

The TMV semiconductor device further includes a third passivation layer formed on an upper surface of the second semiconductor die and the second encapsulant and exposing a part of the bond pad to the outside; And a fourth passivation layer formed on the third passivation layer and exposing a part of the first redistribution layer to the outside, the first semiconductor die being electrically connected to the first redistribution layer.

In addition, the semiconductor device may further include a lamination device stacked on top of the first semiconductor die, wherein the lamination device may be electrically connected to the first rewiring layer outside the first semiconductor die.

The first encapsulant may further include a first encapsulant that encapsulates the TMV semiconductor device and the first semiconductor die, and the second encapsulant may include a second penetrating electrode. The second penetrating electrode may be formed at a position corresponding to the first rewiring layer. Here, the semiconductor device may further include a lamination device stacked on the first semiconductor die, and the lamination device may be electrically connected to the second penetration electrode.

The semiconductor device according to the present invention includes a first wiring pattern formed on an upper surface, a first passivation layer formed on an upper surface of the first wiring pattern, the second wiring pattern formed on the lower surface, A second passivation layer formed on a lower surface of the second wiring pattern to expose a part of the second wiring pattern to the outside and a through via for electrically connecting the first wiring pattern and the second wiring pattern; A first semiconductor die mounted on top of the substrate and electrically connected to the substrate; And a first rewiring layer that is seated on the first semiconductor die and electrically connects the second semiconductor die and a first penetrating electrode formed on a side of the second semiconductor die and the second semiconductor die and the first penetrating electrode, TMV semiconductor devices; And a first encapsulant encapsulating the first semiconductor die and the TMV semiconductor device, wherein the TMV semiconductor device has a first rewiring layer outside the first semiconductor die, And are electrically connected to each other.

At least one bond pad is formed on the bottom surface of the second semiconductor device, and a protective layer is formed on the bottom surface excluding the bond pad. The first rewiring layer electrically connects the bond pad and the first penetrating electrode You can connect.

The TMV semiconductor device further includes a second encapsulant encapsulating a side of the second semiconductor die, wherein the first penetrating electrode is formed through the upper and lower surfaces of the second encapsulant . The first rewiring layer may extend from a lower portion of the second semiconductor die to a lower portion of the second encapsulant.

The TMV semiconductor device further includes a third passivation layer formed on a lower surface of the second semiconductor die and the second encapsulant and exposing a part of the bond pad to the outside; A fourth passivation layer formed below the third passivation layer and covering the first redistribution layer; And a solder ball formed on the first rewiring layer. The solder ball may be electrically connected to the first wiring pattern of the substrate. The first encapsulant may encapsulate the solder ball.

In addition, the semiconductor device may further include a lamination device stacked on top of the TMV semiconductor device, and the lamination device may be electrically connected to the first penetration electrode.

The semiconductor device further includes a third semiconductor die formed between the first semiconductor die and the TMV semiconductor device and having a bond pad formed therein, and the bond pad of the third semiconductor die may be electrically connected to the first rewiring layer. The TMV semiconductor device may further include a lamination device stacked on top of the TMV semiconductor device, and the lamination device may be electrically connected to the first penetration electrode.

The semiconductor device according to the present invention includes a second semiconductor die, a TMV semiconductor device including a first through-hole electrode formed on a side surface of the second semiconductor die, and a first re-wiring layer electrically connecting the second semiconductor die and the first through- device; And a first semiconductor die mounted on top of the TMV semiconductor device, wherein the first semiconductor die is electrically connected to the first rewiring layer.

Here, at least one bond pad is formed on the upper surface of the second semiconductor device, a protective layer is formed on the upper surface except for the bond pad, and the first re-wiring layer electrically connects the bond pad and the first penetrating electrode You can connect.

The TMV semiconductor device further includes a second encapsulant encapsulating a side of the second semiconductor die, wherein the first penetrating electrode is formed through the upper and lower surfaces of the second encapsulant . The first rewiring layer may be formed to extend from an upper portion of the second semiconductor die to an upper portion of the second encapsulant.

The TMV semiconductor device further includes a third passivation layer formed on an upper surface of the second semiconductor die and the second encapsulant and exposing a part of the bond pad to the outside; A fourth passivation layer formed on the third passivation layer and exposing a part of the first redistribution layer to the outside; A fifth passivation layer formed on a lower surface of the second semiconductor die and the second encapsulant and exposing a part of the first penetrating electrode to the outside; A second rewiring layer formed below the fifth passivation layer and electrically connected to the first penetrating electrode; A sixth passivation layer formed below the fifth passivation layer and exposing a part of the second re-wiring layer to the outside; And a solder ball formed on the second rewiring layer.

Here, the second rewiring layer may be formed to extend from a lower portion of the second semiconductor die to a lower portion of the second encapsulant.

In addition, the semiconductor device may further include a lamination device stacked on the first semiconductor die, and the lamination device may be electrically connected to the first rewiring layer.

A semiconductor device according to an embodiment of the present invention includes a first semiconductor die, a second semiconductor die, a first penetrating electrode, and a first rewiring layer electrically connecting the second semiconductor die and the first penetrating electrode, A semiconductor device is provided to electrically connect the first semiconductor die and the second semiconductor die through the first penetrating electrode so that a separate interposer is not required to connect the first semiconductor die and the second semiconductor die. Therefore, the semiconductor device according to the embodiment of the present invention can reduce the size and thickness of the package.

The semiconductor device according to an embodiment of the present invention further includes a TMV semiconductor device including a second semiconductor die, a first penetrating electrode, and a first rewiring layer electrically connecting the second semiconductor die and the first penetrating electrode By electrically connecting the first semiconductor die and the substrate through the first penetrating electrode, a separate interposer is not required to connect the substrate to the first semiconductor die. Therefore, the semiconductor device according to another embodiment of the present invention can reduce the size and thickness of the package.

A semiconductor device according to another embodiment of the present invention further includes a TMV semiconductor device including a second semiconductor die on a first semiconductor die and a first rewiring layer formed on a lower portion of the second semiconductor die, By electrically connecting the one semiconductor die and the second semiconductor die through the first redistribution layer, no separate interposer is required to connect the first semiconductor die and the second semiconductor die. Therefore, the semiconductor device according to another embodiment of the present invention can reduce the size and thickness of the package.

1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.
2 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention.
3 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention.
4 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention.
5 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention.
6 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention.
7 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention.
8 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention.
9 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention.
10 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention.
11 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention.
12 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention.
13 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the present invention.

1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor device 100 according to an embodiment of the present invention includes a substrate 110, a first semiconductor die 120, a TMV semiconductor device 130, and a first encapsulant 140 .

The substrate 110 includes an insulating layer 111, a first wiring pattern 112, a second wiring pattern 113, a first passivation layer 114, a second passivation layer 115, a through via 116, And a first solder ball (117). The substrate 110 may be a printed circuit board (PCB) formed on both sides.

The insulating layer 111 is composed of a flat upper surface 111a and a lower surface 111b. The insulating layer 111 isolates a first wiring pattern 112 formed on the upper surface 111a and a second wiring pattern 113 formed on the lower surface 111b. Here, the insulating layer 111 may be a single layer.

The first wiring pattern 112 is formed on the upper surface 111a of the insulating layer 111. [ The first wiring patterns 112 may be electrically connected to the second wiring patterns 113 through the through vias 116. The first wiring pattern 112 may be electrically connected to the first semiconductor die 120 and the TMV semiconductor device 130 through the second solder ball 123 and the third solder ball 137. The first wiring pattern 112 may be made of copper (Cu), titanium (Ti), nickel (Ni), palladium (Pd) or the like, but the metal material is not limited thereto.

The second wiring patterns 113 are formed on the lower surface 111b of the insulating layer 111. The second wiring patterns 113 are electrically connected to the first wiring patterns 112 through the through vias 116, Can be connected. Also, a first solder ball 117 is welded to the second wiring pattern 113. The second wiring patterns 113 may be formed of the same material as the first wiring patterns 112.

The first passivation layer 114 is formed on the upper surface 111a of the insulating layer 111 to have a predetermined thickness on the outer periphery of the first wiring pattern 112, . That is, the first passivation layer 114 is formed on the upper surface 111a of the insulating layer 111, and exposes a part of the first wiring pattern 112 to the outside. The first passivation layer 114 may be formed of any one selected from conventional polyimide, epoxy, benzocyclobutene (BCB), polybenzoxazole (PBO), oxide film, nitride film, , But the material is not limited thereto.

The second passivation layer 115 is formed on the lower surface 111b of the insulating layer 111 to have a predetermined thickness on the outer periphery of the second wiring pattern 113, . That is, the second passivation layer 115 is formed on the lower surface 111b of the insulating layer 111 to expose a part of the second wiring pattern 113 to the outside. The second passivation layer 115 may be formed of the same material as the first passivation layer 114.

The through vias 116 are formed to penetrate from the upper surface 111a of the insulating layer 111 to the lower surface 111b. The through vias 116 may electrically connect the first wiring patterns 112 and the second wiring patterns 113. The through vias 116 may be formed of any one or a combination of conductive materials such as gold (Au), silver (Ag), and copper (Cu).

The first solder ball 117 is welded to the second wiring pattern 113. The first solder ball 117 may be electrically connected to the first semiconductor die 120 through the through via 116, the first wiring pattern 112, and the second solder ball 123. The first solder ball 117 may be electrically connected to the TMV semiconductor device 130 through the through via 116, the first wiring pattern 112, and the third solder ball 137. The first solder ball 117 may be formed of any one selected from tin / lead, lead-free tin, and the like, and the material thereof is not limited thereto.

The first semiconductor die 120 is seated on top of the substrate 110. The first semiconductor die 120 is generally formed of a silicon material, and a plurality of semiconductor elements are formed in the first semiconductor die 120. The first semiconductor die 120 has a substantially flat upper surface 120a and a lower surface 120b. At least one bond pad 121 is formed on the lower surface 120b of the first semiconductor die 120 and a protective layer 122 is formed on the outer periphery of the bond pad 121. [ The protective layer 122 exposes a part of the bond pad 121 to the outside and the second solder ball 123 is welded to the exposed part of the bond pad 121. The first semiconductor die 120 is electrically connected to the first wiring pattern 112 of the substrate 110 through the second solder ball 123. That is, the second solder ball 123 is welded to the first wiring pattern 112 of the substrate 110, so that the substrate 110 and the first semiconductor die 120 are electrically connected to each other.

The TMV semiconductor device 130 is mounted on the first semiconductor die 120 and is electrically connected to the substrate 110. The TMV semiconductor device 130 includes a second semiconductor die 131, a second encapsulant 132, a first penetrating electrode 133, a third passivation layer 134, a first rewiring layer 135, 4 passivation layer 136 and a third solder ball 137 as shown in FIG.

Like the first semiconductor die 120, the second semiconductor die 131 is formed of a silicon material, and some semiconductor elements are formed in the second semiconductor die 131. The second semiconductor die 131 has a substantially flat upper surface 131a and a lower surface 131b. At least one bond pad 131c is formed on the upper surface 131a of the second semiconductor die 131 and a protective layer 131d is formed on the outer periphery of the bond pad 131c. Here, the lower surface 131b of the second semiconductor die 131 and the upper surface 120a of the first semiconductor die 120 are in contact with each other. That is, the surfaces of the second semiconductor die 131 and the first semiconductor die 120 on which the bond pads are not formed come into contact with each other. Also, the size of the second semiconductor die 131 may be larger than that of the first semiconductor die 120.

The second encapsulant 132 encapsulates the side of the second semiconductor die 131. That is, the second encapsulant 132 is formed on the side surface of the second semiconductor die 131 to protect the side surface of the second semiconductor die 131 from the external environment. The second encapsulant 132 uses an electrical insulating material and is generally formed of an epoxy-based resin. The second encapsulant 132 may be formed on a side surface of the second semiconductor die 131 to electrically connect a first rewiring layer 135 electrically connected to the bond pad 131c to the second semiconductor die 131). The structure of the TMV semiconductor device 130 is referred to as wafer-level fan-out (WLFO).

The first penetrating electrode 133 is formed on the second encapsulant 132 and is formed to penetrate the lower surface of the second encapsulant 132 from the upper surface. The first penetrating electrode 133 is electrically connected to the second semiconductor die 131 through the first rewiring layer 135. The first penetrating electrode 133 is electrically connected to the substrate 110 through a third solder ball 137. Here, the substrate 110 is electrically connected to the first semiconductor die 120. As a result, the first semiconductor die 120 and the second semiconductor die 131 are electrically connected through the first penetrating electrode 133. The first penetrating electrode 133 may be formed of a conductive material, for example, gold, silver or copper, or a combination thereof.

The third passivation layer 134 is formed to have the same thickness on the upper surface 131a of the second semiconductor die 131 and the upper surface of the second encapsulant 132. [ The third passivation layer 134 exposes a part of the bond pad 131c of the second semiconductor die 131 to the outside and a part of the first penetrating electrode 133 to the outside. The third passivation layer 134 may be formed of the same material as the first passivation layer 114 and the second passivation layer 115.

The first rewiring layer 135 is formed on the third passivation layer 134 and includes a bond pad 131c and a first penetrating electrode 133 exposed to the outside by the third passivation layer 134, Respectively. That is, the first rewiring layer 135 is formed to extend from the upper portion of the second semiconductor die 131 to the upper surface of the second encapsulant 132, and the bonding pad 131c and the first through- And serves to electrically connect the electrode 133. Of course, the first rewiring layer 135 may be formed only on the second semiconductor die 131 or only on the second encapsulant 132. The first rewiring layer 135 may be formed of gold (Au), silver (Ag), nickel (Ni), or the like, but is not limited thereto.

The fourth passivation layer 136 is formed to have the same thickness on the third passivation layer 134 so as to cover the first redistribution layer 135. The fourth passivation layer 136 protects the first redistribution layer 135 from the external environment. The fourth passivation layer 136 may be formed of the same material as the third passivation layer 134.

The third solder ball 137 is welded to the lower portion of the first penetrating electrode 133. The third solder ball 117 may be electrically connected to the second semiconductor die 131 through the first penetrating electrode 133 and the first rewiring layer 135. The third solder ball 137 is electrically connected to the first wiring pattern 112 of the substrate 110 to electrically connect the TMV semiconductor device 130 to the substrate 110 . Here, the first wiring pattern 112 is electrically connected to the first semiconductor die 120. Accordingly, the TMV semiconductor device 130 is electrically connected to the first semiconductor die 120 through the third solder ball 137.

The first encapsulant 140 encapsulates the first semiconductor die 120 and the TMV semiconductor device 130 on top of the substrate 110 to protect them from the external environment. The first encapsulant 140 may encapsulate the side surfaces and the bottom surface of the TMV semiconductor device 130 to expose the top surface of the TMV semiconductor device 130 to the outside. That is, the upper surface of the first encapsulant 140 and the fourth passivation layer 136 of the TMV semiconductor device 130 may be flush with each other. The first encapsulant 140 may be formed of an epoxy-based resin using an electrical insulating material.

As described above, the semiconductor device 100 according to an embodiment of the present invention includes a second semiconductor die 131, a first penetrating electrode 133, and a second semiconductor die 131 And a first rewiring layer 135 that electrically connects the first semiconductor die 120 and the first penetrating electrode 133 to the first semiconductor die 120 and the second semiconductor die 131, A separate interposer is not required to connect the first semiconductor die 120 and the second semiconductor die 131 by electrically connecting through the first penetrating electrode 133. Accordingly, the semiconductor device 100 according to the embodiment of the present invention can reduce the size and the thickness of the package.

In addition, a plurality of semiconductor devices may be stacked on the semiconductor device 100 according to an embodiment of the present invention. 2 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention. 3 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention.

2, a first stacked semiconductor device 10 is stacked on top of a semiconductor die 100 according to one embodiment of the present invention to implement a semiconductor device 200 according to another embodiment of the present invention . Here, the first laminated semiconductor device 10 may be soldered to the first rewiring layer 135 of the TMV semiconductor device 130 and electrically connected thereto.

3, a first stacked semiconductor device 10 and a second stacked semiconductor device 20 are stacked on top of a semiconductor die 100 according to an embodiment of the present invention, The semiconductor device 300 according to another embodiment can be implemented. Here, the package of the first laminated semiconductor device 10 and the second laminated semiconductor device 20 is not limited to that shown in the drawings, and any semiconductor device that can be stacked on the semiconductor device 100 may be any package It is possible. Therefore, the description of the first laminated semiconductor device 10 and the second laminated semiconductor device 20 will be omitted.

Next, a semiconductor device according to another embodiment of the present invention will be described.

4 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention.

The semiconductor device 400 shown in Fig. 4 is substantially similar to the semiconductor device 100 shown in Fig. Therefore, the difference will be mainly described here.

4, a semiconductor device 400 according to another embodiment of the present invention includes a substrate 110, a first semiconductor die 420, and a TMV semiconductor device 430. In other words, the semiconductor device 400 according to another embodiment of the present invention differs from the semiconductor device 100 shown in FIG. 1 in the stacking positions of the first semiconductor die 420 and the TMV semiconductor device 430, It is not encapsulated by the first encapsulant 140.

The TMV semiconductor device 430 is mounted on the substrate 110 and is electrically connected to the substrate 110. The TMV semiconductor device 430 includes a second semiconductor die 431, a second encapsulant 432, a first penetrating electrode 433, a third passivation layer 434, a first rewiring layer 435, 4 passivation layer 436. Here, the TMV semiconductor device 430 is a state in which the second solder ball 137 is removed from the TMV semiconductor device 130 shown in FIG. That is, since the TMV semiconductor device 430 is seated on the substrate 110 and the first penetrating electrode 433 is directly connected to the second wiring pattern 112, the third solder ball 137 ) Is not required.

The first penetrating electrode 433 is formed on the second encapsulant 432 and penetrates the lower surface of the second encapsulant 432 through the lower surface. The first penetrating electrode 433 is formed on the second wiring pattern 112 formed on the substrate 110 and is electrically connected to the substrate 110. The first penetrating electrode 433 is electrically connected to the second semiconductor die 431 through a first rewiring layer 435 and the first rewiring layer 435 is electrically connected to the first semiconductor die 420. [ The second solder ball 423 is welded. As a result, the first semiconductor die 420 and the substrate 110 are electrically connected through the first penetrating electrode 433. The first penetrating electrode 433 may be formed of a conductive material, for example, gold, silver or copper, or a combination thereof.

The fourth passivation layer 436 is formed to have the same thickness on the third passivation layer 436 to cover the first redistribution layer 435. The fourth passivation layer 436 protects the first rewiring layer 435 and the third passivation layer 434 from the external environment. In addition, the fourth passivation layer 436 exposes a part of the first redistribution layer 435 to the outside. The fourth passivation layer 436 may be formed of the same material as the third passivation layer 434.

The first semiconductor die 420 is seated on top of the TMV semiconductor device 430. The first semiconductor die 420 has a substantially flat upper surface 420a and a lower surface 420b. At least one bond pad 421 is formed on the lower surface 420b of the first semiconductor die 420 and a protective layer 422 is formed on the outer periphery of the bond pad 421. [ The protective layer 422 exposes a part of the bond pad 421 to the outside and the second solder ball 423 is welded to the exposed part of the bond pad 421. The first semiconductor die 420 is electrically connected to the first rewiring layer 435 of the TMV semiconductor device 430 through the second solder ball 423. That is, the second solder ball 423 is welded to the first rewiring layer 435 of the TMV semiconductor device 430 to electrically connect the second semiconductor die 431 and the first semiconductor die 420 . In addition, since the TMV semiconductor device 430 is electrically connected to the substrate 110 through the first penetrating electrode 433, the first semiconductor die 420 is electrically connected to the substrate 110 And is electrically connected.

As described above, the semiconductor device 400 according to another embodiment of the present invention includes the second semiconductor die 431, the first penetrating electrode 433, the second semiconductor die 431 and the first penetrating electrode 433, And a TMV semiconductor device 430 including a first rewiring layer 435 electrically connecting the first semiconductor die 420 and the substrate 110 via the first penetrating electrode 433 A separate interposer is not required to connect the first semiconductor die 420 and the substrate 110. [ Therefore, the semiconductor device 400 according to another embodiment of the present invention can reduce the size and thickness of the package.

In addition, another semiconductor device may be stacked on the semiconductor device 400 according to another embodiment of the present invention. 5 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention.

5, a second stacked semiconductor device 20 is stacked on top of a semiconductor device 400 according to another embodiment of the present invention to form a semiconductor device 500 according to another embodiment of the present invention. Can be implemented. Here, the second laminated semiconductor device 20 may be soldered to the first rewiring layer 435 of the TMV semiconductor device 430 to be electrically connected thereto.

Next, a semiconductor device according to another embodiment of the present invention will be described.

6 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention.

The semiconductor device 600 shown in Fig. 6 is substantially similar to the semiconductor device 400 shown in Fig. Therefore, the difference will be mainly described below.

6, a semiconductor device 600 according to another embodiment of the present invention includes a substrate 110, a first semiconductor die 420, a TMV semiconductor device 430 and a first encapsulant 640, . That is, the semiconductor device 600 according to another embodiment of the present invention further includes a first encapsulant 640 as compared with the semiconductor device 400 shown in FIG.

The first encapsulant 640 encapsulates the first semiconductor die 420 and the TMV semiconductor device 430 on top of the substrate 110 to protect them from the external environment. The first encapsulant 640 encapsulates the sides of the TMV semiconductor device 430 and the first semiconductor die 420 to form the upper surface 420a of the first semiconductor die 420 to the outside Can be exposed. That is, the upper surface of the first encapsulant 640 and the upper surface 420a of the first semiconductor die 420 may be flush with each other. In addition, a second penetrating electrode 641 may be formed in the first encapsulant 640. The second penetrating electrode 641 is formed on the first encapsulant 640 formed on the side surface of the first semiconductor die 420. The second penetrating electrode 641 may be formed on the first rewiring layer 435 of the TMV semiconductor device 430 and electrically connected to the second semiconductor die 431. The first encapsulant 640 may be formed of an epoxy-based resin using an electrically insulating material.

In addition, other semiconductor devices may be stacked on the semiconductor device 600 according to another embodiment of the present invention. 7 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention.

7, a second stacked semiconductor device 20 is stacked on top of a semiconductor device 600 according to another embodiment of the present invention to form a semiconductor device 700 according to another embodiment of the present invention. Can be implemented. Here, the second laminated semiconductor device 20 may be electrically connected to a second penetrating electrode 641 formed on the first encapsulant 640 by welding a solder ball.

Next, a semiconductor device according to another embodiment of the present invention will be described.

8 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention.

The semiconductor device 800 shown in Fig. 8 is almost similar to the semiconductor device shown in Fig. Therefore, the difference will be mainly described below.

8, a semiconductor device 800 according to another embodiment of the present invention includes a substrate 110, a first semiconductor die 120, a TMV semiconductor device 830, and a first encapsulant 140, . In other words, the semiconductor device 800 according to another embodiment of the present invention is formed by inverting the TMV semiconductor device 130 (rotated by 180 degrees) in the semiconductor device 100 shown in FIG.

The TMV semiconductor device 830 is seated on the first semiconductor die 120 and is electrically connected to the substrate 110. The TMV semiconductor device 830 includes a second semiconductor die 831, a second encapsulant 832, a first penetrating electrode 833, a third passivation layer 834, a first rewiring layer 835, 4 passivation layer 836 and a third solder ball 837.

The second semiconductor die 831 has a substantially flat upper surface 831a and a lower surface 831b. At least one bond pad 831c is formed on the lower surface 831b of the second semiconductor die 831 and a passivation layer 831d is formed on the outer periphery of the bond pad 831c. The upper surface 831a of the second semiconductor die 831 is exposed to the outside and the lower surface 831b on which the bond pad 831c is formed faces the upper surface 120a of the first semiconductor die 120, I will see.

The second encapsulant 832 encapsulates the side of the second semiconductor die 831. That is, the second encapsulant 832 is formed on the side surface of the second semiconductor die 831 to protect the side surface of the second semiconductor die 831 from the external environment.

The first penetrating electrode 833 is formed on the second encapsulant 832 and penetrates the lower surface of the second encapsulant 832 through the lower surface. The first penetrating electrode 833 is electrically connected to the second semiconductor die 831 through the first rewiring layer 835.

The third passivation layer 834 is formed to have the same thickness at the lower portion of the second semiconductor die 831 and the lower portion of the second encapsulant 832. The third passivation layer 834 exposes a part of the bond pad 831c of the second semiconductor die 831 to the outside and a part of the first penetrating electrode 833 to the outside.

The first rewiring layer 835 is formed under the third passivation layer 834 and includes a bond pad 831c and a first penetrating electrode 833 exposed to the outside by the third passivation layer 834, Respectively. That is, the first rewiring layer 835 extends from the lower portion of the second semiconductor die 831 to the lower portion of the second encapsulant 832, And serves to electrically connect the electrodes 833.

The fourth passivation layer 836 is formed to have the same thickness below the third passivation layer 834 so as to cover the first rewiring layer 835. The fourth passivation layer 836 protects the first rewiring layer 835 and the third passivation layer 834 from the external environment and exposes a part of the first rewiring layer 835 to the outside.

The third solder ball 837 is welded to the first rewiring layer 835 exposed to the outside by the fourth passivation layer 836. Thus, the third solder ball 837 is electrically connected to the second semiconductor die 831 through the first rewiring layer 835. The third solder ball 837 is electrically connected to the first wiring pattern 112 of the substrate 110 to electrically connect the TMV semiconductor device 830 to the substrate 110 . Here, the first wiring pattern 112 is electrically connected to the first semiconductor die 120. Accordingly, the TMV semiconductor device 830 is electrically connected to the first semiconductor die 120 through the third solder ball 837.

The semiconductor device 800 according to another embodiment of the present invention includes a second semiconductor die 831 on the first semiconductor die 120 and a first semiconductor die 831 formed on the bottom of the second semiconductor die 831. [ And a TMV semiconductor device 830 including a redistribution layer 835 and electrically connecting the first semiconductor die 120 and the second semiconductor die 831 through the first rewiring layer 835, A separate interposer is not required to connect the first semiconductor die 120 and the second semiconductor die 831. [ Accordingly, the semiconductor device 800 according to another embodiment of the present invention can reduce the size and thickness of the package.

In addition, another semiconductor device may be stacked on the semiconductor device 800 according to another embodiment of the present invention. 9 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention.

9, a second stacked semiconductor device 20 is stacked on top of a semiconductor device 800 according to another embodiment of the present invention to form a semiconductor device 900 according to another embodiment of the present invention. Can be implemented. Here, the second laminated semiconductor device 20 may be soldered to the first penetrating electrode 833 of the TMV semiconductor device 830 to be electrically connected thereto.

Next, a semiconductor device according to another embodiment of the present invention will be described.

10 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention.

The semiconductor device 1000 shown in Fig. 10 is almost similar to the semiconductor device 800 shown in Fig. Therefore, the difference will be mainly described below.

10, a semiconductor device 1000 according to another embodiment of the present invention includes a substrate 110, a first semiconductor die 120, a TMV semiconductor device 830, a first encapsulant 140, And a third semiconductor die 1120.

The third semiconductor die 1120 is located between the first semiconductor die 120 and the TMV semiconductor device 830. The third semiconductor die 1120 is seated on the upper surface 120a of the first semiconductor die 120 and has a substantially flat upper surface 1120a and a lower surface 1120b. The upper surface 1120a of the third semiconductor die 1120 faces the lower surface 830b of the TMV semiconductor device 830 and the lower surface 1120b of the third semiconductor die 1120 faces the upper surface 120a of the first semiconductor die 120, . At this time, the third semiconductor die 1120 may be attached to the first semiconductor die 120 by an adhesive member (not shown). At least one bond pad 1121 is formed on the upper surface 1120a of the third semiconductor die 1120 and a protective layer 1122 is formed on the outer periphery of the bond pad 1121. [ The protective layer 1122 exposes a portion of the bond pad 1121 to the outside and a fourth solder ball 1123 is welded to the exposed portion of the bond pad 1121. The third semiconductor die 1120 is electrically connected to the first redistribution layer 835 of the TMV semiconductor device 830 through the fourth solder ball 1123. Thus, the third semiconductor die 1120 is electrically connected to the second semiconductor die 831 of the TMV semiconductor device 830.

As described above, the semiconductor device 1000 according to another embodiment of the present invention includes the TMV semiconductor device 830 including the first rewiring layer 835 formed at the lower portion thereof, even if a plurality of semiconductor dies are stacked on the substrate 110 ), So that each semiconductor die can be electrically connected without a separate interposer.

In addition, another semiconductor device may be stacked on the semiconductor device 1000 according to another embodiment of the present invention. 11 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention.

11, a second stacked semiconductor device 20 is stacked on top of a semiconductor device 1000 according to another embodiment of the present invention to form a semiconductor device 1100 according to another embodiment of the present invention. Can be implemented. Here, the second laminated semiconductor device 20 may be soldered to the first penetrating electrode 833 of the TMV semiconductor device 830 to be electrically connected thereto.

Next, a semiconductor device according to another embodiment of the present invention will be described.

12 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention.

12, a semiconductor device 1200 according to another embodiment of the present invention includes a first semiconductor die 120 and a TMV semiconductor device 1130.

The TMV semiconductor device 1130 includes a second semiconductor die 1131, a second encapsulant 1132, a first penetrating electrode 1133, a third passivation layer 1134, a first rewiring layer 1135, 4 passivation layer 1136, a fifth passivation layer 1137, a second redistribution layer 1138, a sixth passivation layer 1139 and a third solder ball 1140. [ That is, the TMV semiconductor device 1130 further includes a first rewiring layer 1135 formed on the upper surface 1130a, and a second rewiring layer 1138 formed on the lower surface 1130b.

The second semiconductor die 1131 is generally formed of a silicon material, and a plurality of semiconductor elements are formed in the second semiconductor die 1131. The second semiconductor die 1131 has a substantially flat upper surface 1131a and a lower surface 1131b. At least one bond pad 1131c is formed on the upper surface 1131a of the second semiconductor die 1131 and a protective layer 1131d is formed on the outer periphery of the bond pad 1131c.

The second encapsulant 1132 encapsulates the side of the second semiconductor die 1131. That is, the second encapsulant 1132 is formed on the side surface of the second semiconductor die 1131 and protects the side surface of the second semiconductor die 1131 from the external environment. The second encapsulant 1132 uses an electrical insulating material and is generally formed of an epoxy-based resin. The second encapsulant 1132 may be formed on a side surface of the second semiconductor die 1131 to electrically connect a first rewiring layer 1135 electrically connected to the bond pad 1131c to the second semiconductor die 1131, respectively. In addition, the second encapsulant 1132 may be formed on a side surface of the second semiconductor die 1131 to extend the second rewiring layer 1138 to the outside of the second semiconductor die 1131. The structure of the TMV semiconductor device 1130 is referred to as wafer-level fan-out (WLFO).

The first penetrating electrode 1133 is formed in the second encapsulant 1132 and is formed to penetrate the lower portion of the second encapsulant 1132 through the lower portion. The first penetrating electrode 1133 is electrically connected to the second semiconductor die 1131 through the first rewiring layer 1135. The first penetrating electrode 1133 is electrically connected to the third solder ball 1140 through the second rewiring layer 1138. The first penetrating electrode 1133 may be formed of any one or a combination of conductive materials such as gold, silver, and copper.

The third passivation layer 1134 is formed to have the same thickness on the upper portion of the second semiconductor die 1131 and on the second encapsulant 1132. The third passivation layer 1134 exposes a part of the bond pad 1131c of the second semiconductor die 1131 to the outside and exposes a part of the first penetrating electrode 1133 to the outside.

The first rewiring layer 1135 is formed on the third passivation layer 1134 and includes a bond pad 1131c and a first penetrating electrode 1133 exposed to the outside by the third passivation layer 1134, Respectively. That is, the first rewiring layer 1135 is formed to extend from the upper portion of the second semiconductor die 1131 to the upper portion of the second encapsulant 1132, and the bond pad 1131c, And serves to electrically connect the electrodes 1133.

The fourth passivation layer 1136 is formed to have the same thickness on the third passivation layer 1134 so as to cover the first redistribution layer 1135. In addition, the fourth passivation layer 1136 exposes a part of the first redistribution layer 1135 to the outside.

The fifth passivation layer 1137 is formed to have the same thickness at the lower portion of the second semiconductor die 1131 and the lower portion of the second encapsulant 1132. The fifth passivation layer 1137 exposes a part of the first penetrating electrode 1133 to the outside. The fifth passivation layer 1137 may be formed of any one selected from conventional polyimide, epoxy, BCB (Benzo Cyclo Butene), PBO (Poly Benz Oxazole), oxide film, nitride film, , But the material is not limited thereto.

The second rewiring layer 1138 is formed under the fifth passivation layer 1137 and is electrically connected to the first penetrating electrode 1133 exposed to the outside by the fifth passivation layer 1137. That is, the second rewiring layer 1138 is formed to extend from the lower portion of the second encapsulation 1132 to the lower portion of the second semiconductor die 1131, and the first penetrating electrode 1133 is formed in the third And electrically connects the solder ball 1140 to the solder ball 1140. Of course, the second redistribution layer 1138 may be formed only on the lower portion of the second semiconductor die 1131 or only on the lower portion of the second encapsulant 1132.

The sixth passivation layer 1139 is formed to have the same thickness below the fifth passivation layer 1137 so as to cover the second redistribution layer 1138. The sixth passivation layer 1139 exposes a part of the second redistribution layer 1138 to the outside. The sixth passivation layer 1139 may be made of the same material as the fifth passivation layer 1137.

The third solder ball 1140 is welded to the second redistribution layer 1138. The third solder ball 1140 may be electrically connected to the second semiconductor die 1131 through the second rewiring layer 1138, the first penetrating electrode 1133, and the first rewiring layer 1135. The third solder ball 1140 may be formed of any one selected from tin / lead, lead-free tin, and the like, and the material thereof is not limited thereto.

The first semiconductor die 120 is seated on top of the TMV semiconductor device 1130. Here, the second solder balls 123 of the first semiconductor die 120 are welded to the first rewiring layer 1135. Thus, the first semiconductor die 120 is electrically connected to the second semiconductor die 1131. Since the first semiconductor die 120 is the same as that described above, a detailed description thereof will be omitted.

In addition, another semiconductor device may be stacked on the semiconductor device 1200 according to another embodiment of the present invention. 13 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention.

13, a second stacked semiconductor device 20 is stacked on top of a semiconductor device 1200 according to another embodiment of the present invention to form a semiconductor device 1300 according to another embodiment of the present invention. Can be implemented. Here, the second laminated semiconductor device 20 may be soldered to the first rewiring layer 1135 of the TMV semiconductor device 1130 to be electrically connected thereto.

It is to be understood that the present invention is not limited to the above-described embodiment, but may be modified in various other forms without departing from the spirit of the present invention as claimed in the following claims. It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

100: semiconductor device 110: substrate
111: insulating layer 112: first wiring pattern
113: second wiring pattern 114: first passivation layer
115: second passivation layer 116: through vias
117: first solder ball 120: first semiconductor die
121: Bond pad 122: Protective layer
123: second solder ball 130: TMV semiconductor device
131: second semiconductor die 132: second encapsulant
133: first penetrating electrode 134: third passivation layer
135: first rewiring layer 136: fourth passivation layer
137: third solder ball 140: first encapsulant

Claims (35)

A second wiring pattern formed on a lower surface of the first passivation layer; and a second wiring pattern formed on the lower surface of the first passivation layer to expose a part of the second wiring pattern to the outside A second passivation layer formed on the lower surface of the substrate, and a through via for electrically connecting the first wiring pattern and the second wiring pattern;
A first semiconductor die mounted on top of the substrate and electrically connected to the substrate;
And a first rewiring layer that is seated on the first semiconductor die and electrically connects the second semiconductor die and a first penetrating electrode formed on a side of the second semiconductor die and the second semiconductor die and the first penetrating electrode, TMV semiconductor devices; And
And a first encapsulant encapsulating the first semiconductor die and the TMV semiconductor device,
Wherein the TMV semiconductor device has a first through-hole electrode electrically connected to the first wiring pattern at an outer side of the first semiconductor die,
The TMV semiconductor device further includes a solder ball formed on the first penetrating electrode,
Wherein the solder ball is electrically connected to the first wiring pattern of the substrate. The method according to claim 1,
At least one bond pad is formed on the upper surface of the second semiconductor die, a protective layer is formed on the upper surface except for the bond pad,
And the first re-wiring layer electrically connects the bond pad and the first penetrating electrode. 3. The method of claim 2,
Wherein the TMV semiconductor device further comprises a second encapsulant encapsulating a side of the second semiconductor die,
Wherein the first penetrating electrode is formed to penetrate the upper surface and the lower surface of the second encapsulant. The method of claim 3,
Wherein the first rewiring layer is formed to extend from an upper portion of the second semiconductor die to an upper portion of the second encapsulant. The method of claim 3,
The TMV semiconductor device
A third passivation layer formed on an upper surface of the second semiconductor die and the second encapsulant and exposing a part of the bond pad to the outside; And
And a fourth passivation layer formed on the third passivation layer and covering the first redistribution layer. delete 6. The method of claim 5,
Wherein the first encapsulant encapsulates the solder ball. The method according to claim 1,
Further comprising a lamination device stacked on top of the TMV semiconductor device,
Wherein the lamination device is electrically connected to the first redistribution layer. A second wiring pattern formed on a lower surface of the first passivation layer; and a second wiring pattern formed on the lower surface of the first passivation layer to expose a part of the second wiring pattern to the outside A second passivation layer formed on the lower surface of the substrate, and a through via for electrically connecting the first wiring pattern and the second wiring pattern;
And a first rewiring layer that is seated on the substrate and that electrically connects the second semiconductor die and the first penetrating electrode formed on the side of the second semiconductor die and the second semiconductor die and the first penetrating electrode, device; And
A first semiconductor die mounted on top of the TMV semiconductor device and electrically connected to the substrate,
Wherein the TMV semiconductor device is characterized in that the first penetrating electrode is directly connected to the first wiring pattern. 10. The method of claim 9,
And the first penetrating electrode is formed at a position corresponding to the first wiring pattern. 10. The method of claim 9,
At least one bond pad is formed on the upper surface of the second semiconductor die, a protective layer is formed on the upper surface except for the bond pad,
And the first re-wiring layer electrically connects the bond pad and the first penetrating electrode. 12. The method of claim 11,
Wherein the TMV semiconductor device further comprises a second encapsulant encapsulating a side of the second semiconductor die,
Wherein the first penetrating electrode is formed to penetrate the upper surface and the lower surface of the second encapsulant. 13. The method of claim 12,
Wherein the first rewiring layer is formed to extend from an upper portion of the second semiconductor die to an upper portion of the second encapsulant. 13. The method of claim 12,
The TMV semiconductor device
A third passivation layer formed on an upper surface of the second semiconductor die and the second encapsulant and exposing a part of the bond pad to the outside; And
And a fourth passivation layer formed on the third passivation layer and exposing a part of the first redistribution layer to the outside,
Wherein the first semiconductor die is electrically connected to the first redistribution layer. 10. The method of claim 9,
Further comprising a lamination device stacked on top of the first semiconductor die,
Wherein the lamination device is electrically connected to the first rewiring layer outside the first semiconductor die. 10. The method of claim 9,
Further comprising a first encapsulant encapsulating the TMV semiconductor device and the first semiconductor die,
And a second penetrating electrode is formed in the first encapsulant. 17. The method of claim 16,
And the second penetrating electrode is formed at a position corresponding to the first rewiring layer. 18. The method of claim 17,
Further comprising a lamination device stacked on top of the first semiconductor die,
And the lamination device is electrically connected to the second penetrating electrode. A second wiring pattern formed on a lower surface of the first passivation layer; and a second wiring pattern formed on the lower surface of the first passivation layer to expose a part of the second wiring pattern to the outside A second passivation layer formed on the lower surface of the substrate, and a through via for electrically connecting the first wiring pattern and the second wiring pattern;
A first semiconductor die mounted on top of the substrate and electrically connected to the substrate;
And a first rewiring layer that is seated on the first semiconductor die and electrically connects the second semiconductor die and a first penetrating electrode formed on a side of the second semiconductor die and the second semiconductor die and the first penetrating electrode, TMV semiconductor devices; And
And a first encapsulant encapsulating the first semiconductor die and the TMV semiconductor device,
Wherein the TMV semiconductor device has the first rewiring layer electrically connected to the first wiring pattern outside the first semiconductor die. 20. The method of claim 19,
Wherein at least one bond pad is formed on a bottom surface of the second semiconductor die, a protective layer is formed on a bottom surface excluding the bond pad,
And the first re-wiring layer electrically connects the bond pad and the first penetrating electrode. 21. The method of claim 20,
Wherein the TMV semiconductor device further comprises a second encapsulant encapsulating a side of the second semiconductor die,
Wherein the first penetrating electrode is formed to penetrate the upper surface and the lower surface of the second encapsulant. 22. The method of claim 21,
And the first rewiring layer is formed to extend from a lower portion of the second semiconductor die to a lower portion of the second encapsulant. 22. The method of claim 21,
The TMV semiconductor device
A third passivation layer formed on a lower surface of the second semiconductor die and the second encapsulant and exposing a part of the bond pad to the outside;
A fourth passivation layer formed below the third passivation layer and covering the first redistribution layer; And
And a solder ball formed on the first re-wiring layer. 24. The method of claim 23,
Wherein the solder ball is electrically connected to the first wiring pattern of the substrate. 24. The method of claim 23,
Wherein the first encapsulant encapsulates the solder ball. 20. The method of claim 19,
Further comprising a lamination device stacked on top of the TMV semiconductor device,
And the lamination device is electrically connected to the first penetrating electrode. 20. The method of claim 19,
Further comprising a third semiconductor die formed between the first semiconductor die and the TMV semiconductor device and having a bond pad formed thereon,
Wherein the bond pad of the third semiconductor die is electrically connected to the first redistribution layer. 28. The method of claim 27,
Further comprising a lamination device stacked on top of the TMV semiconductor device,
And the lamination device is electrically connected to the first penetrating electrode. A TMV semiconductor device including a second semiconductor die and a first through electrode formed on a side of the second semiconductor die and a first rewiring layer electrically connecting the second semiconductor die and the first penetrating electrode; And
A first semiconductor die mounted on top of the TMV semiconductor device,
Wherein the first semiconductor die is electrically connected to the first rewiring layer,
At least one bond pad is formed on the upper surface of the second semiconductor die, a protective layer is formed on the upper surface except for the bond pad,
Wherein the TMV semiconductor device further comprises a second encapsulant encapsulating a side of the second semiconductor die,
The TMV semiconductor device
A third passivation layer formed on an upper surface of the second semiconductor die and the second encapsulant and exposing a part of the bond pad to the outside;
A fourth passivation layer formed on the third passivation layer and exposing a part of the first redistribution layer to the outside;
A fifth passivation layer formed on a lower surface of the second semiconductor die and the second encapsulant and exposing a part of the first penetrating electrode to the outside;
A second rewiring layer formed below the fifth passivation layer and electrically connected to the first penetrating electrode;
A sixth passivation layer formed below the fifth passivation layer and exposing a part of the second re-wiring layer to the outside; And
And a solder ball formed on the second re-wiring layer. 30. The method of claim 29,
And the first re-wiring layer electrically connects the bond pad and the first penetrating electrode. 31. The method of claim 30,
Wherein the first penetrating electrode is formed to penetrate the upper surface and the lower surface of the second encapsulant. 32. The method of claim 31,
Wherein the first rewiring layer is formed to extend from an upper portion of the second semiconductor die to an upper portion of the second encapsulant. delete 30. The method of claim 29,
And the second rewiring layer is formed to extend from a lower portion of the second semiconductor die to a lower portion of the second encapsulant. 30. The method of claim 29,
Further comprising a lamination device stacked on top of the first semiconductor die,
Wherein the lamination device is electrically connected to the first redistribution layer.

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