KR101398797B1 - Nonvolatile semiconductor memory device and erasure method therefor - Google Patents

Abstract

The nonvolatile semiconductor memory device of the present invention includes a first bit line LBL for commonly connecting the drain sides of the memory cells MC, a word line WL for commonly connecting the control gates of the memory cell transistors MT and a second bit line MBL A row decoder 14 for controlling the potential of the word line; a first transistor provided between the first bit line and the second bit line, the source being connected to the first bit line, the drain A first transistor SST connected to the column decoder through the second bit line, and a first control section 23 for controlling the potential of the gate of the first transistor. The memory cell is formed on the first well 26 And the first transistor is formed on the second well 74PS electrically isolated from the first well and the film thickness of the gate insulating film of the first transistor is set in the row decoder, Gate Isolation of 2 Transistors Is thinner than the film thickness of the film.

Description

TECHNICAL FIELD [0001] The present invention relates to a nonvolatile semiconductor memory device and a method of erasing the nonvolatile semiconductor memory device.

The present invention relates to a nonvolatile semiconductor memory device and an erasing method therefor.

Recently, a nonvolatile semiconductor memory device in which a memory cell having a select transistor and a memory cell transistor is formed is proposed.

In such a nonvolatile semiconductor memory device, a memory cell is selected by appropriately selecting a bit line, a word line, a source line, or the like by a column decoder or a row decoder, and reading, writing, erasing, etc. of information Is done. Background arts are as follows.

Japanese Patent Application Laid-Open No. 2000-235797 Japanese Patent Application Laid-Open No. 2005-268621 Japanese Patent Application Laid-Open No. 2004-228396

However, in the proposed nonvolatile semiconductor memory device, there was a case where a sufficiently fast operation speed could not be obtained.

It is an object of the present invention to provide a nonvolatile semiconductor memory device having a high operating speed and an erasing method therefor.

According to an aspect of the embodiment, there is provided a memory cell array including a memory cell array in which a plurality of memory cells having memory cell transistors are arranged in a matrix, a plurality of first bit lines commonly connected to the drain sides of the plurality of memory cells existing in the same column, A plurality of word lines commonly connected to control gates of the plurality of memory cell transistors existing in the same row; a column decoder connected to the plurality of second bit lines to control the potential of the plurality of second bit lines; A plurality of first transistors each connected between a first bit line and a second bit line, each of the first transistors being connected to a word line and controlling a potential of the plurality of word lines; And the drain of the first transistor is electrically connected to the column decoder via the second bit line And a first control section for controlling a potential of a gate of the plurality of first transistors, wherein the memory cell transistor is formed on a first well, and the first transistor is connected to the first well Further comprising a first voltage application unit for applying a voltage to the first well and a second voltage application unit for applying a voltage to the second well, the second voltage application unit being formed on a second well electrically separated from the first well, The film thickness of the gate insulating film of one transistor is thinner than the film thickness of the gate insulating film of the second transistor provided in the row decoder and connected to the word line.

According to another aspect of the embodiment, there is provided a semiconductor memory device including a memory cell array in which a plurality of memory cells having memory cell transistors are arranged in a matrix, a plurality of first bit lines commonly connecting the drain sides of the plurality of memory cells existing in the same column, A plurality of word lines commonly connected to control gates of the plurality of memory cell transistors existing in the same row; a column decoder connected to the plurality of second bit lines to control the potential of the plurality of second bit lines; A plurality of first transistors each connected between a first bit line and a second bit line, each of the first transistors being connected to a word line and controlling a potential of the plurality of word lines; And a drain of the first transistor is electrically connected to the column decoder via the second bit line, And a first control section for controlling a potential of a gate of the plurality of first transistors, wherein the memory cell transistor is formed on a first well, the first transistor is connected to the first well, And the gate electrode of the first transistor is formed in a second well electrically isolated from the gate electrode of the second transistor, A method for erasing a nonvolatile semiconductor memory device, the method comprising: setting the first well to a first potential, setting a gate electrode of the first transistor to a second potential or floating lower than the first potential, And erasing the information recorded in the memory cell while setting the third potential lower than the first potential. An erase method is provided.

According to the nonvolatile semiconductor memory device and the erase method thereof disclosed in the present application, the first well and the second well are electrically separated from each other, and the first transistor is formed on the second well. Therefore, when erasing information recorded in the memory cell transistor, it is possible to apply a voltage different from the voltage applied to the first well to the second well. Therefore, even when a relatively large voltage is applied to the first well when information is erased, the voltage applied to the first transistor can be made relatively small. Therefore, even when a low-voltage transistor is used as the first transistor, destruction of the first transistor sector can be prevented at the time of erasing. Since it is possible to use a low-voltage transistor as the first transistor, a sufficiently large read current can be obtained when reading the information recorded in the memory cell transistor. Therefore, the information recorded in the memory cell transistor can be judged at a high speed, and further, the information recorded in the memory cell transistor MT can be read at a high speed.

1 is a circuit diagram showing a nonvolatile semiconductor memory device according to the first embodiment.
2 is a cross-sectional view of the nonvolatile semiconductor memory device according to the first embodiment.
3 is a plan view showing a memory cell array of the nonvolatile semiconductor memory device according to the first embodiment.
4 is a cross-sectional view taken along line A-A 'in Fig. 3;
5 is a cross-sectional view taken along line B-B 'in Fig.
6 is a diagram showing the type of the transistor used in each component of the nonvolatile semiconductor memory device according to the first embodiment, the breakdown voltage of the transistor, and the film thickness of the gate insulating film of the transistor.
7 is a diagram showing a reading method, a recording method and an erasing method of the nonvolatile semiconductor memory device according to the first embodiment.
8 is a time chart showing the erasing method of the nonvolatile semiconductor memory device according to the first embodiment.
9 is a cross-sectional view showing the erasing method of the nonvolatile semiconductor memory device according to the first embodiment.
10 is a process sectional view (No. 1) showing a method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment.
11 is a process sectional view (No. 2) showing a method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment.
12 is a process sectional view (part 3) showing a method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment.
13 is a process sectional view (No. 4) showing a method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment.
14 is a process sectional view (No. 5) showing a method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment.
15 is a process sectional view (No. 6) showing a method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment.
16 is a process sectional view (No. 7) showing a method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment.
17 is a process sectional view (No. 8) showing a method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment.
18 is a process sectional view (No. 9) showing a method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment.
19 is a process sectional view (No. 10) showing a method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment.
20 is a process sectional view (No. 11) showing a method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment.
21 is a process sectional view (No. 12) showing a method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment.
22 is a process sectional view (No. 13) showing a method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment;
23 is a process sectional view (No. 14) showing a method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment.
24 is a process sectional view (No. 15) showing a method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment.
25 is a process sectional view (No. 16) showing a method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment.
26 is a cross-sectional view showing a nonvolatile semiconductor memory device according to a modification of the first embodiment.
27 is a circuit diagram showing a nonvolatile semiconductor memory device according to the second embodiment.
28 is a cross-sectional view of a nonvolatile semiconductor memory device according to the second embodiment.
29 is a plan view showing a memory cell array of a nonvolatile semiconductor memory device according to the second embodiment.
30 is a cross-sectional view taken along line C-C 'in Fig.
31 is a cross-sectional view taken along line D-D 'in Fig.
32 is a cross-sectional view taken along line E-E 'in Fig.
33 is a diagram showing the type of the transistor used in each component of the nonvolatile semiconductor memory device according to the second embodiment, the breakdown voltage of the transistor, and the film thickness of the gate insulating film of the transistor.
34 is a diagram showing a reading method, a recording method and an erasing method of the nonvolatile semiconductor memory device according to the second embodiment.
35 is a time chart showing the erasing method of the nonvolatile semiconductor memory device according to the second embodiment.
36 is a cross-sectional view showing the erasing method of the nonvolatile semiconductor memory device according to the second embodiment.
37 is a process sectional view (No. 1) showing a method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment.
38 is a process sectional view (part 2) showing a method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment.
39 is a process sectional view (part 3) showing a method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment.
40 is a process sectional view (part 4) showing a method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment.
41 is a process sectional view (No. 5) showing a method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment.
42 is a process sectional view (No. 6) showing a method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment.
FIG. 43 is a process sectional view (part 7) showing a method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment. FIG.
44 is a process sectional view (No. 8) showing a method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment.
45 is a process sectional view (No. 9) showing a method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment.
46 is a process sectional view (No. 10) showing a method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment.
47 is a process sectional view (No. 11) showing a method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment.
48 is a process sectional view (No. 12) showing a method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment.
FIG. 49 is a process sectional view (No. 13) showing a method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment. FIG.
FIG. 50 is a process sectional view (No. 14) showing a method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment. FIG.
51 is a process sectional view (No. 15) showing a method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment.
52 is a process sectional view (No. 16) showing a method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment.
53 is a process sectional view (No. 17) showing a method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment.
54 is a process sectional view (part 18) showing a method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment.
55 is a process sectional view (No. 19) showing a method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment.
56 is a circuit diagram showing a nonvolatile semiconductor memory device according to the third embodiment.
57 is a cross-sectional view showing a nonvolatile semiconductor memory device according to the third embodiment.
58 is a diagram showing the type of the transistor used in each constituent element of the nonvolatile semiconductor memory device according to the third embodiment, the breakdown voltage of the transistor, and the film thickness of the gate insulating film of the transistor.
59 is a diagram showing a reading method, a recording method and an erasing method of the nonvolatile semiconductor memory device according to the third embodiment.
60 is a cross-sectional view showing the erasing method of the nonvolatile semiconductor memory device according to the third embodiment.
61 is a circuit diagram showing a nonvolatile semiconductor memory device according to the fourth embodiment.
62 is a cross-sectional view showing a nonvolatile semiconductor memory device according to the fourth embodiment.
63 is a diagram showing the type of the transistor used in each constituent element of the nonvolatile semiconductor memory device according to the fourth embodiment, the breakdown voltage of the transistor, and the film thickness of the gate insulating film of the transistor.
Fig. 64 is a diagram showing a reading method, a recording method and an erasing method of the nonvolatile semiconductor memory device according to the fourth embodiment.
65 is a cross-sectional view showing the erasing method of the nonvolatile semiconductor memory device according to the fourth embodiment.
FIG. 66 is a process sectional view (No. 1) showing a method of manufacturing the nonvolatile semiconductor memory device according to the fourth embodiment. FIG.
FIG. 67 is a process sectional view (part 2) showing a method of manufacturing the nonvolatile semiconductor memory device according to the fourth embodiment. FIG.
68 is a process sectional view (part 3) showing a method of manufacturing the nonvolatile semiconductor memory device according to the fourth embodiment;
69 is a process sectional view (part 4) showing a method of manufacturing the nonvolatile semiconductor memory device according to the fourth embodiment;
70 is a process sectional view (No. 5) showing a method of manufacturing the nonvolatile semiconductor memory device according to the fourth embodiment.
71 is a process sectional view (No. 6) showing a method of manufacturing the nonvolatile semiconductor memory device according to the fourth embodiment;
FIG. 72 is a process sectional view (part 7) showing a method of manufacturing the nonvolatile semiconductor memory device according to the fourth embodiment. FIG.
73 is a process sectional view (No. 8) showing a method of manufacturing the nonvolatile semiconductor memory device according to the fourth embodiment;
74 is a process sectional view (No. 9) showing a method of manufacturing the nonvolatile semiconductor memory device according to the fourth embodiment;
75 is a process sectional view (No. 10) showing a method of manufacturing the nonvolatile semiconductor memory device according to the fourth embodiment;
76 is a process sectional view (No. 11) showing a method of manufacturing the nonvolatile semiconductor memory device according to the fourth embodiment;
77 is a process sectional view (No. 12) showing a method of manufacturing the nonvolatile semiconductor memory device according to the fourth embodiment;
78 is a process sectional view (No. 13) showing a method of manufacturing the nonvolatile semiconductor memory device according to the fourth embodiment;
79 is a circuit diagram showing a nonvolatile semiconductor memory device according to a reference example.
80 is a cross-sectional view showing a nonvolatile semiconductor memory device according to a reference example.

79 is a circuit diagram showing a nonvolatile semiconductor memory device according to a reference example. 80 is a cross-sectional view showing a nonvolatile semiconductor memory device according to a reference example.

As shown in Fig. 79, the nonvolatile semiconductor memory device according to the reference example has a plurality of memory cells MC having memory cell transistors MT. A plurality of memory cells MC arranged in a matrix form form a memory cell array. The memory cell array is divided into a plurality of sector SCTs.

The drains of the plurality of memory cell transistors MT existing in the same column are commonly connected by a local bit line LBL. The control gates of the plurality of memory cell transistors MT existing in the same row are commonly connected by the word lines WL. The sources of the plurality of memory cell transistors MT are electrically connected to the source lines, respectively.

In each sector SCT, a plurality of sector select transistors SST are provided. The local bit lines LBL for commonly connecting the drains of the plurality of memory cell transistors MT existing in the same column are connected to the sources of the sector select transistors SST, respectively. The drains of the plurality of sector select transistors SST existing in the same column are commonly connected by the main bit line MBL. The local bit line LBL is connected to the main bit line MBL via the sector select transistor SST. The gates of the sector select transistors SST are commonly connected by a sector select line SSL.

A plurality of main bit lines MBL for commonly connecting the drains of the sector select transistors SST are connected to the column decoder 212. The column decoder 212 is connected to a sense amplifier 213 for detecting a current flowing through the main bit line MBL. A plurality of word lines WL connected in common to the control gates of the memory cell transistors MT are connected to a row decoder 214. A plurality of sector select lines SSL for commonly connecting the gates of the sector select transistors SST are connected to the control circuit 223.

80, an element isolation region 222 for defining an element region is formed in the semiconductor substrate 220. In this case, In the memory cell array region 202, an N type well (N type diffusion layer) 224 formed in the semiconductor substrate 220 and a P type well 226 formed in the N type well 224 are formed. As shown in FIG. 79, the P-type well 226 is connected to the first voltage application circuit 215 via a wiring.

On the P-type well 226, a floating gate 230a is formed via a tunnel insulating film 228a. A control gate 234a is formed on the floating gate 230a via an insulating film 232a. Source / drain diffusion layers 236a and 236c are formed in the semiconductor substrate 220 on both sides of the laminate having the floating gate 230a and the control gate 234a. Thus, the memory cell transistor MT having the floating gate 230a, the control gate 234a, and the source / drain diffusion layers 236a and 236c is formed. The source diffusion layer 236 of the memory cell transistor MT is connected to the source line SL.

A P-type well 274P is formed in the semiconductor substrate 220 in the region 207 where the sector select transistor is formed. A gate electrode 234d is formed on the P-type well 274P with a gate insulating film 276 interposed therebetween. A source / drain diffusion layer 304 is formed in the semiconductor substrate 220 on both sides of the gate electrode 234d. In this way, the sector select transistor SST having the gate electrode 234d and the source / drain diffusion layer 304 is formed. The source diffusion layer 304 of the sector select transistor SST is connected to the drain diffusion layer 236c of the memory cell transistor MT via the local bit line LBL.

A P-type well 274P is formed in the semiconductor substrate 220 in the region 217 where the column decoder is formed. A gate electrode 234d is formed on the P-type well 274P with a gate insulating film 278 interposed therebetween. A source / drain diffusion layer 304 is formed in the semiconductor substrate 220 on both sides of the gate electrode 278. Thus, the NMOS transistor 312 having the gate electrode 234d and the source / drain diffusion layer 304 is formed.

The source diffusion layer 304 of the NMOS transistor 312 is connected to the drain diffusion layer 304 of the sector select transistor SST via the main bit line MBL. The drain diffusion layer 304 of the NMOS transistor 312 is connected to the internal circuit of the column decoder.

When the information recorded in the memory cell transistor MT is erased, the potential of the main bit line MBL is made floating. Further, the potential of the sector selection line SSL is set to 0V.

Next, the voltage application circuit 215 sets the potential of the P-type well 226 to 9 V, for example.

Next, the potentials of the word lines WL11 and WL12 connected to the memory cells MC in the first sector SCT1 to be erased are set to -9 V, for example. On the other hand, the potentials of the word lines WL21 and WL22 connected to the memory cells MC in the second sector SCT2 that are not to be erased are made floating, for example.

When the potential of the word lines WL11 and WL12 is set to, for example, -9 V, charges are discharged from the floating gate 230a of the memory cell transistor MT. As a result, no charge is accumulated in the floating gate 230a of the memory cell transistor MT, and information of the memory cell transistor MT is erased.

Thus, in the nonvolatile semiconductor memory device according to the reference example, when erasing information recorded in the memory cell transistor MT, a relatively high voltage of, for example, about 9 V is applied to the P-type well 226. The voltage applied to the P-type well 226 is applied to the source diffusion layer 304 of the sector select transistor SST through the local bit line LBL. Therefore, when erasing the information recorded in the memory cell transistor MT, a relatively large voltage is applied to the sector select transistor SST. For this reason, as the sector select transistor SST, a high breakdown voltage transistor having a relatively high breakdown voltage is used.

However, the high breakdown voltage transistor has a relatively small driving current as compared with the low voltage transistor. Therefore, when a high breakdown voltage transistor is used as the sector select transistor SST like the nonvolatile semiconductor memory device according to the reference example, a sufficiently large read current can not be obtained when reading information recorded in the memory cell transistor MT. For this reason, in the nonvolatile semiconductor memory device according to the reference example, it is difficult to determine the information recorded in the memory cell transistor MT at a high speed, and therefore it is difficult to read the information recorded in the memory cell transistor MT at a high speed .

[First Embodiment]

A nonvolatile semiconductor memory device, a reading method, a recording method, an erasing method, and a method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment will be described with reference to FIGS. 1 to 25. FIG.

(Nonvolatile semiconductor memory device)

First, a nonvolatile semiconductor memory device according to the present embodiment will be described with reference to Figs. 1 and 2. Fig. 1 is a circuit diagram showing a nonvolatile semiconductor memory device according to the present embodiment. 2 is a cross-sectional view of the nonvolatile semiconductor memory device according to the present embodiment.

As shown in Fig. 1, the nonvolatile semiconductor memory device according to the present embodiment has a plurality of memory cells MC having memory cell transistors MT. A plurality of memory cells MC are arranged in a matrix. A plurality of memory cells MC arranged in a matrix form form a memory cell array. The memory cell array is divided into a plurality of sector SCTs.

1, a first sector SCT1 and a second sector SCT2 of a plurality of sectors SCT are shown.

The drains of the plurality of memory cell transistors MT existing in the same column are commonly connected by a local bit line (first bit line) LBL.

The control gates of the plurality of memory cell transistors MT existing in the same row are commonly connected by the word lines WL.

1, word lines WL11, WL12, WL21, and WL22 among a plurality of word lines WL are shown.

The word line WL11 commonly connects the control gates of the plurality of memory cell transistors MT existing in the first row of the first sector SCT1. The word line WL12 connects the control gates of the plurality of memory cell transistors MT existing in the second row of the first sector SCT1 in common. The word line WL21 connects the control gates of the plurality of memory cell transistors MT existing in the first row of the second sector SCT2 in common. The word line WL22 connects the control gates of the plurality of memory cell transistors MT existing in the second row of the second sector SCT2 in common.

The sources of the plurality of memory cell transistors MT are electrically connected to the source lines SL, respectively.

Each of the sectors is provided with a plurality of sector select transistors (sector select transistors) SST. As the sector select transistor SST, a low-voltage transistor (low-breakdown-voltage transistor) having a relatively low rated voltage and withstand voltage is used.

Fig. 6 is a diagram showing the type of transistors used in each component, the breakdown voltage of the transistors, and the film thickness of the gate insulating film of the transistor.

As shown in FIG. 6, a low-voltage transistor 5 VTr having a rated voltage of, for example, 5 V is used as the sector select transistor SST. The breakdown voltage of the sector select transistor SST is, for example, about 8V. The film thickness of the gate insulating film 78 (see FIG. 25) of the sector select transistor SST is, for example, about 11 nm.

The low-voltage transistor (low-voltage transistor) is shorter in gate length, thinner in film thickness, and larger in driving current than a high-breakdown-voltage transistor (high-voltage transistor). In the present embodiment, since a low-voltage transistor is used as the sector select transistor SST, a large read current can be obtained. Therefore, since a large read current can be obtained, information recorded in the memory cell transistor MT can be judged at a high speed, and therefore it is possible to realize high-speed reading.

The local bit lines LBL for commonly connecting the drains of the plurality of memory cell transistors MT existing in the same column are connected to the sources of the sector select transistors (sector select transistors) SST, respectively.

The drains of the plurality of sector select transistors SST existing in the same column are commonly connected by a main bit line (second bit line, global bit line) MBL.

1, main bit lines MBL1 and MBL2 in a plurality of main bit lines MBL are shown. The local bit line LBL is connected to the main bit line MBL via the sector select transistor SST.

The gates of the sector select transistors SST are commonly connected by a sector select line (sector select line) SSL.

1, sector select lines SSL11, SSL12, SSL21, and SSL22 of a plurality of sector select lines SSL are shown.

A plurality of main bit lines MBL for commonly connecting the drains of the sector select transistors SST are connected to the column decoder 12. [ The column decoder 12 controls the potentials of the plurality of main bit lines MBL, respectively. The column decoder 12 is formed by a low voltage circuit operating at a relatively low voltage. A low-voltage circuit is a circuit that can operate at a high speed while having a relatively low withstand voltage.

Low-voltage transistors (low-voltage transistors) 112N and 112P (see Fig. 25) are used for the low-voltage circuit of the column decoder 12. [ As shown in Fig. 6, a low-voltage transistor 5 VTr having a rated voltage of, for example, 5 V is used for the column decoder 12. [ The internal voltages of the low-voltage transistors 112N and 112P used in the column decoder 12 are, for example, about 8V. The film thickness of the gate insulating film 78 (see FIG. 25) of the low-voltage transistors 112N and 112P used in the column decoder 12 is, for example, about 11 nm. The use of the low-voltage transistors 112N and 112P in the column decoder 12 makes it possible to read the information recorded in the memory cell transistor MT at a high speed.

The column decoder 12 is connected to a sense amplifier 13 for detecting a current flowing through the main bit line MBL.

The sense amplifier 13 uses low-voltage transistors 112N and 112P (see Fig. 25). As shown in Fig. 6, the sense amplifier 13 uses a low-voltage transistor 5 VTr having a rated voltage of 5V. The breakdown voltage of the low-voltage transistor used in the sense amplifier 13 is, for example, about 8V. The film thickness of the gate insulating film 78 (see FIG. 25) of the low-voltage transistors 112N and 112P used in the sense amplifier 13 is, for example, about 11 nm. Since the sense amplifier 13 uses the low-voltage transistors 112N and 112P, information recorded in the memory cell transistor MT can be judged at a high speed, and further, high-speed reading can be realized.

A plurality of word lines WL connected in common to the control gates 34a of the memory cell transistors MT are connected to the row decoder 14. [ The row decoder 14 controls the potentials of the plurality of word lines WL. The row decoder 14 is formed by a high voltage circuit (high voltage circuit). The high-voltage circuit is a relatively high-breakdown-voltage circuit while the operation speed is relatively low. High voltage transistors (high breakdown voltage transistors) 110N and 110P (see Figs. 2 and 25) are used for the high voltage circuit of the row decoder 14. As shown in Fig. 6, the high-voltage transistor 10 VTr having a rated voltage of, for example, 10 V is used for the row decoder 14. [ The breakdown voltage of the high breakdown voltage transistors 110N and 110P used in the row decoder 14 is, for example, about 12V. The film thickness of the gate insulating film 76 of the high voltage transistors 110N and 110P used in the row decoder 14 is, for example, about 16 nm.

The reason why the high breakdown voltage transistors 110N and 110P are used in the row decoder 14 is that when writing information to the memory cell transistor MT and erasing the information recorded in the memory cell transistor MT, This is because the high voltage is applied.

A plurality of sector select lines SSL for commonly connecting the gates of the sector select transistors SST are connected to a control circuit (control section) The control circuit 23 controls the potentials of the plurality of sector select lines SSL. The control circuit 23 is formed by a low-voltage circuit operating at a relatively low voltage.

The control circuit 23 uses a low-voltage circuit. Low-voltage transistors (low-voltage transistors) 112N and 112P (see Fig. 25) are used for the low-voltage circuit of the control circuit 23. As shown in Fig. 6, a low-voltage transistor 5 VTr having a rated voltage of, for example, 5 V is used as the control circuit 23. The internal voltages of the low-voltage transistors 112N and 112P used in the control circuit 23 are, for example, about 8V. The film thickness of the gate insulating film 78 of the low-voltage transistors 112N and 112P used in the control circuit 23 is, for example, about 11 nm. The use of the low-voltage transistors 112N and 112P in the control circuit 23 makes it possible to select the sector SCT at a high speed.

2A, an N-type well (N-type diffusion layer) 24 formed in the semiconductor substrate 20 and an N-type well (N-type diffusion layer) 24 are formed in the memory cell array region 2 of each sector SCT, And a P-type well 26 formed in the well 24 is formed. This structure is referred to as a triple well. The memory cell transistor MT is formed on such a triple well.

1, the P-type well 26 is connected to a first voltage applying circuit (first voltage applying portion) 15 via a wiring. The first voltage application circuit 15 controls the potential V _B1 of the P-type well 26. The first voltage applying circuit 15 is formed by a high voltage circuit. The high-voltage transistors 110N and 110P (see Figs. 2 and 25) are used for the high-voltage circuit of the first voltage application circuit 15. Fig. As shown in FIG. 6, the first voltage application circuit 15 uses a high-voltage transistor 10 VTr having a rated voltage of, for example, 10 V. The breakdown voltage of the high voltage transistors 110N and 110P used in the first voltage application circuit 15 is, for example, about 12V. The film thickness of the gate insulating film 76 (see FIG. 25) of the high voltage transistors 110N and 110P used in the first voltage applying circuit 15 is, for example, about 16 nm.

The use of the high voltage transistors 110N and 110P in the first voltage applying circuit 15 is to apply a high voltage to the P-type well 26 when erasing the information recorded in the memory cell transistor MT Because.

As shown in FIG. 2A, an N-type well (N-type diffusion layer) 25 is formed in the semiconductor substrate 20 in the region 7 where the sector select transistor is formed. In the N-type well 25, a P-type well 74PS is formed. The sector select transistor SST is formed on such a triple well.

As shown in Fig. 1, the P-type well 74PS is electrically connected to the second voltage applying circuit (second voltage applying portion) 17 via wiring. The second voltage application circuit 16 controls the potential V _B2 of the P-type well 74PS. The second voltage applying circuit 16 is formed by a low voltage circuit. The low-voltage transistors 112N and 112P (see Fig. 25) are used in the low-voltage circuit of the second voltage application circuit 17. Fig. As shown in Fig. 6, the second voltage applying circuit 17 uses a low-voltage transistor 5 VTr having a rated voltage of, for example, 5V. The internal voltages of the low-voltage transistors 112N and 112P used in the second voltage application circuit 17 are, for example, about 8V. The film thickness of the gate insulating film 78 (see FIG. 25) of the low-voltage transistors 112N and 112P used in the second voltage applying circuit 17 is, for example, about 11 nm.

Next, the structure of the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIGS. 2 to 5. FIG. 3 is a plan view showing a memory cell array of the nonvolatile semiconductor memory device according to the present embodiment. 4 is a cross-sectional view along the line A-A 'in Fig. 5 is a sectional view taken along the line B-B 'in Fig.

In the semiconductor substrate 20, an element isolation region 22 for defining the element region 21 is formed. As the semiconductor substrate 20, for example, a P-type silicon substrate is used. The element isolation region 22 is formed by, for example, STI (Shallow Trench Isolation) method.

As shown in FIG. 2A, an N-type well (N-type diffusion layer) 24 is formed in the semiconductor substrate 20 in the memory cell array region 2. This N-type well 24 is formed for each sector SCT (see FIG. 1). In the N-type well 24, a P-type well 26 is formed. The P-type well 26 is electrically separated from the semiconductor substrate 20 by the N-type well 24.

A floating gate 30a is formed on the P-type well 26 via a tunnel insulating film 28a. As shown in Fig. 5, the floating gate 30a is electrically isolated for each of the device regions 21.

A control gate 34a is formed on the floating gate 30a via an insulating film 32a. The control gates 34a of the memory cell transistors MT existing in the same row are connected in common. In other words, on the floating gate 30, word lines WL for commonly connecting the control gates 34a via the insulating film 32a are formed.

N-type impurity diffusion layers 36a and 36c are formed in the semiconductor substrate 20 on both sides of the floating gate 30a. The sources of the mutually adjacent memory cell transistors MT are formed by the same impurity diffusion layer 36a.

As shown in Fig. 4, a sidewall insulation film 37 is formed on the sidewall portion of the laminate having the floating gate 30a and the control gate 34a.

On the source region 36a and the drain region 36c and on the control gate 34a are formed silicide layers 38a to 38c made of, for example, cobalt silicide. The silicide layer 38a on the source diffusion layer 36a functions as a source electrode. The silicide layer 38c on the drain diffusion layer 36c functions as a drain electrode.

Thus, the memory cell transistor MT having the floating gate 30a, the control gate 34a, and the source / drain diffusion layers 36a and 36c is formed on the P-type well 26. [

An N-type well (N-type diffusion layer) 25 is formed in the semiconductor substrate 20 in the sector select transistor formation region 7. In the N-type well 25, a P-type well 74PS is formed. The P-type well 74PS is electrically separated from the semiconductor substrate 20 by the N-type well 25. [

A gate electrode 34d is formed on the P-type well 74PS with a gate insulating film 78 interposed therebetween. A source / drain diffusion layer 104, which is an N-type impurity diffusion layer, is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d.

In this way, the sector select transistor SST having the gate electrode 34d and the source / drain diffusion layer 104 is formed on the P-type well 74PS.

The P-type well 74PS and the P-type well 26 are electrically separated from each other by the N-type wells 24 and 25.

As shown in FIG. 2A, the source diffusion layer 104 of the sector select transistor SST and the drain diffusion layer 36c of the memory cell transistor MT are electrically connected by the local bit line LBL.

A P-type well 74P is formed in the region 27 where the column decoder is formed. A gate electrode 34d is formed on the P-type well 74P with a gate insulating film 78 interposed therebetween. A source / drain diffusion layer 104, which is an N-type impurity diffusion layer, is formed in the semiconductor substrate 20 on both sides of the gate electrode 34a.

Thus, the low-voltage N-channel transistor 112N having the gate electrode 34d and the source / drain diffusion layer 104 is formed in the region 27 where the column decoder is formed.

The source diffusion layer 104 of the low voltage N-channel transistor 112N of the column decoder 12 and the drain diffusion layer 104 of the sector select transistor SST are connected to each other by the main bit line MBL And are electrically connected. The drain diffusion layer 104 of the low-voltage N-channel transistor 112N is connected to the internal circuit (low voltage circuit) of the column decoder 12.

2 (b), an N-type well (N-type diffusion layer) 25 is formed in the semiconductor substrate 20. The N- In the N-type well 25, a P-type well 72P is formed. The P-type well 72P is electrically separated from the semiconductor substrate 20 by the N-type well 25. [

A gate electrode 34c is formed on the P-type well 72P with a gate insulating film 76 interposed therebetween. A source / drain diffusion layer 96, which is an N-type impurity diffusion layer, is formed in the semiconductor substrate 20 on both sides of the gate electrode 34c.

Thus, the high-voltage N-channel transistor 110N having the gate electrode 34c and the source / drain diffusion layer 96 is formed on the P-type well 72P.

In addition, an N-type well 72N is formed in the semiconductor substrate 20. A gate electrode 34c is formed on the N-type well 72N with a gate insulating film 76 interposed therebetween. In the semiconductor substrate 20 on both sides of the gate electrode 34c, a source / drain diffusion layer 100 which is a P type impurity diffusion layer is formed.

Thus, a high breakdown voltage P-channel transistor 110P having the gate electrode 34c and the source / drain diffusion layer 100 is formed.

The interlayer insulating film 40 is formed on the semiconductor substrate 20 on which the memory cell transistor MT, the sector select transistor SST, the low voltage transistors 112N and 112P and the high voltage transistors 110N and 110P are formed 5, Fig. 24, Fig. 25). The interlayer insulating film 40 is formed of, for example, a silicon nitride film 114 and a silicon oxide film 116 formed on the silicon nitride film 114 (see FIGS. 24 and 25).

In the interlayer insulating film 40, contact holes 42 each corresponding to the source electrode 38a and the drain electrode 38b are formed.

A conductor plug 44 made of, for example, tungsten is embedded in the contact hole 42.

A wiring (first metal wiring layer) 46 is formed on the interlayer insulating film 40 in which the conductor plug 44 is buried.

An interlayer insulating film 48 is formed on the interlayer insulating film 40 on which the wiring 46 is formed.

In the interlayer insulating film 48, a contact hole 50 reaching the wiring 46 is formed.

A conductor plug 52 made of, for example, tungsten is embedded in the contact hole 50.

A wiring (second metal wiring layer) 54 is formed on the interlayer insulating film 48 in which the conductor plug 52 is buried.

An interlayer insulating film 56 is formed on the interlayer insulating film 48 on which the wiring 54 is formed.

In the interlayer insulating film 56, a contact hole 58 reaching the wiring 54 is formed.

A conductor plug 60 made of tungsten, for example, is buried in the contact hole 58.

A wiring (third metal wiring layer) 62 is formed on the interlayer insulating film 56 in which the conductor plug 60 is buried.

(Operation of nonvolatile semiconductor memory device)

Next, an operation method of the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIGS. 7 and 8. FIG. 7 is a diagram showing a reading method, a recording method and an erasing method of the nonvolatile semiconductor memory device according to the present embodiment. In Fig. 7, F represents floating.

(Reading method)

First, a reading method of the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIG.

Here, the case of reading the information recorded in the memory cell MC surrounded by the broken line A and the memory cell MC surrounded by the broken line B in Fig. 1 will be described as an example.

When reading information recorded in the memory cell transistor MT, the potential of each part is set as follows.

That is, the potential of the sector selection line SSL11 connected to the sector select transistor SST connected to the memory cell MC to be selected is set to 1.8 V, for example. On the other hand, the potentials of the sector selection lines SSL12, SSL21, and SSL22 other than the selected sector selection line SSL11 are all 0V.

The potentials of the main bit lines (bit lines) MBL1 and MBL2 connected to the sector select transistor SST connected to the memory cell MC to be selected are set to 0.5 V, for example.

Further, the potential of the word line WL11 connected to the memory cell MC to be selected is set to 4.5 V, for example. On the other hand, the potentials of the word lines WL12, WL21, and WL22 other than the selected word line WL11 are set to 0V.

The potential V _B1 of the P-type well 26 is set to 0 V in all cases. In addition, the potential V _B2 of the P-type well 74PS is set to 0V. The potential of the source line SL is set to 0 V in all cases.

In the present embodiment, since the low-voltage transistor is used as the sector select transistor SST, a sufficiently large read current can be obtained when the information recorded in the memory cell transistor MT is read. A sufficiently large read current can be obtained. Therefore, according to the present embodiment, information recorded in the memory cell transistor MT can be judged at a high speed. Therefore, according to the present embodiment, information recorded in the memory cell transistor MT can be read at a high speed.

When information is recorded in the memory cell transistor MT, that is, when the information of the memory cell transistor MT is "0 ", charge is accumulated in the floating gate 30a of the memory cell transistor MT. In this case, no current flows between the source diffusion layer 36a and the drain diffusion layer 36c of the memory cell transistor MT, and no current flows through the selected main bit line MBL. In this case, the information of the memory cell transistor MT is judged to be "0 ".

On the other hand, when information recorded in the memory cell transistor MT is erased, that is, when the information of the memory cell is "1 ", no charge is accumulated in the floating gate 30a of the memory cell transistor MT. In this case, a current flows between the source diffusion layer 36a and the drain diffusion layer 36c of the memory cell transistor MT, and a current flows through the selected main bit line MBL. The current flowing through the selected main bit line MBL is detected by the sense amplifier 13. In this case, it is determined that the information of the memory cell transistor MT is "1 ".

(Recording method)

Next, a recording method of the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIG.

Here, a case where information is recorded in the memory cell MC surrounded by the broken line A in Fig. 1 will be described as an example.

When information is written in the memory cell transistor MT, the potential of each part is set as follows.

That is, the potential of the sector selection line SSL11 connected to the sector select transistor SST connected to the memory cell MC to be selected is set to, for example, 5V. On the other hand, the potentials of the sector selection lines SSL12, SSL21, and SSL22 other than the selected sector selection line SSL11 are all 0V.

Further, the potential of the main bit line (bit line) MBL1 connected to the sector select transistor SST connected to the memory cell MC to be selected is set to, for example, 4V. On the other hand, the potential of the main bit line MBL2 other than the selected main bit line MBL1 is set to 0V.

Further, the potential of the word line WL11 connected to the memory cell MC to be selected is set to 9 V, for example. On the other hand, the potentials of the word lines WL12, WL21, and WL22 other than the selected word line WL11 are set to 0V.

The potential V _B1 of the P-type well 26 is set to 0 V in all cases. In addition, the potential V _B2 of the P-type well 74PS is set to 0V. The potential of the source line SL is set to 0 V in all cases.

When the electric potential of each part is set as described above, electrons flow between the source diffusion layer 36a and the drain diffusion layer 36c of the memory cell transistor MT and electrons are introduced into the floating gate 30a of the memory cell transistor MT. As a result, charges are accumulated in the floating gate 30a of the memory cell transistor MT, and information is written in the memory cell transistor MT.

(Erase method)

Next, a method of erasing the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIGS. 7 to 9. FIG. 8 is a time chart showing the erasing method of the nonvolatile semiconductor memory device according to the present embodiment. The broken line in Fig. 8 indicates a potential of 0V. 9 is a cross-sectional view showing the erasing method of the nonvolatile semiconductor memory device according to the present embodiment.

Erasing of information recorded in the memory cell array is performed for each sector SCT, for example. Here, a case where the information recorded in the plurality of memory cells MC existing in the first sector SCT1 is collectively erased will be described as an example.

In the present embodiment, the information recorded in the memory cell transistor MT is erased as follows.

When the information recorded in the memory cell transistor MT is erased, the potential of the main bit line MBL is always set to the floating state. When the information recorded in the memory cell transistor MT is erased, the potential of the source line SL is always set to the floating state. The potential of the semiconductor substrate 20 is set to 0 V (ground).

To erase the information recorded in the memory cell transistor MT, the potential V _B2 of the P-type well _74PS is first set to the third potential V _ERS3 by the second voltage application circuit 17. [ Here, the third potential V _ERS3 is set to 5 V, for example.

Further, the potential of the sector selection line SSL is set to the second potential V _ERS2 . Here, the second potential V _ERS2 is set to 5 V, for example.

Next, the first voltage application circuit 15 sets the potential V _B1 of the P-type well 26 to the first potential V _ERS1 . Here, the first potential V _ERS1 is set to 9 V, for example.

Next, the potentials of the word lines WL11 and WL12 connected to the memory cells MC in the first sector SCT1 to be erased are set to -9 V, for example. On the other hand, the potentials of the word lines WL21 and WL22 connected to the memory cells MC in the second sector SCT2 that are not to be erased are made floating, for example.

When the potential of the word lines WL11 and WL12 is set to, for example, -9 V, charges are discharged from the floating gate 30a of the memory cell transistor MT. As a result, no charge is accumulated in the floating gate 30a of the memory cell transistor MT, and information of the memory cell transistor MT is erased.

As described above, when the information recorded in the memory cell transistor MT is erased, the potential (first potential) V _ERS1 of the P-type well 26 is set to, for example, _9V . When the potential V _ERS1 of the P-type well 26 is set to 9 V, the potential V _ERS1 'of the source diffusion layer 104 of the sector select transistor SST is about 8.5 to 8.7 V, for example. The reason why the potential V _ERS1 'of the source diffusion layer 104 is lower than the bias voltage V _ERS1 applied to the P-type well 26 is that the voltage drop by the diode formed by the P-type well 26 and the drain diffusion layer 36c .

When the potential (third potential) V _ERS3 of the P-type well _74PS is, for example, 5 V, the potential difference (V _ERS1 '- VRS3) between the source diffusion layer 104 of the sector select transistor SST and the P- V _ERS3 ) is about 3.5 to 3.7 V, for example. Since the breakdown voltage of the sector select transistor SST is, for example, about 8 V as described above, no breakage occurs between the source diffusion layer 104 and the P-type well 74PS of the sector select transistor SST.

In addition, the sector select line SSL of the potential (second electric potential) is V _ERS2 For example, if a 5 V, the potential difference (V _ERS1 '-V _ERS2) of a sector select transistor SST gate electrode (34d) and the source diffusion layer 104 of the For example, about 3.5 to 3.7 V. Since the breakdown voltage of the sector select transistor SST is, for example, about 8 V as described above, there is no breakdown between the gate electrode 34d of the sector select transistor SST and the source diffusion layer 104. [

When the potential (third potential) V _ERS3 of the P-type well _74PS is set to, for example, 5 V, the potential V _ERS3 of the source diffusion layer 104 of the low-voltage transistor 112N used in the column decoder 12 Is about 4.5 to 4.7 V, for example. The reason why the potential V _ERS3 'of the source diffusion layer 104 of the low voltage transistor 112N of the column decoder 12 is lower than the bias voltage V _ERS3 applied to the P-type well _74PS is that the potential _difference between the P- The voltage drop is caused by the diode formed by the diode 104.

Since the breakdown voltage of the low voltage transistor used in the column decoder 12 is, for example, about 8 V as described above, the breakdown of the low voltage transistor 112N of the column decoder 12 is not caused.

The electric potential of each part is not limited to the above.

The potential of the P-type well 26 (the first potential) V _ERS1, and the potential of the P-type well (74PS) (third electric potential) difference between the V _ERS3, sector select transistors, each of the electric potential is smaller than the breakdown voltage of the SST V _ERS1, V _ERS3 is set.

More specifically, the bias voltages V _ERS1 and V _ERS2 are set so that the difference between the potential V _ERS1 'of the source diffusion layer 104 of the sector select transistor SST and the potential V _ERS3 of the P-type well 74PS _becomes smaller than the breakdown voltage of the sector select transistor SST, V _ERS3 is set.

The difference between the potential (second potential) V _ERS2 of the gate electrode 34d of the sector select transistor SST and the potential (first potential) V _ERS1 of the P-type well 26 is smaller than the breakdown voltage of the sector select transistor SST The potentials V _ERS1 and V _ERS3 are set.

More strictly speaking, the sector select transistors SST of the potential V _ERS1 of the gate electrode potential V _ERS2 and the source diffusion layer 104 of (34d) 'difference, is smaller than the breakdown voltage of a sector select transistor SST each potential V _ERS1, V _ERS2 Is set.

The potential V _ERS3 of the P-type well 74PS is set such that the potential (third potential) V _ERS3 of the P-type well _74PS becomes smaller than the breakdown voltage of the low-voltage transistor 112N of the column decoder 12.

More precisely, the difference between the potential V _ERS3 'of the source diffusion layer 104 of the low-voltage transistor 112N of the column decoder 12 and the potential of the P-type well _74P is lower than the potential of the low- The third potential V _ERS3 is set so as to be smaller than the breakdown voltage of the _{transistor Tr3} .

The first potential V _ERS1 , the second potential V _ERS2 And the third potential V _ERS3 are all positive, the second potential V _ERS2 is set to be lower than the first potential V _ERS1 , and the third potential V _{ERS3 is} also set to be lower than the first potential V _ERS1 .

As described above, in this embodiment, the P-type well 74PS and the P-type well 26 are electrically separated by the N-type wells 24 and 25. On the P-type well 74PS, SST is formed. Therefore, in the present embodiment, it is possible to apply a bias voltage different from the voltage applied to the P-type well 26 to the P-type well 74PS when erasing the information recorded in the memory cell transistor MT. Therefore, even when a relatively large voltage is applied to the P-type well 26 at the time of erasing information, it is necessary to relatively reduce the potential difference between the source diffusion layer 104 of the sector select transistor SST and the P-type well 74PS It becomes possible. It is also possible to make the potential difference between the gate electrode 34d of the sector select transistor SST and the source diffusion layer 104 relatively small by applying a bias voltage to the gate electrode 34d of the sector select transistor SST. Therefore, according to the present embodiment, even when a low-voltage transistor having a relatively low internal voltage is used as the sector select transistor SST, it is possible to prevent the sector select transistor SST from being broken at the time of erasing. In the present embodiment, since a low-voltage transistor can be used as the sector select transistor SST, a sufficiently large read current can be obtained when information recorded in the memory cell transistor MT is read. Therefore, according to the present embodiment, information recorded in the memory cell transistor MT can be determined at a high speed, and further, information recorded in the memory cell transistor MT can be read at high speed.

In this example, the case where the potential V _ERS2 of the sector select line SSL is 5 V, for example, when erasing the information recorded in the memory cell transistor MT has been described as an example, however, the sector select line SSL may be electrically floating . The gate electrode 34d of the sector select transistor SST is capacitively coupled to the source diffusion layer 104 and the P-type well 74PS of the sector select transistor SST. Therefore, when the sector selection line SSL is set to the floating state, the potential V _ERS3 of the P-type well _74PS and the potential V _ERS1 'of the source diffusion layer 104 of the sector select transistor SST are applied to the gate electrode of the sector select transistor SST So that the potential of the signal line 34d rises. Therefore, even when the potential of the sector selection line SSL is set to be floating when erasing the information recorded in the memory cell transistor MT, the potential difference between the gate electrode 34d of the sector select transistor SST and the P-type well 74PS Is kept relatively small. In addition, the potential difference between the gate electrode 34d of the sector select transistor SST and the source / drain diffusion layer 102 of the sector select transistor SST is also kept relatively small. Therefore, even when the potential of the sector select line SSL is set to be floating when the information recorded in the memory cell transistor MT is erased, it is possible to prevent the sector select transistor SST from being broken at the time of erasing.

(Manufacturing Method of Nonvolatile Semiconductor Memory Device)

Next, a manufacturing method of the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIGS. 10 to 25. FIG. 10 to 25 are process sectional views showing a method of manufacturing the nonvolatile semiconductor memory device according to the present embodiment.

Figs. 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, 21A, 22, and 24 show the memory cell array region (core region) 2). Figs. 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, 21A, 22, and 24, the left side view of the drawing is a view of the BB of FIG. 3 'Section. Figs. 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, 21A, 22, and 24, the drawing on the right side of the drawing corresponds to AA 'Section.

Figures 10 (b), 11 (b), 12 (b), 13 (b), 14 (b), 15 (b), 16 17 (b), 18 (b), 19 (b), 20 (b), 21 (b), 23 and 25 show the peripheral circuit region 4 .

Figures 10 (b), 11 (b), 12 (b), 13 (b), 14 (b), 15 (b), 16 17 (b), 18 (b), 19 (b), 20 (b), 21 (b), 23 and 25, And the area 6 is shown.

The region 6 on the left side of the region 6 where the high breakdown voltage transistor is formed represents the region 6N where the high breakdown voltage N-channel transistor is formed. The right side of the region 6N where the high-breakdown-voltage N-channel transistor is formed represents the region 6P where the high-breakdown-voltage P-channel transistor is formed.

The right side of the region 6P where the high breakdown voltage P-channel transistor is formed shows the region 7 where the sector select transistor is formed.

Figures 10 (b), 11 (b), 12 (b), 13 (b), 14 (b), 15 (b), 16 17 (b), 18 (b), 19 (b), 20 (b), 21 (b), 23 and 25, (8).

The left side of the region 8 where the low-voltage transistor is formed represents the region 8N where the low-voltage N-channel transistor is formed, and the right side of the region 8 where the low-voltage transistor is formed is the region 8P).

First, as shown in Fig. 10, a semiconductor substrate 20 is prepared. As the semiconductor substrate 20, for example, a P-type silicon substrate is prepared.

Next, a thermal oxidation film 64 having a thickness of 15 nm, for example, is formed on the entire surface by, for example, thermal oxidation.

Next, a silicon nitride film 66 having a film thickness of 150 nm, for example, is formed on the entire surface by, for example, CVD.

Next, a photoresist film (not shown) is formed on the entire surface by, for example, a spin coating method.

Next, an opening (not shown) is formed in the photoresist film by photolithography. This opening is for patterning the silicon nitride film 66.

Next, the silicon nitride film 66 is patterned using the photoresist film as a mask. Thus, a hard mask 66 made of a silicon nitride film is formed.

Next, the semiconductor substrate 20 is etched by dry etching using the hard mask 66 as a mask. Thus, a groove 68 is formed in the semiconductor substrate 20. The depth of the groove 68 formed in the semiconductor substrate 20 is set to 400 nm from the surface of the semiconductor substrate 20, for example.

Next, the exposed portion of the semiconductor substrate 20 is oxidized by thermal oxidation. As a result, a silicon oxide film (not shown) is formed on the exposed portion of the semiconductor substrate 20.

Next, a silicon oxide film 22 having a thickness of 700 nm, for example, is formed on the entire surface by a high-density plasma CVD method.

Next, the silicon oxide film 22 is polished by CMP (Chemical Mechanical Polishing) until the surface of the silicon nitride film 66 is exposed. Thus, an element isolation region 22 made of a silicon oxide film is formed (see FIG. 11).

Next, a heat treatment for curing the element isolation region 22 is performed. The heat treatment conditions are, for example, 900 占 폚 for 30 minutes in a nitrogen atmosphere.

Next, the silicon nitride film 66 is removed by wet etching.

Next, as shown in Fig. 12, a sacrifice oxide film 69 is grown on the surface of the semiconductor substrate 20 by thermal oxidation.

Next, as shown in FIG. 13, an N-type buried diffusion layer 24 is formed by deeply implanting N-type dopant impurities into the memory cell array region 2. An N-type buried diffusion layer 25 is also formed by implanting an N-type dopant impurity deep into the region 6N where the high-breakdown-voltage N-channel transistor is formed. The N type buried diffusion layer 25 is also formed by implanting N type dopant impurities deep into the region 7 where the sector select transistor is formed. A P-type well 26 is formed by implanting a P-type dopant impurity into the memory cell array region 2 shallower than the buried diffusion layer 24. The P-type well 72P is formed by implanting a P-type dopant impurity shallower than the buried diffusion layer 25 in the region 6N where the high-voltage N-channel transistor is formed.

Next, in the region 6N in which the high-breakdown-voltage N-channel transistor is formed, the N-type diffusion layer 70 is formed in a frame shape. This frame-type diffusion layer 70 is formed so as to extend from the surface of the semiconductor substrate 20 to the periphery of the buried diffusion layer 25. [ The P type well 72P is surrounded by the buried diffusion layer 25 and the diffusion layer 70. [

The N-type diffusion layer 70 is also formed in the frame 7 in the region 7 where the sector select transistor is formed. This frame-type diffusion layer 70 is formed so as to extend from the surface of the semiconductor substrate 20 to the periphery of the buried diffusion layer 25. [

Although not shown, the P-type well 26 of the memory cell array region 2 is also surrounded by the buried diffusion layer 24 and the frame-shaped diffusion layer 70.

Next, an N-type well 72N is formed by introducing an N-type dopant impurity into the region 6P where the high-breakdown-voltage P-channel transistor is formed.

Next, channel doping is performed on the memory cell array region 2 (not shown).

Next, channel doping is performed on the region 6N where the high-breakdown-voltage N-channel transistor is formed and the region 6P where the high breakdown voltage P-channel transistor is formed (not shown).

Next, the sacrifice oxide film 69 existing on the surface of the semiconductor substrate 20 is removed by etching.

Next, a tunnel insulating film 28 having a thickness of 10 nm is formed on the entire surface by thermal oxidation (see Fig. 14).

Next, a polysilicon film 30 having a film thickness of 90 nm is formed on the entire surface by, for example, CVD. As the polysilicon film 30, a polysilicon film doped with an impurity is formed.

Next, the polysilicon film 30 in the memory cell region 2 is patterned, and the polysilicon film 30 existing in the peripheral circuit region 4 is etched away.

Next, an insulating film (ONO film) 32 formed by sequentially laminating a silicon oxide film, a silicon nitride film, and a silicon oxide film on the entire surface is formed. This insulating film 32 is for insulating the floating gate 30a and the control gate 34a.

Next, a P-type well 74P is formed by introducing a P-type dopant impurity into the region 8N where the low-voltage N-channel transistor is formed. A P-type well 74PS is formed by introducing a P-type dopant impurity into the region 7 where the sector select transistor is formed.

Next, an N-type well 74N is formed by introducing an N-type dopant impurity into the region 8P in which the low-voltage P-channel transistor is formed.

Next, channel doping is performed on the region 8N where the low-voltage N-channel transistor is formed, the region 8P where the low-voltage P-channel transistor is formed, and the region 7 where the sector select transistor is formed (not shown).

Next, the insulating film (ONO film) 32 present in the peripheral circuit region 4 is removed by etching.

Next, a gate insulating film 76 having a thickness of 9 nm, for example, is formed on the entire surface by thermal oxidation (see FIG. 15).

Next, the region 7 where the sector select transistor is formed and the gate insulating film 76 existing in the region 8 where the low-voltage transistor is formed are removed by wet etching.

Next, a gate insulating film 78 having a film thickness of, for example, 11 nm is formed on the entire surface by thermal oxidation. Thus, in the region 7 where the sector select transistor is formed and the region 8 where the low-voltage transistor is formed, for example, a gate insulating film 78 with a film thickness of 11 nm is formed. On the other hand, in the region 6 where the high breakdown voltage transistor is formed, the film thickness of the gate insulating film 76 is, for example, about 16 nm (see FIG. 16).

Next, a polysilicon film 34 having a thickness of, for example, 180 nm is formed on the entire surface by, for example, CVD.

Next, an antireflection film 80 is formed on the entire surface (see FIG. 17).

18, the antireflection film 80, the polysilicon film 34, the insulating film 32, and the polysilicon film 30 are dry-etched by using the photolithography technique. As a result, a laminate having a floating gate 30a made of polysilicon and a control gate 34a made of polysilicon is formed in the memory cell array region 2.

Next, a silicon oxide film (not shown) is formed on the sidewall portions of the floating gate 30a and the sidewall portions of the control gate 34a by thermal oxidation.

Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

Next, an opening (not shown) exposing the memory cell array region 2 is formed in the photoresist film by photolithography.

Next, an N-type dopant impurity is introduced into the semiconductor substrate 20 using the photoresist film as a mask. Accordingly, the impurity diffusion layers 36a and 36c are formed in the semiconductor substrate 20 on both sides of the floating gate 30a. Thereafter, the photoresist film is peeled off.

Thus, the memory cell transistor MT having the floating gate 30a, the control gate 34a, and the source / drain diffusion layers 36a and 36c is formed.

Next, a silicon oxide film 82 is formed on the sidewall portion of the floating gate 30a and the sidewall portion of the control gate 34a by thermal oxidation.

Next, a silicon nitride film 84 having a thickness of 50 nm is formed by, e.g., CVD.

Next, the silicon nitride film 84 is anisotropically etched by dry etching to form a sidewall insulation film 84 made of a silicon nitride film. At this time, the antireflection film 80 is etched away.

Next, using the photolithography technique, the region 6 in which the high breakdown voltage transistor is formed and the polysilicon film 34 in the region 8 in which the low voltage transistor is formed are patterned. Thus, the gate electrodes 34c of the high voltage transistors 110N and 110P made of the polysilicon film 34 are formed. Further, the gate electrode 34d of the low-voltage transistors 112N and 112P made of polysilicon 34 is formed. In addition, the gate electrode 34d of the sector select transistor SST made of polysilicon 34 is formed.

Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

Next, an opening (not shown) exposing the region 6N in which the high-voltage N-channel transistor is formed is formed in the photoresist film by photolithography.

Next, an N-type dopant impurity is introduced into the semiconductor substrate 20 using the photoresist film as a mask. Thus, the N type lightly doped diffusion layer 86 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34c of the high-voltage N-channel transistor 110N. Thereafter, the photoresist film is peeled off.

Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

Next, an opening (not shown) exposing the region 6P in which the high voltage P-channel transistor is formed is formed in the photoresist film by photolithography.

Next, using the photoresist film as a mask, a P-type dopant impurity is introduced into the semiconductor substrate 20. Thus, a P-type low-concentration diffusion layer 88 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34c of the high-breakdown-voltage P-channel transistor 110P. Thereafter, the photoresist film is peeled off.

Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

Next, an opening (not shown) exposing an opening (not shown) exposing the region 7 where the sector select transistor is formed and an area 8N where the low voltage N-channel transistor is formed is formed by photolithography, Is formed on the photoresist film.

Next, an N-type dopant impurity is introduced into the semiconductor substrate 20 using the photoresist film as a mask. Thus, the N type lightly doped diffusion layer 90 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d of the sector select transistor SST. An N-type lightly doped diffusion layer 90 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d of the low-voltage N-channel transistor 112N. Thereafter, the photoresist film is peeled off.

Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

Next, an opening (not shown) exposing the region 8P in which the low-voltage P-channel transistor is formed is formed in the photoresist film by photolithography.

Next, using the photoresist film as a mask, a P-type dopant impurity is introduced into the semiconductor substrate 20. Thus, a P-type lightly doped diffusion layer 92 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d of the low-voltage P-channel transistor 112P. Thereafter, the photoresist film is peeled off (see Fig. 19).

Next, a silicon oxide film 93 having a thickness of 100 nm is formed by, e.g., CVD.

Next, the silicon oxide film 93 is anisotropically etched by dry etching. Thus, a sidewall insulating film 93 made of a silicon oxide film is formed on the sidewall portion of the laminate having the floating gate 30a and the control gate 34a. A sidewall insulation film 93 made of a silicon oxide film is formed on the sidewall portions of the gate electrodes 34c and 34d.

Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

Next, an opening (not shown) exposing the region 6N in which the high-voltage N-channel transistor is formed is formed in the photoresist film by photolithography.

Next, an N-type dopant impurity is introduced into the semiconductor substrate 20 using the photoresist film as a mask. Thus, an N-type high-concentration diffusion layer 94 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34c of the high-breakdown-voltage N-channel transistor 110N. An N-type source / drain diffusion layer 96 of an LDD structure is formed by the N-type low-concentration diffusion layer 86 and the N-type high-concentration diffusion layer 94. Thus, the high-breakdown-voltage N-channel transistor 110N having the gate electrode 34c and the source / drain diffusion layer 96 is formed. The high breakdown voltage N-channel transistor 110N is used in a high voltage circuit (high breakdown voltage circuit). Thereafter, the photoresist film is peeled off.

Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

Next, an opening (not shown) exposing the region 6P in which the high voltage P-channel transistor is formed is formed in the photoresist film by photolithography.

Next, using the photoresist film as a mask, a P-type dopant impurity is introduced into the semiconductor substrate 20. Thus, a P-type high-concentration diffusion layer 98 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34c of the high-breakdown-voltage P-channel transistor 110P. The P-type source / drain diffusion layer 100 of the LDD structure is formed by the P-type low-concentration diffusion layer 88 and the P-type high-concentration diffusion layer 98. Thus, a high breakdown voltage P-channel transistor 110P having the gate electrode 34c and the source / drain diffusion layer 100 is formed. The high breakdown voltage p-channel transistor 110P is used in a high voltage circuit (high breakdown voltage circuit). Thereafter, the photoresist film is peeled off.

Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

Next, an opening (not shown) exposing an opening (not shown) exposing the region 7 where the sector select transistor is formed and an area 8N where the low voltage N-channel transistor is formed is formed by photolithography, Is formed on the photoresist film.

Next, an N-type dopant impurity is introduced into the semiconductor substrate 20 using the photoresist film as a mask. Thus, an N-type high concentration diffusion layer 102 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d of the sector select transistor SST. An N-type high-concentration diffusion layer 102 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d of the low-voltage N-channel transistor 112N. An N-type source / drain diffusion layer 104 of an LDD structure is formed by the N-type low-concentration diffusion layer 90 and the N-type high-concentration diffusion layer 102. Thus, the sector select transistor SST having the gate electrode 34d and the source / drain diffusion layer 104 is formed. Further, a low-voltage N-channel transistor 112N having a gate electrode 34d and a source / drain diffusion layer 104 is formed. The low voltage N-channel transistor 112N is used in a low voltage circuit. Thereafter, the photoresist film is peeled off.

Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

Next, an opening (not shown) exposing the region 8P in which the low-voltage P-channel transistor is formed is formed in the photoresist film by photolithography.

Next, using the photoresist film as a mask, a P-type dopant impurity is introduced into the semiconductor substrate 20. Thus, the P-type high-concentration diffusion layer 106 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d of the low-voltage P-channel transistor 112P. The P-type source / drain diffusion layer 108 of the LDD structure is formed by the P-type low-concentration diffusion layer 92 and the P-type high-concentration diffusion layer 106. [ Thus, the low-voltage P-channel transistor 112P having the gate electrode 34d and the source / drain diffusion layer 108 is formed. The low-voltage P-channel transistor 112P is used in a low-voltage circuit. Thereafter, the photoresist film is peeled off (see Fig. 20).

Next, a cobalt film having a thickness of 10 nm, for example, is formed on the entire surface by, for example, sputtering.

Next, the silicon atoms on the surface of the semiconductor substrate 20 and the cobalt atoms in the cobalt film are reacted by performing the heat treatment. Further, the silicon atoms on the surface of the control gate 34c are reacted with the cobalt atoms in the cobalt film. Further, the silicon atoms on the surface of the polysilicon film 34d are reacted with the cobalt atoms in the cobalt film. Further, the silicon atoms on the surfaces of the gate electrodes 34c and 34d are reacted with the cobalt atoms in the cobalt film. Thus, the cobalt silicide films 38a and 38b are formed on the source / drain diffusion layers 36a and 36c. Further, a cobalt silicide film 38c is formed on the control gate 34a. In addition, a cobalt silicide film 38e is formed on the source / drain diffusion layers 96, 100, 104, Further, a cobalt silicide film 38f is formed on the gate electrodes 34c and 34d.

Next, unreacted cobalt film is removed by etching.

The cobalt silicide film 38a formed on the source diffusion layer 36a of the memory cell transistor MT functions as a source electrode. The cobalt silicide film 38b formed on the drain diffusion layer 36c of the memory cell transistor MT also functions as a drain electrode.

The cobalt silicide film 38e formed on the source / drain diffusion layers 96 and 100 of the high-voltage transistors 110N and 110P functions as a source / drain electrode.

The cobalt silicide film 38e formed on the source / drain diffusion layer 104 of the sector select transistor SST functions as a source / drain electrode.

The cobalt silicide film 38e formed on the source / drain diffusion layers 104 and 108 of the low-voltage transistors 112N and 112P functions as a source / drain electrode (see FIG. 21).

Next, a silicon nitride film 114 having a thickness of 100 nm is formed on the entire surface by, for example, CVD. The silicon nitride film 114 functions as an etching stopper.

Next, a silicon oxide film 116 having a thickness of 1.6 占 퐉 is formed on the entire surface by a CVD method. Thus, an interlayer insulating film 40 composed of the silicon nitride film 114 and the silicon oxide film 116 is formed.

Next, the surface of the interlayer insulating film 40 is planarized by a CMP method.

Next, a contact hole 42 reaching the source / drain electrodes 38a and 38b, a contact hole 42 reaching the cobalt silicide film 38e, and a contact reaching the cobalt silicide film 38f are formed by photolithography. Holes 42 are formed.

Next, a barrier layer (not shown) made of a Ti film and a TiN film is formed on the entire surface by sputtering.

Next, a tungsten film 44 having a film thickness of 300 nm is formed on the entire surface by, for example, CVD.

Next, the tungsten film 44 and the barrier film are polished by CMP until the surface of the interlayer insulating film 40 is exposed. In this manner, a conductor plug 44 made of, for example, tungsten is embedded in the contact hole 42.

Next, a laminated film 46 is formed by sequentially laminating a Ti film, a TiN film, an Al film, a Ti film and a TiN film on the interlayer insulating film 40 in which the conductor plugs 44 are buried by, for example, sputtering. .

Next, the laminated film 46 is patterned by photolithography. Thus, a wiring (first metal wiring layer) 46 made of a laminated film is formed (see FIGS. 22 and 23).

Next, as shown in FIGS. 24 and 25, a silicon oxide film 118 having a thickness of 700 nm is formed by, for example, a high-density plasma CVD method.

Next, the silicon oxide film 120 is formed by the TEOS CVD method. The interlayer insulating film 48 is formed by the silicon oxide film 118 and the silicon oxide film 120. [

Next, a contact hole 50 reaching the wiring 46 is formed in the interlayer insulating film 48 by photolithography.

Next, a barrier layer (not shown) made of a Ti film and a TiN film is formed on the entire surface by sputtering.

Next, a tungsten film 52 having a film thickness of 300 nm is formed on the entire surface by, for example, CVD.

Next, the tungsten film 52 and the barrier film are polished until the surface of the interlayer insulating film 48 is exposed by the CMP method. In this way, a conductor plug 52 made of, for example, tungsten is embedded in the contact hole 50.

Next, a laminated film 54 is formed by sequentially laminating a Ti film, a TiN film, an Al film, a Ti film and a TiN film on the interlayer insulating film 48 in which the conductor plugs 52 are buried by, for example, sputtering. .

Next, the laminated film 54 is patterned by photolithography. Thus, a wiring (second metal wiring layer) 54 made of a laminated film is formed.

Next, a silicon oxide film 122 is formed by, for example, high-density plasma CVD.

Next, a silicon oxide film 124 is formed by a TEOS CVD method. The interlayer insulating film 56 is formed by the silicon oxide film 122 and the silicon oxide film 124. [

Next, a contact hole 58 reaching the wiring 54 is formed in the interlayer insulating film 56 by photolithography.

Next, a barrier layer (not shown) made of a Ti film and a TiN film is formed on the entire surface by sputtering.

Next, a 300 nm-thick tungsten film 60 is formed on the entire surface by, for example, CVD.

Next, the tungsten film 60 and the barrier film are polished by CMP until the surface of the interlayer insulating film 56 is exposed. In this way, a conductor plug 60 made of, for example, tungsten is embedded in the contact hole 58.

Next, a laminated film 62 is formed on the interlayer insulating film 56 in which the conductor plug 60 is buried, for example, by the sputtering method.

Next, the laminated film 62 is patterned by photolithography. Thus, a wiring (third metal wiring layer) 62 made of a laminated film is formed.

Next, a silicon oxide film 126 is formed by, for example, high-density plasma CVD.

Next, a silicon oxide film 128 is formed by a TEOS CVD method. The interlayer insulating film 130 is formed by the silicon oxide film 126 and the silicon oxide film 128.

Next, a contact hole 132 reaching the wiring line 62 is formed in the interlayer insulating film 130 by photolithography.

Next, a barrier layer (not shown) made of a Ti film and a TiN film is formed on the entire surface by sputtering.

Next, a tungsten film 134 having a film thickness of 300 nm is formed on the entire surface by, for example, a CVD method.

Next, the tungsten film 134 and the barrier film are polished by a CMP method until the surface of the interlayer insulating film 130 is exposed. In this way, a conductive plug (not shown) 134 made of, for example, tungsten is embedded in the contact hole 132.

Next, a laminated film 136 is formed on the interlayer insulating film 130 in which the conductor plug 134 is buried by, for example, sputtering.

Next, the laminated film 136 is patterned by photolithography. Thus, a wiring (fourth metal wiring layer) 136 made of a laminated film is formed.

Next, a silicon oxide film 138 is formed by, for example, high-density plasma CVD.

Next, a silicon oxide film 140 is formed by a TEOS CVD method. The interlayer insulating film 142 is formed by the silicon oxide film 138 and the silicon oxide film 140. [

Next, a contact hole 143 reaching the wiring 136 is formed in the interlayer insulating film 142 by photolithography.

Next, a barrier layer (not shown) made of a Ti film and a TiN film is formed on the entire surface by sputtering.

Next, a tungsten film 146 having a film thickness of 300 nm is formed on the entire surface by, for example, CVD.

Next, the tungsten film 146 and the barrier film are polished by CMP until the surface of the interlayer insulating film 142 is exposed. Thus, a conductive plug 144 made of, for example, tungsten is embedded in the contact hole 143.

Next, a laminated film 145 is formed on the interlayer insulating film 142 in which the conductor plug 144 is buried by, for example, sputtering.

Next, the laminated film 145 is patterned by using a photolithography technique. Thus, a wiring (fifth metal wiring layer) 145 made of a laminated film is formed.

Next, a silicon oxide film 146 is formed by, for example, high-density plasma CVD.

Next, a silicon nitride film 148 having a thickness of 1 占 퐉 is formed by a plasma CVD method.

Thus, the nonvolatile semiconductor memory device according to the present embodiment is manufactured.

(Modified example)

Next, a nonvolatile semiconductor memory device according to a modification of the present embodiment will be described with reference to FIG. 26 is a cross-sectional view showing a nonvolatile semiconductor memory device according to the present modification.

The N-type well (N-type diffusion layer) in the memory cell array region 2 and the N-type well (N-type well) in the sector select transistor formation region 7 in the non- Diffusion layer) are integrally formed.

As shown in Fig. 26, an N-type well (N-type diffusion layer) 24a is formed in the memory cell array region 2 and the sector select transistor formation region 7. The N-type well 24a is formed for each sector SCT.

In the N-type well 24a in the memory cell array region 2, a P-type well 26 is formed.

In the N-type well 24a in the sector select transistor formation region 7, a P-type well 74PS is formed.

The P-type well 74PS and the P-type well 26 are electrically separated by the N-type well 24a.

In this manner, the N-type well 24a in the memory cell array region 2 and the N-type well 24a in the sector select transistor formation region 7 may be integrally formed.

[Second Embodiment]

A nonvolatile semiconductor memory device, a reading method, a recording method, an erasing method and a manufacturing method of the nonvolatile semiconductor memory device according to the second embodiment will be described with reference to FIGS. 27 to 55. FIG. The same components as those of the nonvolatile semiconductor memory device or the like according to the first embodiment shown in Figs. 1 to 26 are denoted by the same reference numerals, and the description thereof is omitted or simplified.

(Nonvolatile semiconductor memory device)

First, a nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIGS. 27 to 36. FIG. 27 is a circuit diagram showing a nonvolatile semiconductor memory device according to the present embodiment. 28 is a cross-sectional view of the nonvolatile semiconductor memory device according to the present embodiment.

27, the memory cell MC is formed by the selection transistor ST and the memory cell transistor MT connected to the selection transistor ST. The source of the selection transistor ST is connected to the drain of the memory cell transistor MT. More specifically, the source of the selection transistor ST and the drain of the memory cell transistor MT are formed integrally with one impurity diffusion layer 36b (see FIG. 28).

The drains of the plurality of select transistors ST existing in the same column are connected in common by the local bit lines LBL.

The control gates of the plurality of memory cell transistors MT existing in the same row are commonly connected by the first word line CG.

27, first word lines CG11, CG12, CG21, and CG22 of a plurality of first word lines CG are shown.

The select gates of the plurality of select transistors ST existing in the same row are connected in common by the second word line SG.

27, the second word lines SG11, SG12, SG21, and SG22 of the plurality of second word lines SG are shown.

The sources of the plurality of memory cell transistors MT existing in the same row are connected in common by the source line SL. The sources of the memory cell transistors MT in mutually adjacent rows are connected by a common source line SL.

In Fig. 27, the source lines SL11 and SL21 of the plurality of source lines SL are shown.

In each sector, a plurality of sector select transistors (sector select transistors) SST are provided. As the sector select transistor SST, a low-voltage transistor having a relatively low withstand voltage is used.

33 is a diagram showing the type of the transistor used in each component, the breakdown voltage of the transistor, and the film thickness of the gate insulating film of the transistor.

As shown in Fig. 33, a low-voltage transistor 3 VTr having a rated voltage of, for example, 3 V is used as the sector select transistor SST. The breakdown voltage of the sector select transistor SST is about 6 V, for example. The film thickness of the gate insulating film 77 of the sector select transistor SST is, for example, about 6 nm. The gate insulating film 77 of the sector select transistor SST is formed by the same gate insulating film as the second low voltage transistors 113N and 113P (see FIG. 55) described later. Therefore, the film thickness of the gate insulating film 77 of the sector select transistor SST is equal to the film thickness of the gate insulating film 77 of the second low-voltage transistors 113N and 113P.

The sector select transistor SST has a short gate length, a thin film thickness of the gate insulating film 77, and a large drive current as compared with the high breakdown voltage transistors 110N and 110P (see FIG. 54). In the present embodiment, since a low-voltage transistor is used as the sector select transistor SST, a large read current can be obtained. Therefore, in the present embodiment, it is possible to determine the information recorded in the memory cell transistor MT at a high speed, and furthermore, it is possible to realize high-speed reading.

The local bit lines LBL for commonly connecting the drains of the plurality of memory cell transistors MT existing in the same column are connected to the sources of the sector select transistors (sector select transistors) SST, respectively.

The drains of the plurality of sector select transistors SST existing in the same column are commonly connected by a main bit line (bit line, global bit line) MBL. Each of the local bit lines LBL is electrically connected to the main bit line MBL through the sector select transistor SST.

In Fig. 27, main bit lines MBL1 and MBL2 of a plurality of main bit lines MBL are shown.

The gates of the sector select transistors SST are commonly connected by a sector select line (sector select line) SSL. 27, the sector select lines SSL11, SSL12, SSL21, and SSL22 in the plurality of sector select lines SSL are shown.

A plurality of main bit lines MBL for commonly connecting the drains of the sector select transistors SST are connected to the source of a voltage buffer transistor (the protection transistor BT). The drain of the voltage buffer transistor BT is connected to the column decoder 12 .

As the voltage buffering transistor BT, a first low-voltage transistor (low-voltage transistor) is used. As shown in Fig. 33, a first low-voltage transistor (1.8 VTr) having a rated voltage of, for example, 1.8 V is used as the voltage buffer transistor BT. The breakdown voltage of the voltage buffer transistor BT is, for example, about 3 V. [ The film thickness of the gate insulating film 79 (see FIG. 55) of the voltage buffer transistor BT is, for example, about 3 nm.

28A, in the voltage buffering transistor forming region 11 in each sector SCT, an N-type well (N-type diffusion layer) 25 formed in the semiconductor substrate 20 and an N-type well And a P-type well 74PB formed in the well 25 is formed. The voltage buffer transistor BT is formed on such a triple well.

The column decoder 12 controls the potentials of a plurality of main bit lines MBL that commonly connect the drains of the sector select transistors SST. The column decoder 12 is formed by a low-voltage circuit operating at a relatively low voltage.

The first low-voltage transistors 111N and 111P (see Fig. 55) are used for the low-voltage circuit of the column decoder 12. [ The first low-voltage transistors 111N and 111P are transistors having lower rated voltages than the second low-voltage transistors 113N and 113P described later. The film thickness of the gate insulating film 79 is thinner in the first low-voltage transistors 111N and 111P than in the second low-voltage transistors 113N and 113P. As shown in Fig. 33, a first low-voltage transistor (1.8 VTr) having a rated voltage of, for example, 1.8 V is used as the column decoder 12. [ The internal voltages of the first low-voltage transistors 111N and 111P used in the column decoder 12 are, for example, about 3V. The film thickness of the gate insulating film 79 of the first low-voltage transistors 111N and 111P used in the column decoder 12 is, for example, about 3 nm. The use of the first low-voltage transistors 111N and 111P in the column decoder 12 makes it possible to read information recorded in the memory cell transistor MT at a high speed.

The column decoder 12 is connected to a sense amplifier 13 for detecting a current flowing through the main bit line MBL.

As shown in Fig. 33, a first low-voltage transistor (1.8 VTr) having a rated voltage of, for example, 1.8 V is used for the sense amplifier 13. The internal voltages of the first low-voltage transistors 111N and 111P used in the sense amplifier 13 are, for example, about 3V. The film thickness of the gate insulating film 79 of the first low-voltage transistors 111N and 111P used in the sense amplifier 13 is, for example, about 3 nm.

A plurality of first word lines CG for commonly connecting the control gates of the memory cell transistors MT are connected to the first row decoder 14. The first row decoder 14 controls the potentials of the plurality of first word lines CG that commonly connect the control gates 34a of the memory cell transistors MT. The first row decoder 14 is formed by a high-voltage circuit. The high-voltage transistors 110N and 110P (see Figs. 28 and 54) are used for the high-voltage circuit of the first row decoder 14. [ As shown in Fig. 33, a high-voltage transistor 10 VTr having a rated voltage of, for example, 10 V is used for the first row decoder 14. [ The breakdown voltage of the high voltage transistors 110N and 110P used in the first row decoder 14 is, for example, about 12 V. [ The film thickness of the gate insulating film 76 of the high voltage transistors 110N and 110P used in the first row decoder 14 is, for example, about 16 nm.

The reason why the high voltage transistors 110N and 110P are used in the first row decoder 14 is that a high voltage must be applied to the word line WL when information is written to the memory cell transistor MT or when information is erased .

A plurality of second word lines SG connecting the select gates 30b of the select transistors ST in common are connected to the second row decoder 16. [ The second row decoder 16 controls the potentials of the plurality of second word lines SG, respectively. The second row decoder 16 is formed by a low-voltage circuit. The first low-voltage transistors 111N and 111P are used in the low-voltage circuit of the second row decoder 16. [ As shown in FIG. 33, a low voltage transistor (1.8 VTr) having a rated voltage of, for example, 1.8 V is used for the second row decoder 16. The internal voltages of the first low-voltage transistors 111N and 111P used in the second row decoder 16 are, for example, about 3V. The film thickness of the gate insulating film 79 of the first low breakdown voltage transistor 111N and 111P used in the second row decoder 16 is, for example, about 3 nm.

The source line SL for commonly connecting the sources of the memory cell transistors MT is connected to the third row decoder 18. [ The third row decoder 18 controls the potentials of the plurality of source lines SL, respectively. The third row decoder 18 is formed by a high voltage circuit. The high-voltage transistors 110N and 110P are used in the high-voltage circuit of the third row decoder 18. [ As shown in Fig. 33, the high-voltage transistor 10 VTr having a rated voltage of, for example, 10 V is used for the third row decoder 18. [ The breakdown voltage of the high voltage transistors 110N and 110P used in the third row decoder 18 is, for example, about 12V. The film thickness of the gate insulating film 76 of the high voltage transistors 110N and 110P used in the third row decoder 18 is, for example, about 16 nm.

A plurality of sector select lines SSL for commonly connecting the gates of the sector select transistors SST are connected to a first control circuit (first control section) The first control circuit 23 controls the potentials of the plurality of sector select lines SSL. The first control circuit 23 is formed by a low-voltage circuit that operates at a relatively low voltage.

The second low-voltage transistor (second low-voltage transistor) 113N, 113P (see FIG. 55) is used for the low-voltage circuit of the first control circuit 23. As shown in Fig. 33, a second low-voltage transistor 3 VTr having a rated voltage of, for example, 3 V is used for the first control circuit 23. The internal voltages of the second low-voltage transistors 113N and 113P used in the first control circuit 23 are, for example, about 6V. The film thickness of the gate insulating film 77 of the second low-voltage transistors 113N and 113P used in the first control circuit 23 is, for example, about 6 nm.

The gate BG of the voltage buffer transistor BT is electrically connected to the second control circuit 29. [ The second control circuit 29 controls the potential of the gate BG of the voltage buffering transistor. The second control circuit 29 is formed by a low-voltage circuit operating at a relatively low voltage.

The second low-voltage transistor (second low-voltage transistor) 113N, 113P is used for the low-voltage circuit of the second control circuit 29. [ As shown in Fig. 33, the second control circuit 29 uses a second low-voltage transistor 3 VTr having a rated voltage of 3 V, for example. The internal voltages of the second low-voltage transistors 113N and 113P used in the second control circuit 29 are, for example, about 6V. The film thickness of the gate insulating film 77 of the second low-voltage transistors 113N and 113P used in the second control circuit 29 is, for example, about 6 nm.

Each of the P-type wells 26 is electrically connected to the first voltage application circuit 15. The first voltage application circuit 15 controls the potential V _B1 of the P-type well 26. The first voltage applying circuit 15 is formed by a high voltage circuit. The high voltage transistors 110N and 110P are used in the high voltage circuit of the first voltage applying circuit 15. [ As shown in Fig. 33, a high voltage transistor 10 VTr having a rated voltage of, for example, 10 V is used for the first voltage application circuit 15. [ The breakdown voltage of the high voltage transistors 110N and 110P used in the first voltage application circuit 15 is, for example, about 12V. The film thickness of the gate insulating film 76 of the high voltage transistors 110N and 110P used in the first voltage applying circuit 15 is, for example, about 16 nm.

The use of the high voltage transistors 110N and 110P in the first voltage applying circuit 15 is to apply a high voltage to the P-type well 26 when erasing the information recorded in the memory cell transistor MT Because.

Each of the P-type wells 74PS is electrically connected to the second voltage application circuit 17. [ The second voltage application circuit 16 controls the potential V _B2 of the P-type well 74PS. The second voltage application circuit 16 is formed by a high voltage circuit. The high voltage transistors 110N and 110P are used in the high voltage circuit of the second voltage applying circuit 17. [ Specifically, as shown in Fig. 33, a high voltage transistor 10 VTr having a rated voltage of, for example, 10 V is used for the second voltage application circuit 17. [ The breakdown voltage of the high voltage transistors 110N and 110P used in the second voltage application circuit 17 is, for example, about 12V. The film thickness of the gate insulating film 76 of the high voltage transistors 110N and 110P used in the second voltage applying circuit 17 is, for example, about 16 nm.

The P-type well 74PB is electrically connected to the third voltage application circuit (third voltage application unit) The third voltage application circuit 19 controls the potential V _B3 of the P-type well 74PB. The third voltage applying circuit 19 is formed by a low-voltage circuit. A second low-voltage transistor is used for the low-voltage circuit of the third voltage applying circuit 19. Specifically, as shown in Fig. 33, the second low-voltage transistor (3 VTr) 113N, 113P having a rated voltage of, for example, 3 V is used for the third voltage application circuit 19. [ The internal voltages of the second low-voltage transistors 113N and 113P used in the third voltage application circuit 19 are, for example, about 6V. The film thickness of the gate insulating film 77 of the second low-voltage transistors 113N and 113P used in the third voltage applying circuit 19 is, for example, about 6 nm.

Next, the structure of the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIGS. 28 to 32. FIG. 29 is a plan view showing a memory cell array of the nonvolatile semiconductor memory device according to the present embodiment. 30 is a cross-sectional view taken along line C-C 'in Fig. 31 is a cross-sectional view taken along line D-D 'in Fig. 32 is a cross-sectional view taken along line E-E 'in Fig.

As shown in FIG. 28A, an N-type well (N-type diffusion layer) 24 is formed in the semiconductor substrate 20 in the memory cell array region 2. This N-type well 24 is formed for each sector SCT (see FIG. 27). In the N-type well 24, a P-type well 26 is formed. The P-type well 26 is electrically isolated from the semiconductor substrate 20 by the N-type well 24. [ As described above, triple wells are formed in the memory cell array region 2.

A floating gate 30a is formed on the P-type well 26 via a tunnel insulating film 28a. The floating gate 30a is electrically isolated for each device region 21 (see FIG. 32).

A control gate 34a is formed on the floating gate 30a via an insulating film 32a. The control gates 34a of the memory cell transistors MT existing in the same row are connected in common. In other words, on the floating gate 30, a first word line CG for commonly connecting the control gates 34a via the insulating film 32 is formed.

A select gate 30b of the select transistor ST is formed on the P-type well 26 in parallel with the floating gate 30a. The select gates 30b of the select transistors ST in the same row are commonly connected. In other words, on the semiconductor substrate 20, a second word line SG for commonly connecting the select gates 30b via the gate insulating film 28b is formed. The film thickness of the gate insulating film 28b of the select transistor ST is equal to the film thickness of the tunnel insulating film 28a of the memory cell transistor MT.

A polysilicon layer (conductive layer) 34b is formed on the select gate 30b via an insulating film 32b.

N type impurity diffusion layers 36a, 36b and 36c are formed in the semiconductor substrate 20 on both sides of the floating gate 30a and in the semiconductor substrate 20 on both sides of the select gate 30b. The sources of the mutually adjacent memory cell transistors MT are formed by the same impurity diffusion layer 36a. The impurity diffusion layer 36b constituting the drain of the memory cell transistor MT and the impurity diffusion layer 36b constituting the source of the selection transistor ST are formed by the same impurity diffusion layer 36b.

A sidewall insulation film 37 is formed on the sidewall portion of the laminate having the floating gate 30a and the control gate 34a.

A sidewall insulation film 37 is formed on the sidewall portion of the laminate having the select gate 30b and the polysilicon layer 34b.

On the source region 36a of the memory cell transistor MT, on the drain region 36c of the select transistor ST, on the control gate 34a and on the polysilicon layer 34b, for example, silicide of cobalt silicide Layers 38a to 38d are formed, respectively. The silicide layer 38a on the source electrode 36a functions as a source electrode. The silicide layer 38c on the drain electrode 36c functions as a drain electrode.

Thus, the memory cell transistor MT having the floating gate 30a, the control gate 34a, and the source / drain diffusion layers 36a and 36b is formed on the P-type well 26. [

A selection transistor ST having a select gate 30b and source / drain diffusion layers 36b and 36c is formed on the P-type well 26. [

Thus, the memory cell array of the nonvolatile semiconductor memory device according to the present embodiment is formed.

In the semiconductor substrate 20 in the sector select transistor formation region 7, an N type well (N type diffusion layer) 25 is formed. In the N-type well 25, a P-type well 74PS is formed. The P-type well 74PS is electrically separated from the semiconductor substrate 20 by the N-type well 25. [

A gate electrode 34d is formed on the P-type well 74PS with a gate insulating film 77 interposed therebetween. A source / drain diffusion layer 104, which is an N-type impurity diffusion layer, is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d.

In this way, the sector select transistor SST having the gate electrode 34d and the source / drain diffusion layer 104 is formed on the P-type well 74PS.

The P-type well 74PS and the P-type well 26 are electrically separated from each other by the N-type wells 24 and 25.

The source diffusion layer 104 of the sector select transistor SST and the drain diffusion layer 36c of the memory cell transistor MT are electrically connected by the local bit line LBL.

An N-type well (N-type diffusion layer) 25 is formed in the region 11 where the voltage buffering transistor is formed. In the N-type well 25, a P-type well 74PB is formed. The P-type well 74PB is electrically separated from the semiconductor substrate 20 by the N-type well 25. [

On the P-type well 74PB, a gate electrode 34d is formed with a gate insulating film 79 interposed therebetween. A source / drain diffusion layer 104, which is an N-type impurity diffusion layer, is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d.

Thus, the voltage buffer transistor BT having the gate electrode 34d and the source / drain diffusion layer 104 is formed on the P-type well 74PB.

The P-type well 74PB, the P-type well 74PS, and the P-type well 26 are electrically isolated from each other by the N-type wells 24 and 25.

The source diffusion layer 104 of the voltage buffering transistor BT and the drain diffusion layer 104 of the sector select transistor SST are electrically connected by the main bit line (wiring) MBL.

A P-type well 74P is formed in the region 27 where the column decoder is formed. A gate electrode 34d is formed on the P-type well 74P with a gate insulating film 79 interposed therebetween. A source / drain diffusion layer 104, which is an N-type impurity diffusion layer, is formed in the semiconductor substrate 20 on both sides of the gate electrode 34a.

Thus, a first low-voltage transistor (first low-voltage N-channel transistor) 111N having a gate electrode 34d and a source / drain diffusion layer 104 is formed in the region 27 where the column decoder is formed.

The source diffusion layer 104 of the first low-voltage transistor 111N used in the column decoder 12 and the drain diffusion layer 104 of the voltage buffer transistor BT are electrically connected by the main bit line (wiring) MBL. The source diffusion layer 104 of the low voltage N-channel transistor 111N of the column decoder 12 is connected to the internal circuit (low voltage circuit) of the column decoder 12. [

28 (b), an N-type well (an N-type diffusion layer) 25 is formed in the semiconductor substrate 20. The N- In the N-type well 25, a P-type well 72P is formed. The P-type well 72P is electrically separated from the semiconductor substrate 20 by the N-type well 25. [

A gate electrode 34c is formed on the P-type well 72P with a gate insulating film 76 interposed therebetween. A source / drain diffusion layer 96, which is an N-type impurity diffusion layer, is formed in the semiconductor substrate 20 on both sides of the gate electrode 34c.

Thus, the high-voltage N-channel transistor 110N having the gate electrode 34c and the source / drain diffusion layer 96 is formed on the P-type well 72P.

In the semiconductor substrate 20, an N-type well 72N is formed. On the N-type well 72N, a gate electrode 34c is formed with a gate insulating film 76 interposed therebetween. In the semiconductor substrate 20 on both sides of the gate electrode 34c, a source / drain diffusion layer 100 which is a P type impurity diffusion layer is formed.

Thus, a high breakdown voltage P-channel transistor 110P having the gate electrode 34c and the source / drain diffusion layer 100 is formed.

(Operation of nonvolatile semiconductor memory device)

Next, an operation method of the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIGS. 34 to 36. FIG. 34 is a diagram showing a reading method, a recording method, and an erasing method of the nonvolatile semiconductor memory device according to the present embodiment. In Fig. 34, F represents floating.

(Reading method)

First, a reading method of the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIG.

Here, the case of reading the information recorded in the memory cell MC surrounded by the broken line A and the memory cell MC surrounded by the broken line B in Fig. 27 will be described as an example.

When reading information recorded in the memory cell transistor MT, the potential of each part is set as follows.

That is, the potential of the sector selection line SSL11 connected to the sector select transistor SST connected to the memory cell MC to be selected is set to 1.8 V, for example. On the other hand, the potentials of the sector selection lines SSL12, SSL21, and SSL22 other than the selected sector selection line SSL11 are all set to 0V.

Further, the potential BG of the gate of the voltage buffer transistor BT is set to 1.8 V, for example.

The potentials of the main bit lines (bit lines) MBL1 and MBL2 connected to the sector select transistor SST connected to the memory cell MC to be selected are set to 0.5 V, for example.

The potentials of the first word lines CG11, CG12, CG21, and CG22 are always set to 1.8 V.

Further, the potential of the second word line SG11 connected to the memory cell MC to be selected is set to 1.8 V, for example. On the other hand, the potentials of the second word lines SG12, SG21, and SG22 other than the selected second word line SG11 are set to 0V.

The potential V _B1 of the P-type well 26 is set to 0 V in all cases. In addition, the potential V _B2 of the P-type well 74PS is set to 0V. Further, the potential V _B3 of the P-type well 74PB is set to 0V. The potentials of the source lines SL11 and SL21 are all 0V.

Also in this embodiment, since a low-voltage transistor is used as the sector select transistor SST and the voltage buffer transistor BT, a sufficiently large read current can be obtained when information recorded in the memory cell transistor MT is read. Therefore, according to the present embodiment, it is possible to determine the information recorded in the memory cell transistor MT at a high speed, and moreover, it becomes possible to read the information recorded in the memory cell transistor MT at a high speed.

(Recording method)

Next, a recording method of the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIG.

Here, the case where information is recorded in the memory cell MC surrounded by the broken line A in FIG. 27 will be described as an example.

When information is written in the memory cell transistor MT, the potential of each part is set as follows.

That is, the potential of the sector selection line SSL11 connected to the sector select transistor SST connected to the memory cell MC (memory cell A) to be selected is set to 3 V, for example. On the other hand, the potentials of the sector selection lines SSL12, SSL21, and SSL22 other than the selected sector selection line SSL11 are all 0V.

Further, the potential BG of the gate of the voltage buffer transistor BT is set to 3 V, for example.

In addition, the potential of the main bit line (bit line) MBL1 connected to the sector select transistor SST connected to the memory cell MC to be selected is set to 0 V, for example. On the other hand, the potential of the main bit line MBL2 other than the selected main bit line MBL1 is made floating.

Further, the potential of the first word line CG11 connected to the memory cell MC to be selected is set to 9 V, for example. On the other hand, the potentials of the first word lines CG12, CG21, and CG22 other than the selected first word line CG11 are set to 0V.

Further, the potential of the second word line SG11 connected to the memory cell MC to be selected is set to 2.5 V, for example. On the other hand, the potentials of the second word lines SG12, SG21, and SG22 other than the selected second word line SG11 are set to 0V.

Further, the potential of the source line SL11 connected to the memory cell MC to be selected is set to 5.5 V, for example. On the other hand, the potential of the source line SL21 other than the selected source line SL11 is made floating.

The potential V _B1 of the P-type well 26 is set to 0 V in all cases. In addition, the potential V _B2 of the P-type well 74PS is set to 0V. Further, the potential V _B3 of the P-type well 74PB is set to 0V.

When the electric potential of each part is set as described above, electrons flow between the source diffusion layer 36a and the drain diffusion layer 36b of the memory cell transistor MT and electrons are introduced into the floating gate 30a of the memory cell transistor MT. As a result, charges are accumulated in the floating gate 30a of the memory cell transistor MT, and information is written in the memory cell transistor MT.

(Erase method)

Next, an erasing method of the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIGS. 34 to 36. FIG. 35 is a time chart showing the erasing method of the nonvolatile semiconductor memory device according to the present embodiment. The broken line in Fig. 35 indicates a potential of 0V. 36 is a cross-sectional view showing the erasing method of the nonvolatile semiconductor memory device according to the present embodiment.

Erasing of information recorded in the memory cell array is performed for each sector SCT, for example. Here, a case where the information recorded in the plurality of memory cells MC existing in the first sector SCT1 is collectively erased will be described as an example.

In the present embodiment, the information recorded in the memory cell transistor MT is erased as follows.

When the information recorded in the memory cell transistor MT is erased, the potentials of the main bit lines MBL1 and MBL2 are always set to the floating state. When the information recorded in the memory cell transistor MT is erased, the potentials of the source lines SL11 and SL21 are always set to the floating state. The potential of the semiconductor substrate 20 is set to 0 V (ground). The potentials of the gates SG11, SG12, SG21, and SG22 of the selection transistor ST are always set to the floating state.

To erase the information recorded in the memory cell transistor MT, first, the potential V _B3 of the P-type well _74PB is set to the fifth potential V _ERS5 by the third voltage application circuit 19. Here, the fifth potential V _ERS5 is set to 3 V, for example.

Further, the potential BG of the gate of the voltage buffer transistor BT is set to the fourth potential V _ERS4 by the second control circuit (second control section) Here, the potential (fourth potential) V _ERS4 of the gate of the voltage buffer transistor BT is _set to 3 V, for example.

Next, the second voltage application circuit 17 sets the potential V _B2 of the P-type well 74PS to the third potential V _ERS3 . Here, the third potential V _{ERS3 is set} to, for example, _6V .

In addition, the potentials of the sector select lines SSL11, SSL12, SSL21, and _SSL22 are set to the second potential V _ERS2 . Here, the potential (second potential) V _ERS2 of the sector select lines SSL11, SSL12, SSL21, and SSL22 is _set to 5 V, for example.

Next, the first voltage application circuit 15 sets the potential VB1 of the P-type well 26 to the first potential V _ERS1 . Here, the first potential V _ERS1 is set to 9 V, for example.

Next, the potentials of the first word lines CG11 and CG12 connected to the memory cells MC in the first sector SCT1 to be erased are set to -9 V, for example. On the other hand, the potentials of the word lines CG21 and CG22 connected to the memory cells MC in the second sector SCT2 that are not to be erased are made floating, for example.

When the potential of the first word lines CG11 and CG12 is set to, for example, -9 V, charges are discharged from the floating gate 30a of the memory cell transistor MT. As a result, no charge is accumulated in the floating gate 30a of the memory cell transistor MT, and information of the memory cell transistor MT is erased.

As described above, when the information recorded in the memory cell transistor MT is erased, the potential (first potential) V _ERS1 of the P-type well 26 is set to, for example, _9V . When the potential V _ERS1 of the P-type well 26 is set to 9 V, the potential V _ERS1 'of the source diffusion layer 104 of the sector select transistor SST is about 8.5 to 8.7 V, for example. The potential V _ERS1 'of the source diffusion layer 104 is lower than the potential (first potential) V _{ERS1 of the} P-type well 26 by the diode formed by the P-type well 26 and the drain diffusion layer 36c This is because a voltage drop occurs.

When the potential (third potential) V _ERS3 of the P-type well _74PS is, for example, 6 V, the potential difference V _ERS1 '-V (V ERS1'V) between the source diffusion layer 104 of the sector select transistor SST and the P- _ERS3 ) is about 2.5 to 2.7 V, for example. Since the breakdown voltage of the sector select transistor SST is, for example, about 6 V as described above, there is no breakdown between the source diffusion layer 104 and the P-type well 74PS of the sector select transistor SST.

When the potential (second potential) V _ERS2 of the sector selection line SSL is, for example, 5 V, the potential difference (V _ERS1 '- V _ERS2 ) between the gate electrode 34d of the sector select transistor SST and the source diffusion layer 104 ) Is about 3.5 to 3.7 V, for example. The gate electrode 34d of the sector select transistor SST and the source diffusion layer 104 are connected to each other by the second low voltage transistors 113N and 113P used as the sector select transistors SST, There is no breakdown between the two.

When the potential (third potential) V _ERS3 of the P-type well _74PS is set to, for example, 6 V, the potential V _ERS3 'of the source diffusion layer 104 of the voltage buffer transistor BT is, for example, 5.5 V to 5.7 V . The potential V _ERS3 'of the source diffusion layer 104 is lower than the potential (third potential) V _{ERS3 of the} P-type well 74PS by the diode formed by the P-type well 74PS and the drain diffusion layer 104 This is because a voltage drop occurs.

When the potential (fifth potential) V _ERS5 of the P-type well _74PB is, for example, 3 V, the potential difference V _ERS3 '-V between the source diffusion layer 104 of the voltage buffering transistor BT and the P- _ERS5 ) is about 2.5 to 2.7 V, for example. Since the breakdown voltage of the first low-voltage transistors 111N and 111P used as the voltage buffer transistor BT is, for example, about 3 V as described above, the source diffusion layer 104 of the voltage buffer transistor BT and the P- There is no breakage.

Further, when the potential (fourth potential) V _ERS4 of the gate BG of the voltage buffer transistor BT is, for example, 3 V, the potential difference V _ERS3 'between the gate electrode 34d of the voltage buffer transistor BT and the source diffusion layer 104, -V _ERS4 ) is about 2.5 to 2.7 V, for example. The gate electrode 34d of the voltage buffering transistor BT and the source diffusion layer 104 are connected to each other by the second low voltage transistor 113N or 113P used as the voltage buffer transistor BT, There is no breakdown between the two.

When the potential (fifth potential) V _ERS5 of the P-type well _74PB is, for example, 3 V, the potential V _ERS5 of the source diffusion layer 104 of the first low-voltage transistor 111N used in the column decoder 12 Is about 2.5 to 2.7 V, for example. The potential V _ERS5 'of the source diffusion layer 104 of the first low-voltage transistor 111N of the column decoder 12 is lower than the potential V _ERS5 of the P-type well 74PB because the potential difference between the P-type well 74PB and the drain diffusion layer The voltage drop is caused by the diode formed by the diode 104. [

Since the breakdown voltage of the first low-voltage transistor 111N used in the column decoder 12 is, for example, about 3 V as described above, the breakdown in the first low-voltage transistor 111N of the column decoder 12 There is nothing happening.

The electric potential of each part is not limited to the above.

The potential of the P-type well 26 (the first potential) V _ERS1, and the potential of the P-type well (74PS) (third electric potential) difference between the V _ERS3, sector select transistors, each of the electric potential is smaller than the breakdown voltage of the SST V _ERS1, V _ERS3 is set.

More strictly speaking, a sector select transistor of the potential of the source diffusion layer 104 of the SST V potential of the _ERS1 'and the P-type well (74PS) V _ERS3 difference, is smaller than the breakdown voltage of a sector select transistor SST each potential V _ERS1, V _ERS3 is set.

The respective potentials V _ERS1 and V _ERS2 are set such that the difference between the potential V _ERS2 of the gate electrode 34d of the sector select transistor SST and the potential V _ERS1 of the P-type well 26 becomes smaller than the breakdown voltage of the sector select transistor SST .

More strictly speaking, the sector select transistors SST of the potential V _ERS1 of the gate electrode potential V _ERS2 and the source diffusion layer 104 of (34d) 'difference, is smaller than the breakdown voltage of a sector select transistor SST each potential V _ERS1, V _ERS2 Is set.

Further, the electric potential (third electric potential) of the P-type well (74PS) V _ERS3 and the P-type well (74PB) potential (fifth potential) V _ERS5 difference, is smaller than the voltage buffer transistor BT pressure respective potentials V _ERS3 of , V _ERS5 are set.

More precisely, the potentials V _ERS3, V (V _ERS3 ) and V (V _ERS3 ) are set _{so that} the difference between the potential V _ERS3 'of the source diffusion layer 104 of the voltage buffer transistor BT and the potential V _ERS5 of the _{P- ERS5} is set.

Further, the voltage buffer transistor electric potential of the gate electrode (34d) of the BT potential of the (fourth electric potential) V _ERS4 and the P-type well (74PS) (third electric potential) difference between the V _ERS3, is smaller than the voltage buffer transistor BT pressure, respectively The potentials V _ERS3 and V _ERS4 are set.

More precise, the voltage buffer transistor of the BT of the gate electrode (34d), the potential V _ERS4 and the source diffusion layer 104, the potential V _ERS3 of the "difference, is smaller than the voltage buffer transistor BT pressure respective potentials V _ERS3, V _ERS4 Is set.

The potential V _ERS5 of the P-type well _74PB is set so that the potential (fifth potential) V _ERS5 of the P-type well _74PB becomes smaller than the breakdown voltage of the first low-voltage transistor 111N of the column decoder 12 .

More precisely, the difference between the potential V _ERS5 'of the source diffusion layer 104 of the first low-voltage transistor 111N of the column decoder 12 and the potential of the P-type well _74P is lower than the potential of the first low voltage The fifth potential V _ERS5 is set to be smaller than the breakdown voltage of the transistor 111N.

When both the first potential V _ERS1 to the fifth potential V _ERS5 are positive, the second potential V _ERS2 is set to be lower than the first potential V _ERS1 , and the third potential V _{ERS3 is} also set to be lower than the first potential V _ERS1 . Further, the fourth potential V _ERS4 is set lower than the third potential VE _RS3 , and the fifth potential V _{ERS5 is} also set lower than the third potential V _ERS3 .

Thus, in the present embodiment, the P-type well 74PB, the P-type well 74PS and the P-type well 26 are electrically separated by the N-type wells 24 and 25. A sector select transistor SST is formed on the P-type well 74PS, and a voltage buffer transistor BT is formed on the P-type well 74PB. Therefore, in the present embodiment, it is possible to apply a bias voltage different from the voltage applied to the P-type well 26 to the P-type well 74PS when erasing the information recorded in the memory cell transistor MT. When the information recorded in the memory cell transistor MT is erased, it is possible to apply a bias voltage different from the voltage applied to the P-type well 74PS to the P-type well 74PB. When the information recorded in the memory cell transistor MT is erased, a bias is applied to the P-type well 74PS so that the potential difference between the P-type well 26 and the P-type well 74PS becomes smaller than the breakdown voltage of the sector select transistor SST Voltage is applied. A bias voltage is applied to the gate electrode 34d of the sector select transistor SST so that the potential difference between the gate electrode 34d of the sector select transistor SST and the source diffusion layer 104 becomes smaller than the breakdown voltage of the sector select transistor SST. A bias voltage is applied to the P-type well 74PB so that the potential difference between the P-type well 74PS and the P-type well 74PB becomes smaller than the breakdown voltage of the voltage buffer transistor BT. The bias voltage is applied to the P-type well 74PB so that the voltage applied to the first low-voltage transistor 111N in the column decoder 12 becomes smaller than the breakdown voltage of the first low-voltage transistor 111N. A bias voltage is applied to the gate electrode 34d of the voltage buffer transistor BT so that the potential difference between the gate electrode 34d of the voltage buffer transistor BT and the source diffusion layer 104 becomes smaller than the breakdown voltage of the voltage buffer transistor BT. Therefore, according to the present embodiment, since the voltage buffer transistor BT is provided, the voltage applied to the sector select transistor SST at the time of erasing can be suppressed to be small, and the destruction of the sector select transistor SST can be prevented have. In addition, since the voltage buffer transistor BT is provided, the first low-voltage transistor 112N having a very low withstand voltage can be used as the column decoder 12. According to the present embodiment, it is possible to further increase the speed and reduce the power consumption.

In this example, the case where the potential V _ERS2 of the sector select line SSL is _set to, for example, 5 V at the time of erasing the information recorded in the memory cell transistor MT has been described as an example, but the potential of the sector select line SSL may be floating . It is possible to prevent the sector select transistor SST from being broken at the time of erasing even when the potential of the sector select line SSL is made floating when the information recorded in the memory cell transistor MT is erased.

(Manufacturing Method of Nonvolatile Semiconductor Memory Device)

Next, a method of manufacturing the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIGS. 37 to 55. FIG. 37 to 55 are process cross-sectional views showing a method of manufacturing the nonvolatile semiconductor memory device according to the present embodiment.

Figures 37 (a), 39 (a), 41 (a), 43 (a), 45 (a), 47 (a), 49 51 (a) and FIG. 53 show the memory cell array region 2. Figures 37 (a), 39 (a), 41 (a), 43 (a), 45 (a), 47 (a), 49 The drawings on the left side of FIG. 51 (a) and FIG. 53 correspond to the EE 'section of FIG. Figures 37 (a), 39 (a), 41 (a), 43 (a), 45 (a), 47 (a), 49 The drawings on the right side of FIG. 51 (a) and FIG. 53 correspond to the CC 'section of FIG.

37, (b), 38, 39 (b), 40, 41 (b), 42, 43 (b), 44, 45 (b) Figures 47 (b), 48, 49 (b), 50, 51 (b), 52, 53, 54, and 55 show the peripheral circuit region 4.

Figures 37 (b), 39 (b), 41 (b), 43 (b), 45 (b), 47 (b), 49 51 (b) and 54 show the region 6 where the high-voltage transistor is formed. The region 6 on the left side of the region 6 where the high breakdown voltage transistor is formed represents the region 6N where the high breakdown voltage N-channel transistor is formed. The right side of the region 6N where the high-breakdown-voltage N-channel transistor is formed represents the region 6P where the high-breakdown-voltage P-channel transistor is formed.

The right side of the region 6P where the high breakdown voltage P-channel transistor is formed shows the region 7 where the sector select transistor is formed.

Figures 37 (b), 39 (b), 41 (b), 43 (b), 45 (b), 47 (b), 49 51 (b) and 54 show the region 8 where the first low-voltage transistor is formed. The left side of the region of the region 8 where the first low-voltage transistor is formed shows a region 8N in which the first low-voltage N-channel transistor is formed. The right side of the region 8 where the low-voltage transistor is formed represents the region 8P in which the first low-voltage P-channel transistor is formed.

The left side of the drawing in Figs. 38, 40, 42, 44, 46, 48, 50, 52 and 55 shows the region 9 where the second low- . The left side of the region of the region 9 where the second low-voltage transistor is formed represents a region 9N where the second low-voltage N-channel transistor is formed. The right side of the region 9 in which the second low-voltage transistor is formed represents the region 9P in which the second low-voltage P-channel transistor is formed.

First, the process from the step of preparing the semiconductor substrate 20 to the step of growing the sacrificial oxide film 69 is the same as the method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment described above with reference to FIGS. 10 to 12 The description will be omitted.

Next, as shown in FIG. 37, an N type buried diffusion layer 24 is formed by deeply implanting N type dopant impurities into the memory cell array region 2. Next, as shown in FIG. An N-type buried diffusion layer 25 is also formed by implanting an N-type dopant impurity deep into the region 6N where the high-breakdown-voltage N-channel transistor is formed. Further, an N type buried diffusion layer 25 is formed by deeply implanting an N type dopant impurity into the region 7 where the sector select transistor is formed. 38, an N type buried diffusion layer 25 is formed by deeply implanting an N type dopant impurity into the region 11 where the voltage buffering transistor is formed. A P-type well 26 is formed by implanting a P-type dopant impurity into the memory cell array region 2 shallower than the buried diffusion layer 24. The P-type well 72P is formed by implanting a P-type dopant impurity shallower than the buried diffusion layer 25 in the region 6N where the high-voltage N-channel transistor is formed.

Next, an N-type diffusion layer 70 is formed in a frame shape in a region 6N where a high-breakdown-voltage N-channel transistor is formed. This frame-type diffusion layer 70 is formed so as to extend from the surface of the semiconductor substrate 20 to the periphery of the buried diffusion layer 25. [ The P type well 72P is surrounded by the buried diffusion layer 25 and the diffusion layer 70. [

The N-type diffusion layer 70 is also formed in the frame 7 in the region 7 where the sector select transistor is formed. This frame-type diffusion layer 70 is formed so as to extend from the surface of the semiconductor substrate 20 to the periphery of the buried diffusion layer 25. [

Also in the region 11 where the voltage buffering transistor is formed, the N-type diffusion layer 70 is formed in a frame shape. This frame-type diffusion layer 70 is formed so as to extend from the surface of the semiconductor substrate 20 to the periphery of the buried diffusion layer 25. [

Although not shown, the P-type well 26 of the memory cell array region 2 is also surrounded by the buried diffusion layer 24 and the frame-shaped diffusion layer 70.

Next, an N-type well 72N is formed by introducing an N-type dopant impurity into the region 6P where the high-breakdown-voltage P-channel transistor is formed.

Next, channel doping is performed on the memory cell array region 2 (not shown).

Next, channel doping is performed on the region 6N where the high-breakdown-voltage N-channel transistor is formed and the region 6P where the high breakdown voltage P-channel transistor is formed (not shown).

Next, the sacrificial oxide film 69 (see FIG. 13) existing on the surface of the semiconductor substrate 20 is etched away.

Next, a tunnel insulating film 28 having a thickness of 10 nm is formed on the entire surface by thermal oxidation.

Next, a polysilicon film 30 having a film thickness of 90 nm is formed on the entire surface by, for example, CVD. As the polysilicon film 30, a polysilicon film doped with an impurity is formed.

Next, the polysilicon film 30 in the memory cell array region 2 is patterned, and the polysilicon film 30 existing in the peripheral circuit region 4 is etched away.

Next, an insulating film (ONO film) 32 formed by sequentially laminating a silicon oxide film, a silicon nitride film, and a silicon oxide film on the entire surface is formed. This insulating film 32 is for insulating the floating gate 30a and the control gate 34a.

Next, the P-type well 74P is formed by introducing a P-type dopant impurity into the region 8N where the first low-voltage N-channel transistor is formed. A P-type well 74PS is formed by introducing a P-type dopant impurity into the region 7 where the sector select transistor is formed. A P-type well 74PB is formed by introducing a P-type dopant impurity into the region 11 where the voltage buffering transistor is formed. Further, the P-type well 74P is formed by introducing the P-type dopant impurity into the region 9N where the second low-voltage N-channel transistor is formed.

Next, an N-type well 74N is formed by introducing an N-type dopant impurity into the region 8P in which the first low-voltage P-channel transistor is formed. An N-type well 74N is formed by introducing an N-type dopant impurity into the region 9P in which the second low-voltage P-channel transistor is formed.

Next, channel doping is performed in the region 8N in which the first low-voltage N-channel transistor is formed and in the region 8P in which the first low-voltage P-channel transistor is formed. Channel doping is performed on the region 7 where the sector select transistor is formed, the region 9N where the second low-voltage N-channel transistor is formed, and the region 9P where the second low-voltage P-channel transistor is formed ).

Next, the insulating film (ONO film) 32 present in the peripheral circuit region 4 is removed by etching.

Next, a gate insulating film 76 having a film thickness of, for example, 11 nm is formed on the entire surface by thermal oxidation (see FIGS. 37 and 38).

Next, by the wet etching, the region 7 where the sector select transistor is formed, the region 8 where the first low-voltage transistor is formed, the region 9 where the second low-voltage transistor is formed, and the region where the voltage buffering transistor is formed The gate insulating film 76 of the gate electrode 11 is removed.

Next, a gate insulating film 77 having a film thickness of, for example, 4 nm is formed on the entire surface by thermal oxidation. Thus, in the sector select transistor formation region 7, the region 8 where the first low-voltage transistor is formed, the region 9 where the second low-voltage transistor is formed, and the voltage buffering transistor formation region 11, A gate insulating film 77 having a film thickness of 4 nm is formed. On the other hand, in the region 6 in which the high breakdown voltage transistor is formed, the film thickness of the gate insulating film 76 is about 14 nm, for example (see FIGS. 39 and 40).

Next, the region 8 where the first low-voltage transistor is formed and the gate insulating film 76 of the region 11 where the voltage buffering transistor is formed are removed by wet etching.

Next, on the entire surface, a gate insulating film 79 having a film thickness of 3 nm, for example, is formed by thermal oxidation. Thus, in the region 8 where the first low-voltage transistor is formed and the region 11 where the voltage buffering transistor is formed, for example, a gate insulating film 79 with a film thickness of 3 nm is formed. In the region 9 where the second low-voltage transistor is formed and the region 7 where the sector select transistor is formed, the film thickness of the gate insulating film 77 is about 6 nm, for example. In the region 6 in which the high breakdown voltage transistor is formed, the film thickness of the gate insulating film 76 is about 16 nm, for example (see FIGS. 41 and 42).

Next, a polysilicon film 34 having a thickness of, for example, 180 nm is formed on the entire surface by, for example, CVD.

Next, an antireflection film 80 is formed on the entire surface (see Figs. 43 and 44).

45 and 46, the antireflection film 80, the polysilicon film 34, the insulating film 32, and the polysilicon film 30 are dry-etched by using the photolithography technique. As a result, a laminate having a floating gate 30a made of polysilicon and a control gate 34a made of polysilicon is formed in the memory cell array region 2. Further, a laminate having a select gate 30b made of polysilicon and a polysilicon film 34b is formed in the memory cell array region 2. [

Next, the polysilicon film 34b is etched away (not shown) in the region where the wiring (first metal wiring) 46 and the select gate 30b should be connected.

Next, a silicon oxide film (not shown) is formed on the sidewall portion of the floating gate 30a, the sidewall portion of the control gate 34a, the sidewall portion of the select gate 30b, and the sidewall portion of the polysilicon film 34b by thermal oxidation. Is formed.

Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

Next, an opening (not shown) exposing the memory cell array region 2 is formed in the photoresist film by photolithography.

Next, an N-type dopant impurity is introduced into the semiconductor substrate 20 using the photoresist film as a mask. The impurity diffusion layers 36a to 36c are formed in the semiconductor substrate 20 on both sides of the floating gate 30a and in the semiconductor substrate 20 on both sides of the select gate 30b. Thereafter, the photoresist film is peeled off.

Thus, the memory cell transistor MT having the floating gate 30a, the control gate 34a, and the source / drain diffusion layers 36a and 36b is formed. Further, the selection transistor ST having the control gate 30b and the source / drain diffusion layers 36b and 36c is formed.

A silicon oxide film 82 is formed on the sidewall portion of the floating gate 30a, the sidewall portion of the control gate 34b, the sidewall portion of the select gate 30b, and the sidewall portion of the polysilicon film 34b by thermal oxidation, .

Next, a silicon nitride film 84 having a thickness of 50 nm is formed by, e.g., CVD.

Next, the silicon nitride film 84 is anisotropically etched by dry etching to form a sidewall insulation film 84 made of a silicon nitride film. At this time, the antireflection film 80 is etched away.

Next, the polysilicon film 34 in the peripheral circuit region 4 is patterned by photolithography. The gate electrode 34c of the high breakdown voltage transistors 110N and 110P made of the polysilicon film 34 is formed in the region 6 where the high breakdown voltage transistor is formed. The gate electrode 34d of the sector select transistor SST made of polysilicon 34 is formed in the region 7 where the sector select transistor is formed. The gate electrode 34d of the first low-voltage transistor 111N, 111P made of polysilicon 34 is formed in the region 8 where the first low-voltage transistor is formed. The gate electrode 34d of the second low-voltage transistor 113N, 113P made of polysilicon 34 is formed in the region 9 where the second low-voltage transistor is formed. A gate electrode 34d of the voltage buffer transistor BT made of polysilicon 34 is formed in the region 11 where the voltage buffering transistor is formed.

Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

Next, an opening (not shown) exposing the region 6N in which the high-voltage N-channel transistor is formed is formed in the photoresist film by photolithography.

Next, an N-type dopant impurity is introduced into the semiconductor substrate 20 using the photoresist film as a mask. Thus, the N type lightly doped diffusion layer 86 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34c of the high-voltage N-channel transistor 110N. Thereafter, the photoresist film is peeled off.

Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

Next, an opening (not shown) exposing the region 6P in which the high voltage P-channel transistor is formed is formed in the photoresist film by photolithography.

Next, using the photoresist film as a mask, a P-type dopant impurity is introduced into the semiconductor substrate 20. Thus, a P-type low-concentration diffusion layer 88 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34c of the high-breakdown-voltage P-channel transistor 110P. Thereafter, the photoresist film is peeled off.

Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

Next, an opening (not shown) exposing the region 9N in which the second low-voltage transistor is formed is formed in the photoresist film by photolithography. At this time, an opening (not shown) exposing the region 7 where the sector select transistor is formed is also formed in the photoresist film.

Next, an N-type dopant impurity is introduced into the semiconductor substrate 20 using the photoresist film as a mask. Thus, an N-type low-concentration diffusion layer 90a is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d of the second low-voltage N-channel transistor 113N. An N-type low concentration diffusion layer 90a is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d of the sector select transistor SST. Thereafter, the photoresist film is peeled off.

Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

Next, an opening (not shown) exposing the region 9P in which the second low-voltage P-channel transistor is formed is formed in the photoresist film by photolithography.

Next, using the photoresist film as a mask, a P-type dopant impurity is introduced into the semiconductor substrate 20. Thus, a P-type lightly doped diffusion layer 92a is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d of the second low-voltage P-channel transistor 113P. Thereafter, the photoresist film is peeled off.

Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

Next, an opening (not shown) exposing the region 8N in which the first low-voltage N-channel transistor is formed is formed in the photoresist film by photolithography. At this time, an opening (not shown) exposing the region 11 where the voltage buffering transistor is formed is also formed in the photoresist film.

Next, an N-type dopant impurity is introduced into the semiconductor substrate 20 using the photoresist film as a mask. Thus, an N-type low-concentration diffusion layer 90 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d of the first low-voltage N-channel transistor 111N. An N type lightly doped diffusion layer 90 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d of the voltage buffer transistor BT. Thereafter, the photoresist film is peeled off.

Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

Next, an opening (not shown) exposing the region 8P in which the first low-voltage P-channel transistor is formed is formed in the photoresist film by photolithography.

Next, using the photoresist film as a mask, a P-type dopant impurity is introduced into the semiconductor substrate 20. Thus, a P-type lightly doped diffusion layer 92 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d of the first low-voltage P-channel transistor 111P. Thereafter, the photoresist film is peeled off (see Figs. 47 and 48).

Next, a silicon oxide film 93 having a thickness of 100 nm is formed by, e.g., CVD.

Next, the silicon oxide film 93 is anisotropically etched by dry etching. Thus, a sidewall insulation film 93 made of a silicon oxide film is formed on the sidewall portion of the laminate having the floating gate 30a and the control gate 34a (see Figs. 49 and 50). A sidewall insulation film 93 made of a silicon oxide film is formed on the sidewall portion of the laminate having the select gate 30b and the polysilicon film 34b. A sidewall insulation film 93 made of a silicon oxide film is formed on the sidewall portions of the gate electrodes 34c and 34d.

Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

Next, an opening (not shown) exposing the region 6N in which the high-voltage N-channel transistor is formed is formed in the photoresist film by photolithography.

Next, an N-type dopant impurity is introduced into the semiconductor substrate 20 using the photoresist film as a mask. Thus, an N-type high-concentration diffusion layer 94 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34c of the high-breakdown-voltage N-channel transistor. The N-type source / drain diffusion layer 96 of the LDD structure is formed by the N-type low-concentration diffusion layer 86 and the N-type high-concentration diffusion layer 94. Thus, the high-breakdown-voltage N-channel transistor 110N having the gate electrode 34c and the source / drain diffusion layer 96 is formed. The high voltage N-channel transistor 110N includes a first row decoder 14, a third row decoder 18, a first voltage applying circuit 15, a second voltage applying circuit 17, a third voltage applying circuit 19 ) And the like.

Thereafter, the photoresist film is peeled off.

Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

Next, an opening (not shown) exposing the region 6P in which the high voltage P-channel transistor is formed is formed in the photoresist film by photolithography.

Next, using the photoresist film as a mask, a P-type dopant impurity is introduced into the semiconductor substrate 20. Thus, a P-type high-concentration diffusion layer 98 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34c of the high-breakdown-voltage P-channel transistor 110P. The P-type source / drain diffusion layer 100 of the LDD structure is formed by the P-type low-concentration diffusion layer 88 and the P-type high-concentration diffusion layer 98. Thus, a high breakdown voltage P-channel transistor 110P having the gate electrode 34c and the source / drain diffusion layer 100 is formed. The high voltage p-channel transistor 110P includes a first row decoder 14, a third row decoder 18, a first voltage applying circuit 15, a second voltage applying circuit 17, a third voltage applying circuit 19 ) And the like. Thereafter, the photoresist film is peeled off.

Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

Next, an opening (not shown) exposing the region 8N where the first low-voltage N-channel transistor is formed and an opening (not shown) exposing the second low-voltage N-channel transistor 9N are formed by photolithography, ) Is formed on the photoresist film. At this time, an opening (not shown) exposing the region 7 where the sector select transistor is formed and an opening (not shown) exposing the region 11 where the voltage buffer transistor is formed are formed in the photoresist film.

Next, an N-type dopant impurity is introduced into the semiconductor substrate 20 using the photoresist film as a mask. Thus, an N-type high-concentration diffusion layer 102 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d of the first low-voltage N-channel transistor 111N. An N-type high-concentration diffusion layer 102 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d of the second low-voltage N-channel transistor 113N. An N-type high concentration diffusion layer 102 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d of the sector select transistor SST. In addition, an N-type high-concentration diffusion layer 102 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d of the voltage buffer transistor BT. An N-type source / drain diffusion layer 104 of an LDD structure is formed by the N-type low-concentration diffusion layer 90 and the N-type high-concentration diffusion layer 102.

Thus, the first low-voltage N-channel transistor 111N having the gate electrode 34d and the source / drain diffusion layer 104 is formed. Further, a second low-voltage N-channel transistor 113N having the gate electrode 34d and the source / drain diffusion layer 104 is formed. In addition, the sector select transistor SST having the gate electrode 34d and the source / drain diffusion layer 104 is formed. Further, a voltage buffer transistor BT having a gate electrode 34d and a source / drain diffusion layer 104 is formed.

The first low-voltage N-channel transistor 111N is used in a low-voltage circuit such as a column decoder 12, a second row decoder 16, a sense amplifier 13, and the like. The second low-voltage N-channel transistor 113N is used for a low-voltage circuit such as the first control circuit 23, the second control circuit 29, and the like.

Thereafter, the photoresist film is peeled off.

Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

Next, an opening (not shown) for exposing a region 8P in which the first low-voltage P-channel transistor is formed and an opening 9P for exposing the region 9P in which the second low-voltage P-channel transistor is formed are exposed by photolithography, (Not shown) is formed on the photoresist film.

Next, using the photoresist film as a mask, a P-type dopant impurity is introduced into the semiconductor substrate 20. Thus, a P-type high-concentration diffusion layer 106 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d of the first low-voltage P-channel transistor 111P. A P-type high-concentration diffusion layer 106 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d of the second low-voltage P-channel transistor 113P. The P-type source / drain diffusion layer 108 of the LDD structure is formed by the P-type low-concentration diffusion layer 92 and the P-type high-concentration diffusion layer 106.

Thus, the first low-voltage P-channel transistor 111P having the gate electrode 34d and the source / drain diffusion layer 108 is formed. Further, a second low-voltage P-channel transistor 113P having a gate electrode 34d and a source / drain diffusion layer 108 is formed. The first low-voltage P-channel transistor 111P is used in a low-voltage circuit such as a column decoder 12, a second row decoder 16, a sense amplifier 13, and the like. The second low-voltage P-channel transistor 113P is used for a low-voltage circuit such as the first control circuit 23, the second control circuit 29, and the like.

Thereafter, the photoresist film is peeled off (see Figs. 49 and 50).

Next, a 10-nm-thick cobalt film is formed on the entire surface by, for example, sputtering.

Next, cobalt silicide films 38a to 38f are formed in the same manner as in the nonvolatile semiconductor memory device according to the first embodiment described above with reference to FIG. Thereafter, the unreacted cobalt film is removed by etching.

The cobalt silicide film 38b formed on the drain diffusion layer 36c of the selection transistor ST functions as a drain electrode. The cobalt silicide film 38a formed on the source diffusion layer 36a of the memory cell transistor MT functions as a source electrode.

The cobalt silicide film 38e formed on the source / drain diffusion layers 96 and 100 of the high-voltage transistors 110N and 110P functions as a source / drain electrode. The cobalt silicide film 38e formed on the source / drain diffusion layers 104 and 108 of the first low-voltage transistors 111N and 111P and the second low-voltage transistors 113N and 113P functions as a source / drain electrode. In addition, the cobalt silicide film 38e formed on the source / drain diffusion layer 104 of the sector select transistor SST and the voltage buffering transistor BT functions as a source / drain electrode (see FIGS. 51 and 52).

Next, as shown in FIGS. 53 and 54, a silicon nitride film 114 having a thickness of 100 nm is formed on the entire surface by, for example, CVD. The silicon nitride film 114 functions as an etching stopper.

Next, a silicon oxide film 116 having a thickness of 1.6 占 퐉 is formed on the entire surface by a CVD method. Thus, an interlayer insulating film 40 composed of the silicon nitride film 114 and the silicon oxide film 116 is formed.

Next, the surface of the interlayer insulating film 40 is planarized by a CMP method.

Next, a contact hole 42 reaching the source / drain electrodes 38a and 38c, a contact hole 42 reaching the cobalt silicide film 38e, and a contact reaching the cobalt silicide film 38f are formed by photolithography, Holes 42 are formed.

Next, a barrier layer (not shown) made of a Ti film and a TiN film is formed on the entire surface by sputtering.

Next, a tungsten film 44 having a film thickness of 300 nm is formed on the entire surface by, for example, CVD.

Next, the tungsten film 44 and the barrier film are polished by CMP until the surface of the interlayer insulating film 40 is exposed. In this manner, a conductor plug 44 made of, for example, tungsten is embedded in the contact hole 42.

Next, a laminated film 46 in which a Ti film, a TiN film, an Al film, a Ti film, and a TiN film are sequentially laminated is formed on the interlayer insulating film 40 in which the conductor plug 44 is buried by, for example, sputtering .

Next, the laminated film 46 is patterned by photolithography. Thus, a wiring (first metal wiring layer) 46 made of a laminated film is formed (see FIGS. 53 to 55).

24 and 25, a multilayer wiring structure is formed in the same manner as in the above-described manufacturing method of the nonvolatile semiconductor memory device.

Thus, the nonvolatile semiconductor memory device according to the present embodiment is manufactured.

[Third embodiment]

A nonvolatile semiconductor memory device, a reading method, a recording method, an erasing method, and a method for manufacturing the nonvolatile semiconductor memory device according to the third embodiment will be explained with reference to FIGS. 56 to 60. FIG. Constituent elements that are the same as those of the nonvolatile semiconductor memory device or the like according to the first or second embodiment shown in Figs. 1 to 55 are denoted by the same reference numerals and their description is omitted or simplified.

(Nonvolatile semiconductor memory device)

First, the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIGS. 56 to 58. FIG. 56 is a circuit diagram showing a nonvolatile semiconductor memory device according to the present embodiment. 57 is a cross-sectional view showing a nonvolatile semiconductor memory device according to the present embodiment.

In the nonvolatile semiconductor memory device according to the present embodiment, the region 11 in which the voltage buffering transistor is formed has a triple well structure.

As shown in FIG. 57, a P-type well 74PB is formed in the semiconductor substrate 20 in the region 11 where the voltage buffering transistor is formed. In the present embodiment, an N type well (N type diffusion layer) 25 (see FIG. 36) is not formed in the region 11 where the voltage buffering transistor is formed. That is, the region 11 where the voltage buffering transistor is formed is not a triple well structure.

A voltage buffer transistor BT is formed on the P-type well 74PB. That is, on the P-type well 74PB, a gate electrode 34d is formed with a gate insulating film 79 interposed therebetween. A source / drain diffusion layer 104 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d. Thus, the voltage buffer transistor BT having the gate electrode 34d and the source / drain diffusion layer 104 is formed on the P-type well 74PB.

56, the third voltage applying circuit 19 (see FIG. 27) for applying a voltage to the P-type well 74PB is not provided in this embodiment.

Fig. 58 is a diagram showing the type of the transistor used in each component, the breakdown voltage of the transistor, and the film thickness of the gate insulating film of the transistor.

As shown in FIG. 58, a low-voltage transistor 3 VTr having a rated voltage of, for example, 3 V is used as the sector select transistor SST. The breakdown voltage between the source / drain diffusion layer 104 of the sector select transistor SST and the P-type well 74PS is, for example, about 6V. The breakdown voltage between the gate electrode 34d of the sector select transistor SST and the source / drain diffusion layer 104 is, for example, about 6V. The film thickness of the gate insulating film 77 of the sector select transistor SST is, for example, about 6 nm.

As the voltage buffer transistor BT, a low voltage transistor (1.8 VTr) having a rated voltage of, for example, 1.8 V is used. The breakdown voltage between the source / drain diffusion layer 104 and the P-type well 74PB of the voltage buffering transistor BT is, for example, about 6V. On the other hand, the breakdown voltage between the gate electrode 34d of the voltage buffering transistor BT and the source / drain diffusion layer 104 is, for example, about 3V. That is, the breakdown voltage between the source / drain diffusion layer 104 and the P-type well 74PB of the voltage buffering transistor BT is higher than the breakdown voltage between the gate electrode 34d and the source / drain diffusion layer 104. [ The thickness of the gate insulating film 79 of the voltage buffer transistor BT is, for example, about 3 nm.

A first low-voltage transistor (1.8 VTr) 111N, 111P having a rated voltage of, for example, 1.8 V is used as the low-voltage circuit of the column decoder 12. [ The breakdown voltage between the source diffusion layer 104 and the P-type well 74P of the first low-voltage transistors 111N and 111P (see FIG. 54) used in the column decoder 12 is, for example, about 6V. On the other hand, the withstand voltage between the gate electrode 34d of the first low-voltage transistor 111N, 111P used in the column decoder 12 and the source diffusion layer 104 is, for example, about 3V. That is, the breakdown voltage between the source / drain diffusion layer 104 and the P-type well 74P of the first low-voltage transistors 111N and 111P used in the column decoder 12 is set so that the gate electrode 34d and the source / (104). The film thickness of the gate insulating film 79 of the first low-voltage transistors 111N and 111P used in the column decoder 12 is, for example, about 3 nm.

The sense amplifier 13 uses a first low-voltage transistor (1.8 VTr) 111N and 111P having a rated voltage of 1.8 V, for example. The breakdown voltage between the source / drain diffusion layer 104 and the P-type well 74P of the first low-voltage transistors 111N and 111P used in the sense amplifier 13 is, for example, about 6V. On the other hand, the breakdown voltage between the gate electrode 34d of the first low-voltage transistors 111N and 111P used in the sense amplifier 13 and the source / drain diffusion layer 104 is, for example, about 3V. That is, the breakdown voltage between the source / drain diffusion layer 104 and the P-type well 74P of the first low-voltage transistors 111N and 111P used in the sense amplifier 13 is lower than the breakdown voltage between the gate electrode 34d and the source / (104). The film thickness of the gate insulating film 79 of the first low-voltage transistors 111N and 111P used in the column decoder 12 is, for example, about 3 nm.

The first high-voltage transistor 10 VTr (110 VT) 110 N and 111 P having a rated voltage of, for example, 10 V is used as the first row decoder 14. The breakdown voltage of the high voltage transistors 110N and 110P used in the first row decoder 14 is, for example, about 12 V. [ The film thickness of the gate insulating film 76 of the high voltage transistors 110N and 110P used in the first row decoder 14 is, for example, about 16 nm.

The second row decoder 16 uses a first low-voltage transistor (1.8 VTr) 111N and 111P having a rated voltage of 1.8 V, for example. The breakdown voltage between the source / drain diffusion layer 104 and the P-type well 74P of the first low-voltage transistors 111N and 111P used in the second row decoder 16 is, for example, about 6V. On the other hand, the breakdown voltage between the gate electrode 34d of the first low-voltage transistor 111N and 111P used in the second row decoder 16 and the source / drain diffusion layer 104 is, for example, about 3V. That is, the breakdown voltage between the source / drain diffusion layer 104 and the P-type well 74P of the first low-voltage transistors 111N and 111P used in the second row decoder 16 is set so that the gate electrode 34d and the source / Drain diffusion layer 104. [0064] The film thickness of the gate insulating film 79 of the first low-voltage transistors 111N and 111P used in the second row decoder 16 is, for example, about 3 nm.

The third high-voltage transistor 10 VTr (110 VT) 110 N, 110 P having a rated voltage of, for example, 10 V is used as the third row decoder 18. The breakdown voltage of the high voltage transistors 110N and 110P used in the third row decoder 18 is, for example, about 12V. The film thickness of the gate insulating film 76 of the high voltage transistors 110N and 110P used in the third row decoder 18 is, for example, about 16 nm.

As the low-voltage circuit of the first control circuit 23, the second low-voltage transistor (3 VTr) 113N, 113P having a rated voltage of, for example, 3 V is used. The internal voltages of the second low-voltage transistors 113N and 113P used in the first control circuit 23 are, for example, about 6V. The film thickness of the gate insulating film 77 of the second low-voltage transistors 113N and 113P used in the first control circuit 23 is, for example, about 6 nm.

The second low-voltage transistor (3 VTr) 113N, 113P having a rated voltage of, for example, 3 V is used as the second control circuit 29. [ The internal voltages of the second low-voltage transistors 113N and 113P used in the second control circuit 29 are, for example, about 6V. The film thickness of the gate insulating film 77 of the second low-voltage transistors 113N and 113P used in the second control circuit 29 is, for example, about 6 nm.

The first voltage applying circuit 15 uses the high voltage transistor 10 VTr 110N and 110P having a rated voltage of, for example, 10V. The breakdown voltage of the high voltage transistors 110N and 110P used in the first voltage application circuit 15 is, for example, about 12V. The film thickness of the gate insulating film 76 of the high voltage transistors 110N and 110P used in the first voltage applying circuit 15 is, for example, about 16 nm.

The second voltage application circuit 17 uses high voltage transistors (10 VTr) 110N and 110P having a rated voltage of, for example, 10V. The breakdown voltage of the high voltage transistors 110N and 110P used in the second voltage application circuit 17 is, for example, about 12V. The film thickness of the gate insulating film 76 of the high voltage transistors 110N and 110P used in the second voltage applying circuit 17 is, for example, about 16 nm.

In this embodiment, since the breakdown voltage between the P-type well 74PB and the source / drain diffusion layer 104 of the voltage buffer transistor BT is relatively high, when the information recorded in the memory cell transistor MT is erased, the P-type well 74PB It is not necessary to apply a bias voltage to the gate electrode. When the information recorded in the memory cell transistor MT is erased, a bias voltage is applied to the gate electrode 34d of the voltage buffer transistor BT to prevent breakage of the voltage buffer transistor BT. As in the present embodiment, the region 11 in which the voltage buffering transistor is formed may not be a triple well structure.

(Operation of nonvolatile semiconductor memory device)

Next, a method of operating the nonvolatile semiconductor memory device according to the present modification will be described with reference to FIGS. 59 and 60. FIG. 59 is a diagram showing a reading method, a recording method and an erasing method of the nonvolatile semiconductor memory device according to the present embodiment. In Fig. 59, F represents floating.

(Reading method)

First, a reading method of the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIG.

Here, the case of reading the information recorded in the memory cell MC surrounded by the broken line A and the memory cell MC surrounded by the broken line B in Fig. 56 will be described as an example.

When reading information recorded in the memory cell transistor MT, the potential of each part is set as follows.

That is, the potential of the sector selection line SSL11 connected to the sector select transistor SST connected to the memory cell MC to be selected is set to 1.8 V, for example. On the other hand, the potentials of the sector selection lines SSL12, SSL21, and SSL22 other than the selected sector selection line SSL11 are all 0V.

Further, the potential BG of the gate of the voltage buffer transistor BT is set to 1.8 V, for example.

The potentials of the main bit lines (bit lines) MBL1 and MBL2 connected to the sector select transistor SST connected to the memory cell MC to be selected are set to 0.5 V, for example.

The potentials of the first word lines CG11, CG12, CG21, and CG22 are always set to 1.8 V.

Further, the potential of the second word line SG11 connected to the memory cell MC to be selected is set to 1.8 V, for example. On the other hand, the potentials of the second word lines SG12, SG21, and SG22 other than the selected second word line SG11 are set to 0V.

The potential V _B1 of the P-type well 26 is set to 0 V in all cases. In addition, the potential V _B2 of the P-type well 74PS is set to 0V. The potentials of the source lines SL11 and SL21 are all 0V.

Also in this embodiment, since a low-voltage transistor is used as the sector select transistor SST and the voltage buffer transistor BT, a sufficiently large read current can be obtained when information recorded in the memory cell transistor MT is read. Therefore, according to the present embodiment, it is possible to determine the information recorded in the memory cell transistor MT at a high speed, and moreover, it becomes possible to read the information recorded in the memory cell transistor MT at a high speed.

(Recording method)

Next, a recording method of the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIG.

Here, a case where information is recorded in the memory cell MC surrounded by the broken line A in Fig. 56 will be described as an example.

When information is recorded in the memory cell transistor MT, the potential of each part is set as follows.

That is, the potential of the sector selection line SSL11 connected to the sector select transistor SST connected to the memory cell MC (memory cell A) to be selected is set to 3 V, for example. On the other hand, the potentials of the sector selection lines SSL12, SSL21, and SSL22 other than the selected sector selection line SSL11 are all 0V.

Further, the potential BG of the gate of the voltage buffer transistor BT is set to 3 V, for example.

In addition, the potential of the main bit line (bit line) MBL1 connected to the sector select transistor SST connected to the memory cell MC to be selected is set to 0 V, for example. On the other hand, the potential of the main bit line MBL2 other than the selected main bit line MBL1 is made floating.

Further, the potential of the first word line CG11 connected to the memory cell MC to be selected is set to 9 V, for example. On the other hand, the potentials of the first word lines CG12, CG21, and CG22 other than the selected first word line CG11 are set to 0V.

Further, the potential of the second word line SG11 connected to the memory cell MC to be selected is set to 2.5 V, for example. On the other hand, the potentials of the second word lines SG12, SG21, and SG22 other than the selected second word line SG11 are set to 0V.

Further, the potential of the source line SL11 connected to the memory cell MC to be selected is set to 5.5 V, for example. On the other hand, the potential of the source line SL21 other than the selected source line SL11 is made floating.

The potential V _B1 of the P-type well 26 is set to 0 V in all cases. In addition, the potential V _B2 of the P-type well 74PS is set to 0V.

When the electric potential of each part is set as described above, electrons flow between the source diffusion layer 36a and the drain diffusion layer 36b of the memory cell transistor MT and electrons are introduced into the floating gate 30a of the memory cell transistor MT. As a result, charges are accumulated in the floating gate 30a of the memory cell transistor MT, and information is written in the memory cell transistor MT.

(Erase method)

Next, an erasing method of the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIGS. 59 and 60. FIG. 60 is a cross-sectional view showing the erasing method of the nonvolatile semiconductor memory device according to the present embodiment.

Erasing of information recorded in the memory cell array is performed for each sector SCT, for example. Here, a case where the information recorded in the plurality of memory cells MC existing in the first sector SCT1 is collectively erased will be described as an example.

In the present embodiment, the information recorded in the memory cell transistor MT is erased as follows.

When the information recorded in the memory cell transistor MT is erased, the potentials of the main bit lines MBL1 and MBL2 are always set to the floating state. When the information recorded in the memory cell transistor MT is erased, the potentials of the source lines SL11 and SL21 are always set to the floating state. The potential of the semiconductor substrate 20 is set to 0 V (ground). The potentials of the gates SG11, SG12, SG21, and SG22 of the selection transistor ST are always set to the floating state.

When the information written in the memory cell transistor MT is erased, the second control circuit 29 first sets the potential BG of the gate of the voltage buffer transistor BT to the fourth potential V _ERS4 . Here, the potential (fourth potential) V _ERS4 of the gate of the voltage buffer transistor BT is _set to 3 V, for example.

Next, the second voltage application circuit 17 sets the potential V _B2 of the P-type well 74PS to the third potential V _ERS3 . Here, the third potential V _{ERS3 is set} to, for example, _6V .

In addition, the potentials of the sector select lines SSL11, SSL12, SSL21, and _SSL22 are set to the second potential V _ERS2 . Here, the potential (second potential) V _ERS2 of the sector select lines SSL11, SSL12, SSL21, and SSL22 is _set to 5 V, for example.

Next, the potential V _B1 of the P-type well 26 is set to the first potential V _ERS1 by the first voltage application circuit 15. Here, the first potential V _ERS1 is set to 9 V, for example.

Next, the potentials of the first word lines CG11 and CG12 connected to the memory cells MC in the first sector SCT1 to be erased are set to -9 V, for example. On the other hand, the potentials of the word lines CG21 and CG22 connected to the memory cells MC in the second sector SCT2 that are not to be erased are made floating, for example.

When the potential of the first word lines CG11 and CG12 is set to, for example, -9 V, charges are discharged from the floating gate 30a of the memory cell transistor MT. As a result, no charge is accumulated in the floating gate 30a of the memory cell transistor MT, and information of the memory cell transistor MT is erased.

As described above, when the information recorded in the memory cell transistor MT is erased, the potential (first potential) V _ERS1 of the P-type well 26 is set to, for example, _9V . When the potential V _ERS1 of the P-type well 26 is set to 9 V, the potential V _ERS1 'of the source diffusion layer 104 of the sector select transistor SST is about 8.5 to 8.7 V, for example. The potential V _ERS1 'of the source diffusion layer 104 is lower than the potential V _{ERS1 of the} P-type well 26 because a voltage drop occurs due to the diode formed by the P-type well 26 and the drain diffusion layer 36c to be.

When the potential (third potential) V _ERS3 of the P-type well _74PS is, for example, 6 V, the potential difference V _ERS1 '-V (V ERS1'V) between the source diffusion layer 104 of the sector select transistor SST and the P- _ERS3 ) is about 2.5 to 2.7 V, for example. Since the breakdown voltage of the second low-voltage transistor used as the sector select transistor SST is, for example, about 6 V as described above, it is possible to prevent the breakdown voltage between the source diffusion layer 104 of the sector select transistor SST and the P- There is no destruction.

When the potential (second potential) V _ERS2 of the sector selection line SSL is, for example, 5 V, the potential difference (V _ERS1 '- V _ERS2 ) between the gate electrode 34d of the sector select transistor SST and the source diffusion layer 104 ) Is about 3.5 to 3.7 V, for example. Since the breakdown voltage of the second low-voltage transistor used as the sector select transistor SST is, for example, about 6 V as described above, breakdown occurs between the gate electrode 34d of the sector select transistor SST and the source diffusion layer 104 There is nothing to happen.

When the potential (third potential) V _ERS3 of the P-type well _74PS is set to, for example, 6 V, the potential V _ERS3 'of the source diffusion layer 104 of the voltage buffer transistor BT is, for example, 5.5 V to 5.7 V . The potential V _ERS3 'of the source diffusion layer 104 is lower than the potential V _{ERS3 of the} P-type well 74PS because a voltage drop occurs due to the diode formed by the P-type well 74PS and the drain diffusion layer 104 to be.

The potential of the P-type well 74PB is 0 V (ground) as the potential of the semiconductor substrate 20. The potential difference between the source diffusion layer 104 and the P-type well 74PB of the voltage buffering transistor BT is, for example, about 5.5 to 5.7V. Since the breakdown voltage between the source diffusion layer 104 and the P-type well 74PB of the voltage buffer transistor BT is, for example, about 6 V as described above, the source diffusion layer 104 of the voltage buffer transistor BT and the P- 74PB), there is no breakage.

Further, when the potential (fourth potential) V _ERS4 of the gate BG of the voltage buffer transistor BT is, for example, 3 V, the potential difference between the gate electrode 34d of the voltage buffer transistor BT and the source diffusion layer 104 is For example, it is about 2.5 to 2.7 V. Since the withstand voltage of the voltage buffering transistor BT is, for example, about 3 V as described above, no breakage occurs between the gate electrode 34d of the voltage buffering transistor BT and the source diffusion layer 104. [

The potential of the source diffusion layer 104 of the first low-voltage transistor 111N used in the column decoder 12 becomes a potential V _ERS4 'lower than the potential of the gate electrode 34d of the voltage buffer transistor BT by the threshold voltage. When the potential of the gate electrode 34d of the voltage buffer transistor BT is, for example, 3 V and the threshold voltage of the voltage buffer transistor BT is, for example, 0.4 V, the potential of the first low-voltage transistor 111N of the column decoder 12, The potential V _ERS4 'of the source diffusion layer 104 is 2.6 V. Since the breakdown voltage between the source diffusion layer 104 and the P-type well 74P of the first low-voltage transistor 111N used in the column decoder 12 is about 6 V as described above, No breakdown occurs in the first low-voltage transistor 111N.

The electric potential of each part is not limited to the above.

The potential of the P-type well 26 (the first potential) V _ERS1, and the potential of the P-type well (74PS) (third electric potential) difference between the V _ERS3, sector select transistors, each of the electric potential is smaller than the breakdown voltage of the SST V _ERS1, V _ERS3 is set.

More strictly speaking, a sector select transistor SST difference between the source diffusion layer 104, the potential V _ERS1 'and the P-type well (74PS) potential V _ERS3 of a, is smaller than the breakdown voltage of a sector select transistor SST each potential V _ERS1, V _ERS3 is set.

The difference between the potential (second potential) V _ERS2 of the gate electrode 34d of the sector select transistor SST and the potential (first potential) V _ERS1 of the P-type well 26 is smaller than the breakdown voltage of the sector select transistor SST The potentials V _ERS1 and V _ERS2 are set.

More strictly speaking, the sector select transistors SST of the potential V _ERS1 of the gate electrode potential V _ERS2 and the source diffusion layer 104 of (34d) 'difference, is smaller than the breakdown voltage of a sector select transistor SST each potential V _ERS1, V _ERS2 Is set.

The potential V _ERS3 of the P-type well _74PS is set so that the potential (third potential) V _ERS3 of the P-type well _74PS becomes smaller than the breakdown voltage of the voltage buffer transistor BT.

More precisely, the third potential V _ERS3 is set such that the difference between the potential V _ERS3 'of the source diffusion layer 104 of the voltage buffer transistor BT and the potential of the P-type well _74PB becomes smaller than the breakdown voltage of the voltage buffer transistor BT.

Further, the voltage buffer transistor electric potential of the gate electrode (34d) of the BT potential of the (fourth electric potential) V _ERS4 and the P-type well (74PS) (third electric potential) difference between the V _ERS3, is smaller than the voltage buffer transistor BT pressure, respectively The potentials V _ERS3 and V _ERS4 are set.

More precise, the voltage buffer transistor potential of the potential V _ERS4 and the source diffusion layer 104 of the gate electrode (34d) of the BT V _ERS3 'with the difference, is smaller than the voltage buffer transistor BT pressure respective potentials V _ERS3, V _ERS4 Is set.

The fourth potential V _ERS4 is set so that the potential (fourth potential) V _ERS4 of the gate electrode 34d of the voltage buffer transistor BT becomes smaller than the breakdown voltage of the low voltage transistor 111N of the column decoder 12.

More precisely, the difference between the potential V _ERS4 'of the source diffusion layer 104 of the low-voltage transistor 111N of the column decoder 12 and the potential of the P-type well _74P is lower than the potential of the low- The fourth potential V _ERS4 is set to be smaller than the breakdown voltage.

When both the first potential V _ERS1 to the fourth potential V _ERS4 are positive, the second potential V _ERS2 is set to be lower than the first potential V _ERS1 , and the third potential V _{ERS3 is} also set to be lower than the first potential V _ERS1 . Further, the fourth potential V _ERS4 is set lower than the third potential V _ERS3 .

As described above, in this embodiment, since the breakdown voltage between the P-type well 74PB and the source / drain diffusion layer 104 of the voltage buffering transistor BT is relatively high, a bias voltage is applied to the P-type well 74PB Is not required. When information recorded in the memory cell transistor MT is erased, a bias voltage is applied to the gate electrode 34d of the voltage buffer transistor BT to prevent breakage of the voltage buffer transistor BT. As in the present embodiment, the region 11 in which the voltage buffering transistor is formed may not be a triple well structure.

In this example, the case where the potential V _ERS2 of the sector select line SSL is _set to, for example, 5 V at the time of erasing the information recorded in the memory cell transistor MT has been described as an example, but the potential of the sector select line SSL may be floating . It is possible to prevent the sector select transistor SST from being broken at the time of erasing even when the potential of the sector select line SSL is made floating when the information recorded in the memory cell transistor MT is erased.

[Fourth Embodiment]

A nonvolatile semiconductor memory device, a reading method, a recording method, an erasing method, and a method of manufacturing the nonvolatile semiconductor memory device according to the fourth embodiment will be described with reference to FIGS. 61 to 65. FIG. The same components as those of the nonvolatile semiconductor memory device or the like according to the first to third embodiments shown in Figs. 1 to 60 are denoted by the same reference numerals, and the description thereof is omitted or simplified.

(Nonvolatile semiconductor memory device)

First, a nonvolatile semiconductor memory device according to this embodiment will be described with reference to FIGS. 61 to 63. FIG. 61 is a circuit diagram showing a nonvolatile semiconductor memory device according to the present embodiment. 62 is a cross-sectional view showing a nonvolatile semiconductor memory device according to the present embodiment.

The nonvolatile semiconductor memory device according to the present embodiment is mainly characterized in that a transistor substantially identical to the memory cell transistor MT or the sector select transistor SST is used as the sector select transistor SST.

27), the second control circuit 29 (see FIG. 27), and the third voltage applying circuit 60 (see FIG. 27) (See Fig. 27) is not provided.

The drain of the sector select transistor SST is connected to the column decoder 12 by the main bit line MBL without passing through the voltage buffer transistor BT (see Fig. 27).

As shown in FIG. 62, an N-type well (N-type diffusion layer) 25 is formed in a region 7 where the sector select transistor SST is formed. In the N-type well 25, a P-type well 72PS is formed.

A gate electrode 30c is formed on the P-type well 72PS via a gate insulating film 28c.

The gate insulating film 28c of the sector select transistor SST is formed by the same insulating film as the tunnel insulating film 28a of the memory cell transistor MT and the gate insulating film 28b of the select transistor ST. Therefore, the film thickness of the gate insulating film 28c of the sector select transistor SST becomes equal to the film thickness of the tunnel insulating film 28a of the memory cell transistor MT and the film thickness of the gate insulating film 28b of the sector select transistor SST have.

The gate electrode 30c of the sector select transistor SST is formed by the same conductive film (polysilicon film) as the floating gate 30a of the memory cell transistor MT and the select gate 30b of the select transistor ST. Therefore, the thickness of the gate electrode 30c of the sector select transistor SST is equal to the thickness of the floating gate 30a of the memory cell transistor MT and the thickness of the select gate 30b of the select transistor ST.

A polysilicon layer (conductive layer) 34e is formed on the gate electrode 30b of the sector select transistor SST with an insulating film 32c interposed therebetween. The insulating film 32c of the sector select transistor SST is formed by the same insulating film as the insulating film 32a of the memory cell transistor MT and the insulating film 32b of the select transistor ST. Therefore, the film thickness of the insulating film 32c of the sector select transistor SST is equal to the film thickness of the insulating film 32a of the memory cell transistor MT and the film thickness of the insulating film 32b of the select transistor ST. The polysilicon film 34e of the sector select transistor SST is formed by the same conductive film as the control gate 34a of the memory cell transistor MT and the polysilicon film 34b of the selection transistor ST. Therefore, the thickness of the polysilicon film 34e of the sector select transistor SST is equal to the thickness of the control gate 34a of the memory cell transistor MT and the thickness of the polysilicon film 34b of the select transistor ST.

In the semiconductor substrate 20 on both sides of the gate electrode 30b of the sector select transistor SST, an N type impurity diffusion layer 36d is formed. The source / drain diffusion layer 36d of the sector select transistor SST is formed at the same time as the source / drain diffusion layers 36a to 36c of the selection transistor ST and the memory cell transistor MT are formed.

In this way, the sector select transistor SST having the gate electrode 30c, the polysilicon film 34e, and the source / drain diffusion layer 104 is formed on the P-type well 72PS. As described above, in this embodiment, as the sector select transistor SST, substantially the same transistors as the memory cell transistor MT and the selection transistor ST are used. However, the detailed structure of the sector select transistor SST is not necessarily the same as the memory cell transistor MT or the sector select transistor SST.

63 is a diagram showing the type of the transistor used in each component, the breakdown voltage of the transistor, and the film thickness of the gate insulating film of the transistor.

As shown in Fig. 63, as the sector select transistor SST, the same transistor P1Tr as the memory cell transistor MT and the select transistor ST is used. The breakdown voltage of the sector select transistor SST is, for example, about 8V. In other words, the breakdown voltage of the sector select transistor SST is relatively high, like the memory cell transistor MT and the select transistor ST. The film thickness of the gate insulating film 28c of the sector select transistor SST is, for example, about 8 to 12 nm.

As the column decoder 12, a first low-voltage transistor (1.8 VTr) 111N and 111P (see FIG. 54) having a rated voltage of, for example, 1.8 V is used. The internal voltages of the first low-voltage transistors 111N and 111P used in the column decoder 12 are, for example, about 3V. The film thickness of the gate insulating film 79 of the first low-voltage transistors 111N and 111P used in the column decoder 12 is, for example, about 3 nm.

The sense amplifier 13 uses a first low-voltage transistor (1.8 VTr) 111N and 111P having a rated voltage of 1.8 V, for example. The internal voltages of the low-voltage transistors 111N and 111P used in the sense amplifier 13 are, for example, about 3V. The film thickness of the gate insulating film 79 of the low-voltage transistors 111N and 111P used in the column decoder 12 is, for example, about 3 nm.

Also, as the first row decoder 14, high-voltage transistors (10 VTr) 110N and 110P having a rated voltage of, for example, 10 V are used. The breakdown voltage of the high voltage transistors 110N and 110P used in the first row decoder 14 is, for example, about 12 V. [ The film thickness of the gate insulating film 76 of the high voltage transistors 110N and 110P used in the first row decoder 14 is, for example, about 16 nm.

The second row decoder 16 uses a first low-voltage transistor (1.8 VTr) 111N and 111P having a rated voltage of 1.8 V, for example. The internal voltages of the low-voltage transistors 111N and 111P used in the second row decoder 16 are, for example, about 3V. The film thickness of the gate insulating film 79 of the low-voltage transistors 111N and 111P used in the second row decoder 16 is, for example, about 3 nm.

The third high-voltage transistor 10 VTr (110 VT) 110 N, 110 P having a rated voltage of, for example, 10 V is used as the third row decoder 18. The breakdown voltage of the high voltage transistors 110N and 110P used in the third row decoder 18 is, for example, about 12V. The film thickness of the gate insulating film 76 of the high voltage transistors 110N and 110P used in the third row decoder 18 is, for example, about 16 nm.

As the control circuit 23, low voltage transistors (1.8 VTr) 111N and 111P having a rated voltage of, for example, 1.8 V are used. The internal voltages of the low-voltage transistors 111N and 111P used in the control circuit 23 are, for example, about 3V. The film thickness of the gate insulating film 79 of the low-voltage transistors 111N and 111P used in the control circuit 23 is, for example, about 3 nm.

The first voltage applying circuit 15 uses the high voltage transistor 10 VTr 110N and 110P having a rated voltage of, for example, 10V. The breakdown voltage of the high voltage transistors 110N and 110P used in the first voltage application circuit 15 is, for example, about 12V. The film thickness of the gate insulating film 76 of the high voltage transistors 110N and 110P used in the first voltage applying circuit 15 is, for example, about 16 nm.

As the second voltage applying circuit 17, a first low-voltage transistor (1.8 VTr) 111N, 111P having a rated voltage of, for example, 1.8 V is used. The internal voltages of the low-voltage transistors 111N and 111P used in the second voltage application circuit 17 are, for example, about 3V. The film thickness of the gate insulating film 79 of the low-voltage transistors 111N and 111P used in the second voltage applying circuit 17 is, for example, about 3 nm.

(Operation of nonvolatile semiconductor memory device)

Next, an operation method of the nonvolatile semiconductor memory device according to the present modification will be described with reference to FIGS. 64 and 65. FIG. FIG. 64 is a diagram showing a reading method, a recording method, and an erasing method of the nonvolatile semiconductor memory device according to the present embodiment. In Fig. 64, F represents floating.

(Reading method)

First, a reading method of the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIG.

Here, the case of reading the information recorded in the memory cell MC surrounded by the broken line A and the memory cell MC surrounded by the broken line B in Fig. 61 will be described as an example.

When reading information recorded in the memory cell transistor MT, the potential of each part is set as follows.

That is, the potential of the sector selection line SSL11 connected to the sector select transistor SST connected to the memory cell MC to be selected is set to 1.8 V, for example. On the other hand, the potentials of the sector selection lines SSL12, SSL21, and SSL22 other than the selected sector selection line SSL11 are all 0V.

The potentials of the main bit lines (bit lines) MBL1 and MBL2 connected to the sector select transistor SST connected to the memory cell MC to be selected are set to 0.5 V, for example.

Also, the potentials of the first word lines CG11, CG12, CG21, and CG22 are always set to 1.8V.

Further, the potential of the second word line SG11 connected to the memory cell MC to be selected is set to 1.8 V, for example. On the other hand, the potentials of the second word lines SG12, SG21, and SG22 other than the selected second word line SG11 are set to 0V.

The potential V _B1 of the P-type well 26 is set to 0 V in all cases. In addition, the potential V _B2 of the P-type well 72PS is set to 0V. The potentials of the source lines SL11 and SL21 are all 0V.

Also in this embodiment, since the low-voltage transistor is used as the sector select transistor SST, a sufficiently large read current is obtained when the information recorded in the memory cell transistor MT is read. Therefore, according to the present embodiment, it is possible to determine the information recorded in the memory cell transistor MT at a high speed, and moreover, it becomes possible to read the information recorded in the memory cell transistor MT at a high speed.

(Recording method)

Next, a recording method of the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIG.

Here, a case where information is recorded in the memory cell MC surrounded by the broken line A in FIG. 61 will be described as an example.

When information is written in the memory cell transistor MT, the potential of each part is set as follows.

That is, the potential of the sector selection line SSL11 connected to the sector select transistor SST connected to the memory cell MC (memory cell A) to be selected is set to 1.8 V, for example. On the other hand, the potentials of the sector selection lines SSL12, SSL21, and SSL22 other than the selected sector selection line SSL11 are all 0V.

In addition, the potential of the main bit line (bit line) MBL1 connected to the sector select transistor SST connected to the memory cell MC to be selected is set to 0 V, for example. On the other hand, the potential of the main bit line MBL2 other than the selected main bit line MBL1 is made floating.

Further, the potential of the first word line CG11 connected to the memory cell MC to be selected is set to 9 V, for example. On the other hand, the potentials of the first word lines CG12, CG21, and CG22 other than the selected first word line CG11 are set to 0V.

Further, the potential of the second word line SG11 connected to the memory cell MC to be selected is set to 2.5 V, for example. On the other hand, the potentials of the second word lines SG12, SG21, and SG22 other than the selected second word line SG11 are set to 0V.

Further, the potential of the source line SL11 connected to the memory cell MC to be selected is set to 5.5 V, for example. On the other hand, the potential of the source line SL21 other than the selected source line SL11 is made floating.

The potential V _B1 of the P-type well 26 is set to 0 V in all cases. In addition, the potential V _B2 of the P-type well 72PS is set to 0V.

When the electric potential of each part is set as described above, electrons flow between the source diffusion layer 36a and the drain diffusion layer 36b of the memory cell transistor MT and electrons are introduced into the floating gate 30a of the memory cell transistor MT. As a result, charges are accumulated in the floating gate 30a of the memory cell transistor MT, and information is written in the memory cell transistor MT.

(Erase method)

Next, a method of erasing the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIGS. 64 and 65. FIG. 65 is a cross-sectional view showing the erasing method of the nonvolatile semiconductor memory device according to the present embodiment.

Erasing of information recorded in the memory cell array is performed for each sector SCT, for example. Here, a case where the information recorded in the plurality of memory cells MC existing in the first sector SCT1 is collectively erased will be described as an example.

In the present embodiment, the information recorded in the memory cell transistor MT is erased as follows.

When the information recorded in the memory cell transistor MT is erased, the potentials of the main bit lines MBL1 and MBL2 are always set to the floating state. When the information recorded in the memory cell transistor MT is erased, the potentials of the source lines SL11 and SL21 are always set to the floating state. The potential of the semiconductor substrate 20 is set to 0 V (ground). The potentials of the gates SG11, SG12, SG21, and SG22 of the selection transistor ST are always set to the floating state.

To erase the information recorded in the memory cell transistor MT, the potential V _B2 of the P-type well _72PS is first set to the third potential V _ERS3 by the second voltage application circuit 17. [ Here, the third potential V _{ERS3 is set} to 1.8 V, for example.

Further, the potentials of the sector select lines SSL11, SSL12, SSL21, and _SSL22 are set to the second potential V _ERS2 . Here, the second potential V _ERS2 is set to 1.8 V, for example.

Next, the potential V _B1 of the P-type well 26 is set to the first potential V _ERS1 by the first voltage applying circuit 15. Here, the first potential V _ERS1 is set to 9 V, for example.

Next, the potentials of the first word lines CG11 and CG12 connected to the memory cells MC in the first sector SCT1 to be erased are set to -9 V, for example. On the other hand, the potentials of the word lines CG21 and CG22 connected to the memory cells MC in the second sector SCT2 that are not to be erased are made floating, for example.

When the potential of the first word lines CG11 and CG12 is set to, for example, -9 V, charges are discharged from the floating gate 30a of the memory cell transistor MT. As a result, no charge is accumulated in the floating gate 30a of the memory cell transistor MT, and information of the memory cell transistor MT is erased.

As described above, when the information recorded in the memory cell transistor MT is erased, the potential (first potential) V _ERS1 of the P-type well 26 is set to, for example, _9V . When the potential V _ERS1 of the P-type well 26 is set to 9 V, the potential V _ERS1 'of the source diffusion layer 104 of the sector select transistor SST is about 8.5 to 8.7 V, for example. The potential V _ERS1 'of the source diffusion layer 104 is lower than the potential V _{ERS1 of the} P-type well 26 because a voltage drop occurs due to the diode formed by the P-type well 26 and the drain diffusion layer 36c to be.

When the potential (third potential) V _ERS3 of the P-type well _72PS is, for example, 1.8 V, the potential difference V _ERS1 '-V (V ERS1'V) between the source diffusion layer 104 of the sector select transistor SST and the P- _ERS3 ) is about 6.7 to 6.9 V, for example. Since the breakdown voltage of the sector select transistor SST is, for example, about 8 V as described above, no breakage occurs between the P-type well 72PS and the source diffusion layer 104 of the sector select transistor SST.

When the potential (second potential) V _ERS2 of the sector selection line SSL is, for example, 1.8 V, the potential difference (V _ERS1 '-V _ERS2 between the gate electrode 34d of the sector select transistor SST and the source diffusion layer 104 ) Is about 6.7 to 6.9 V, for example. Since the breakdown voltage of the sector select transistor SST is, for example, about 8 V as described above, there is no breakdown between the gate electrode 34d of the sector select transistor SST and the source diffusion layer 104. [

When the potential (third potential) V _ERS3 of the P-type well _72PS is set to, for example, 1.8 V, the potential V _ERS3 'of the source diffusion layer 104 of the low-voltage transistor 111N of the column decoder 12, For example, it is about 1.3 to 1.5 V. The potential V _ERS3 'of the source diffusion layer 104 of the low-voltage transistor 111N of the column decoder 12 is lower than the potential V _ERS3 of the P-type well 72PS because the potential difference between the P-type well 72PS and the drain diffusion layer 104, A voltage drop occurs due to the diode formed by the diode.

Since the breakdown voltage of the low voltage transistor 111N used in the column decoder 12 is about 3 V as described above, the breakdown of the first low voltage transistor 111N of the column decoder 12 does not occur.

The electric potential of each part is not limited to the above.

The potential of the P-type well 26 (the first potential) V _ERS1, and the potential of the P-type well (72PS) (third electric potential) difference between the V _ERS3, sector select transistors, each of the electric potential is smaller than the breakdown voltage of the SST V _ERS1, V _ERS3 is set.

More strictly speaking, a sector select transistor SST difference between the source diffusion layer 104, the potential V _ERS1 'and the P-type well (72PS) potential V _ERS3 of a, is smaller than the breakdown voltage of a sector select transistor SST each potential V _ERS1, V _ERS3 is set.

The difference between the potential (second potential) V _ERS2 of the gate electrode 30b of the sector select transistor SST and the potential (first potential) V _ERS1 of the P-type well 26 is set to be smaller than the breakdown voltage of the sector select transistor SST The potentials V _ERS1 and V _ERS2 are set.

More strictly speaking, the sector select transistors SST of the potential V _ERS1 of the gate electrode potential V _ERS2 and the source diffusion layer 104 of (34d) 'difference, is smaller than the breakdown voltage of a sector select transistor SST each potential V _ERS1, V _ERS2 Is set.

The third potential V _ERS3 is set such that the potential (third potential) V _ERS3 of the P-type well _72PS becomes smaller than the breakdown voltage of the low voltage transistor 111N of the column decoder 12.

More precisely, the difference between the potential V _ERS3 'of the source diffusion layer 104 of the low-voltage transistor 111N of the column decoder 12 and the potential of the P-type well 72P is lower than the potential of the low-voltage transistor 111N of the column decoder 12, The third potential V _ERS3 is set so as to be smaller than the breakdown voltage of the _{transistor Tr3} .

When both the first potential V _ERS1 to the third potential V _ERS3 are positive, the second potential V _ERS2 is set to be lower than the first potential V _ERS1 , and the third potential V _{ERS3 is} also set to be lower than the first potential V _ERS1 .

As described above, in this embodiment, since the same transistors as the memory cell transistor MT and the selection transistor ST are used as the sector select transistor SST, the breakdown voltage of the sector select transistor SST is relatively high. Therefore, even when a relatively low voltage is applied to the gate electrode 30b and the P-type well 72PS of the sector select transistor SST at the time of erasing the information recorded in the memory cell transistor MT, the sector select transistor SST is destroyed There is no work. The voltage applied to the gate electrode 30b and the P-type well 72PS of the sector select transistor SST can be set relatively low. Therefore, the transistor 111N having a very low withstand voltage can be provided to the column decoder (12).

(Manufacturing Method of Nonvolatile Semiconductor Memory Device)

Next, a method of manufacturing the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIGS. 66 to 78. FIG. 66 to 78 are sectional views showing the steps of a method of manufacturing the nonvolatile semiconductor memory device according to the present embodiment.

Figures 66 (a), 67 (a), 68 (a), 69 (a), 70 (a), 71 (a), 72 73 (a), 74 (a), 75 (a), 76 (a) and 77 show the memory cell array region 2. Figures 66 (a), 67 (a), 68 (a), 69 (a), 70 (a), 71 (a), 72 73A, 74A, 75A, 76A and 77, the left side of the drawing corresponds to the section taken along the line E-E 'in FIG. 29 have. Figures 66 (a), 67 (a), 68 (a), 69 (a), 70 (a), 71 (a), 72 73A, 74A, 75A, 76A and 77, the right side of the drawing corresponds to a cross section taken along the line C-C 'in FIG. 29 have.

Figures 66 (b), 67 (b), 68 (b), 69 (b), 70 (b), 71 (b), 72 73 (b), 74 (b), 75 (b), 76 (b) and 78 show the peripheral circuit region 4. Figures 66 (b), 67 (b), 68 (b), 69 (b), 70 (b), 71 (b), 72 73 (b), 74 (b), 75 (b), 76 (b) and 78 show the region 6 where the high breakdown voltage transistor is formed. The region 6 on the left side of the region 6 where the high breakdown voltage transistor is formed represents the region 6N where the high breakdown voltage N-channel transistor is formed. The right side of the region 6N where the high-breakdown-voltage N-channel transistor is formed represents the region 6P where the high-breakdown-voltage P-channel transistor is formed.

The right side of the region 6P where the high breakdown voltage P-channel transistor is formed shows the region 7 where the sector select transistor is formed.

Figures 66 (b), 67 (b), 68 (b), 69 (b), 70 (b), 71 (b), 72 73 (b), 74 (b), 75 (b), 76 (b) and 78 show the region 8 where the first low-voltage transistor is formed. The left side of the region of the region 8 where the first low-voltage transistor is formed shows a region 8N in which the first low-voltage N-channel transistor is formed. The right side of the region 8 where the low-voltage transistor is formed represents the region 8P in which the first low-voltage P-channel transistor is formed.

First, the steps from the step of preparing the semiconductor substrate 20 to the step of growing the sacrificial oxide film 69 are the same as the method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment described above with reference to FIGS. 10 to 12 Therefore, the description will be omitted.

Next, as shown in FIG. 66, an N type buried diffusion layer 24 is formed by deeply implanting N type dopant impurities into the memory cell array region 2. Next, as shown in FIG. An N type buried diffusion layer 25 is also formed by implanting an N type dopant impurity deep into the region 6N where the high voltage N channel transistor is formed. Further, an N type buried diffusion layer 25 is formed by deeply implanting an N type dopant impurity into the region 7 where the sector select transistor is formed. A P-type well 26 is formed by implanting a P-type dopant impurity into the memory cell array region 2 shallower than the buried diffusion layer 24. The P-type well 72P is formed by implanting a P-type dopant impurity shallower than the buried diffusion layer 25 in the region 6N where the high-voltage N-channel transistor is formed. A P type well 72PS is formed by implanting a P type dopant impurity shallower than the buried diffusion layer 25 in the region 7 where the sector select transistor is formed.

Next, in the region 6N in which the high-breakdown-voltage N-channel transistor is formed, the N-type diffusion layer 70 is formed in a frame shape. This frame-type diffusion layer 70 is formed so as to extend from the surface of the semiconductor substrate 20 to the periphery of the buried diffusion layer 25. [ The P type well 72P is surrounded by the buried diffusion layer 25 and the diffusion layer 70. [

In addition, the N-type diffusion layer 70 is formed in the frame 7 in the region 7 where the sector select transistor is formed. This frame-type diffusion layer 70 is formed so as to extend from the surface of the semiconductor substrate 20 to the periphery of the buried diffusion layer 25. [

Although not shown, the P-type well 26 of the memory cell array region 2 is also surrounded by the buried diffusion layer 24 and the frame-shaped diffusion layer 70.

Next, an N-type well 72N is formed by introducing an N-type dopant impurity into the region 6P where the high-breakdown-voltage P-channel transistor is formed.

Next, channel doping is performed on the memory cell array region 2 (not shown).

Next, channel doping is performed on the region 6N where the high-breakdown-voltage N-channel transistor is formed and the region 6P where the high breakdown voltage P-channel transistor is formed (not shown).

Next, channel doping is performed on the region 7 where the sector select transistor is formed (not shown).

Next, the sacrificial oxide film 69 (see FIG. 13) existing on the surface of the semiconductor substrate 20 is etched away.

Next, a tunnel insulating film 28 with a thickness of 10 nm is formed on the entire surface by thermal oxidation.

Next, a polysilicon film 30 having a film thickness of 90 nm is formed on the entire surface by, for example, CVD. As the polysilicon film 30, a polysilicon film doped with an impurity is formed.

67, the polysilicon film 30 in the memory cell array region 2 is patterned and the polysilicon film 30 present in the peripheral circuit region 4 is etched away.

Next, an insulating film (ONO film) 32 formed by sequentially laminating a silicon oxide film, a silicon nitride film, and a silicon oxide film on the entire surface is formed. This insulating film 32 is for insulating the floating gate 30a and the control gate 34a.

Next, the P-type well 74P is formed by introducing a P-type dopant impurity into the region 8N where the first low-voltage N-channel transistor is formed.

Next, an N-type well 74N is formed by introducing an N-type dopant impurity into the region 8P where the first low-voltage P-channel transistor is formed.

Next, as shown in FIG. 68, the region 6 in which the high breakdown voltage transistor is formed and the insulating film (ONO film) 32 in the region 8 where the first low voltage transistor is formed are etched away. The insulating film 32 remains in the memory cell array region 2 and the region 7 where the sector select transistor is formed.

Next, channel doping is performed on the region 8N where the first low-voltage N-channel transistor is formed and the region 8P where the first low-voltage P-channel transistor is formed (not shown).

Next, a gate insulating film 76 having a thickness of 15 nm, for example, is formed on the entire surface by thermal oxidation (see FIG. 68).

Next, the gate insulating film 76 in the region 8 where the first low-voltage transistor is to be formed is removed by wet etching.

Next, on the entire surface, a gate insulating film 79 having a film thickness of 3 nm, for example, is formed by thermal oxidation (see FIG. 69). Thus, in the region 8 where the first low-voltage transistor is formed, for example, a gate insulating film 79 with a thickness of 3 nm is formed. In the region 6 where the high breakdown voltage transistor is formed, the film thickness of the gate insulating film 76 is, for example, about 16 nm.

Next, a polysilicon film 34 having a thickness of, for example, 180 nm is formed on the entire surface by, for example, CVD.

Next, an antireflection film 80 is formed on the entire surface (see FIG. 70).

71, the antireflection film 80, the polysilicon film 34, the insulating film 32, and the polysilicon film 30 are dry-etched by using the photolithography technique. As a result, a laminate having a floating gate 30a made of polysilicon and a control gate 34a made of polysilicon is formed in the memory cell array region 2. Further, a laminate having a select gate 30b made of polysilicon and a polysilicon film 34b is formed in the memory cell array region 2. [ A laminate having a gate electrode 30c made of polysilicon and a polysilicon film 34e is formed in the region 7 where the sector select transistor is formed.

Next, the polysilicon film 34b is etched away (not shown) in the region where the wiring (first metal wiring) 46 and the select gate 30b should be connected.

Next, a silicon oxide film (not shown) is formed on the sidewall portion of the floating gate 30a, the sidewall portion of the control gate 34a, the sidewall portion of the select gate 30b, and the sidewall portion of the polysilicon film 34b by thermal oxidation. Is formed.

Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

Next, an opening (not shown) exposing an opening (not shown) for exposing the memory cell array region 2 and a region 7 for forming the sector select transistor is formed by photolithography, .

Next, an N-type dopant impurity is introduced into the semiconductor substrate 20 using the photoresist film as a mask. The impurity diffusion layers 36a to 36c are formed in the semiconductor substrate 20 on both sides of the floating gate 30a and in the semiconductor substrate 20 on both sides of the select gate 30b. An impurity diffusion region 36d is formed in the semiconductor substrate 20 on both sides of the gate electrode 30c of the sector select transistor SST. Thereafter, the photoresist film is peeled off.

72, the memory cell transistor MT having the floating gate 30a, the control gate 34a, and the source / drain diffusion layers 36a and 36b is formed. Further, a select transistor ST having the select gate 30b and the source / drain diffused layers 36b and 36c is formed. In addition, the sector select transistor SST having the gate electrode 30c and the source / drain diffusion layer 36d is formed.

73, the sidewall portion of the floating gate 30a, the sidewall portion of the control gate 34a, the sidewall portion of the select gate 30b, and the sidewall portion of the polysilicon film 34b are thermally oxidized by thermal oxidation, A silicon oxide film 82 is formed.

Next, a silicon nitride film 84 having a thickness of 50 nm is formed by, e.g., CVD.

Next, the silicon nitride film 84 is anisotropically etched by dry etching to form a sidewall insulation film 84 made of a silicon nitride film. At this time, the antireflection film 80 is etched away.

Next, as shown in FIG. 74, the polysilicon film 34 in the peripheral circuit region 4 is patterned by photolithography. The gate electrode 34c of the high breakdown voltage transistors 110N and 110P made of the polysilicon film 34 is formed in the region 6 where the high breakdown voltage transistor is formed. A gate electrode 34d of the first low-voltage transistor 111N, 111P made of polysilicon 34 is formed in the region 8 where the first low-voltage transistor is formed.

Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

Next, an opening (not shown) exposing the region 6N in which the high-voltage N-channel transistor is formed is formed in the photoresist film by photolithography.

Next, an N-type dopant impurity is introduced into the semiconductor substrate 20 using the photoresist film as a mask. Thus, the N type lightly doped diffusion layer 86 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34c of the high-voltage N-channel transistor 110N. Thereafter, the photoresist film is peeled off.

Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

Next, an opening (not shown) exposing the region 6P in which the high voltage P-channel transistor is formed is formed in the photoresist film by photolithography.

Next, using the photoresist film as a mask, a P-type dopant impurity is introduced into the semiconductor substrate 20. Thus, a P-type low-concentration diffusion layer 88 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34c of the high-breakdown-voltage P-channel transistor 110P. Thereafter, the photoresist film is peeled off.

Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

Next, an opening (not shown) exposing the region 8N in which the first low-voltage N-channel transistor is formed is formed in the photoresist film by photolithography.

Next, an N-type dopant impurity is introduced into the semiconductor substrate 20 using the photoresist film as a mask. Thus, the N type lightly doped diffusion layer 90 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d of the first low-voltage N-channel transistor 111N. Thereafter, the photoresist film is peeled off.

Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

Next, an opening (not shown) exposing the region 8P in which the first low-voltage P-channel transistor is formed is formed in the photoresist film by photolithography.

Next, using the photoresist film as a mask, a P-type dopant impurity is introduced into the semiconductor substrate 20. Thus, a P-type lightly doped diffusion layer 92 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d of the first low-voltage P-channel transistor 111P. Thereafter, the photoresist film is peeled off.

Next, a silicon oxide film 93 having a thickness of 100 nm is formed by, e.g., CVD.

Next, the silicon oxide film 93 is anisotropically etched by dry etching. 75, a sidewall insulating film 93 made of a silicon oxide film is formed on the sidewall portion of the laminate having the floating gate 30a and the control gate 34a. A sidewall insulation film 93 made of a silicon oxide film is formed on the sidewall portion of the laminate having the select gate 30b and the polysilicon film 34b. A sidewall insulation film 93 made of a silicon oxide film is formed on the sidewall portion of the laminate having the gate electrode 30c and the polysilicon film 34e. A sidewall insulation film 93 made of a silicon oxide film is formed on the sidewall portions of the gate electrodes 34c and 34d.

Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

Next, an opening (not shown) exposing the region 6N in which the high-voltage N-channel transistor is formed is formed in the photoresist film by photolithography.

Next, an N-type dopant impurity is introduced into the semiconductor substrate 20 using the photoresist film as a mask. Thus, an N-type high-concentration diffusion layer 94 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34c of the high-breakdown-voltage N-channel transistor. An N-type source / drain diffusion layer 96 of an LDD structure is formed by the N-type low-concentration diffusion layer 86 and the N-type high-concentration diffusion layer 94. Thus, the high-breakdown-voltage N-channel transistor 110N having the gate electrode 34c and the source / drain diffusion layer 96 is formed. The high voltage N-channel transistor 110N is used in a high voltage circuit such as the first row decoder 14, the third row decoder 18, and the first voltage applying circuit 15. [

Thereafter, the photoresist film is peeled off.

Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

Next, an opening (not shown) exposing the region 6P in which the high voltage P-channel transistor is formed is formed in the photoresist film by photolithography.

Next, using the photoresist film as a mask, a P-type dopant impurity is introduced into the semiconductor substrate 20. Thus, a P-type high-concentration diffusion layer 98 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34c of the high-breakdown-voltage P-channel transistor 110P. The P-type source / drain diffusion layer 100 of the LDD structure is formed by the P-type low-concentration diffusion layer 88 and the P-type high-concentration diffusion layer 98. Thus, a high breakdown voltage P-channel transistor 110P having the gate electrode 34c and the source / drain diffusion layer 100 is formed. The high breakdown voltage p-channel transistor 110P is used in a high voltage circuit such as the first row decoder 14, the third row decoder 18, the first voltage applying circuit 15, and the like. Thereafter, the photoresist film is peeled off.

Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

Next, an opening (not shown) exposing the region 8N in which the first low-voltage N-channel transistor is formed is formed in the photoresist film by photolithography.

Next, an N-type dopant impurity is introduced into the semiconductor substrate 20 using the photoresist film as a mask. Thus, an N-type high-concentration diffusion layer 102 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d of the first low-voltage N-channel transistor 111N. An N-type source / drain diffusion layer 104 of an LDD structure is formed by the N-type low-concentration diffusion layer 90 and the N-type high-concentration diffusion layer 102.

Thus, the first low-voltage N-channel transistor 111N having the gate electrode 34d and the source / drain diffusion layer 104 is formed.

The first low-voltage N-channel transistor 111N is used for a low-voltage circuit such as a column decoder 12, a second row decoder 16, a control circuit 23, a second voltage application circuit 17, a sense amplifier 13, do.

Thereafter, the photoresist film is peeled off.

Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

Next, an opening (not shown) exposing the region 8P in which the first low-voltage P-channel transistor is formed is formed in the photoresist film by photolithography.

Next, using the photoresist film as a mask, a P-type dopant impurity is introduced into the semiconductor substrate 20. Thus, a P-type high-concentration diffusion layer 106 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d of the first low-voltage P-channel transistor 111P. The P-type source / drain diffusion layer 108 of the LDD structure is formed by the P-type low-concentration diffusion layer 92 and the P-type high-concentration diffusion layer 106. [

Thus, the first low-voltage P-channel transistor 111P having the gate electrode 34d and the source / drain diffusion layer 108 is formed. The first low-voltage P-channel transistor 111P is connected to the low-voltage circuit such as the column decoder 12, the second row decoder 16, the control circuit 23, the second voltage application circuit 17 and the sense amplifier 13 .

Thereafter, the photoresist film is peeled off.

Next, a 10-nm-thick cobalt film is formed on the entire surface by, for example, sputtering.

Next, cobalt silicide films 38a to 38f are formed in the same manner as in the nonvolatile semiconductor memory device according to the first embodiment described above with reference to FIG. Thereafter, the unreacted cobalt film is removed by etching.

The cobalt silicide film 38b formed on the drain diffusion layer 36c of the selection transistor ST functions as a drain electrode. The cobalt silicide film 38a formed on the source diffusion layer 36a of the memory cell transistor MT functions as a source electrode. The cobalt silicide film 38e formed on the source / drain diffusion layer 36d of the sector select transistor SST functions as a source / drain electrode.

The cobalt silicide film 38e formed on the source / drain diffusion layers 96 and 100 of the high-voltage transistors 110N and 110P functions as a source / drain electrode. The cobalt silicide film 38e formed on the source / drain diffusion layers 104 and 108 of the first low-voltage transistors 111N and 111P functions as a source / drain electrode (see FIG. 76).

Next, a silicon nitride film 114 having a thickness of 100 nm is formed on the entire surface by, for example, CVD. The silicon nitride film 114 functions as an etching stopper.

Next, a silicon oxide film 116 having a thickness of 1.6 占 퐉 is formed on the entire surface by a CVD method. Thus, an interlayer insulating film 40 composed of the silicon nitride film 114 and the silicon oxide film 116 is formed.

Next, the surface of the interlayer insulating film 40 is planarized by a CMP method.

Next, a contact hole 42 reaching the source / drain electrodes 38a and 38c, a contact hole 42 reaching the cobalt silicide film 38e, and a contact reaching the cobalt silicide film 38f are formed by photolithography, Holes 42 are formed.

Next, a barrier layer (not shown) made of a Ti film and a TiN film is formed on the entire surface by sputtering.

Next, a tungsten film 44 having a film thickness of 300 nm is formed on the entire surface by, for example, CVD.

Next, the tungsten film 44 and the barrier film are polished by CMP until the surface of the interlayer insulating film 40 is exposed. In this manner, a conductor plug 44 made of, for example, tungsten is embedded in the contact hole 42.

Next, a laminated film 46 is formed by sequentially laminating a Ti film, a TiN film, an Al film, a Ti film and a TiN film on the interlayer insulating film 40 in which the conductor plugs 44 are buried by, for example, sputtering. .

Next, the laminated film 46 is patterned by photolithography. Thus, a wiring (first metal wiring layer) 46 made of a laminated film is formed (see Figs. 77 and 78).

24 and 25, a multilayer wiring structure is formed in the same manner as in the above-described manufacturing method of the nonvolatile semiconductor memory device.

Thus, the nonvolatile semiconductor memory device according to the present embodiment is manufactured.

[Modified embodiment]

The present invention is not limited to the above-described embodiment, and various modifications are possible.

For example, in the first embodiment, the memory cell MC is formed by the memory cell transistor MT. However, as in the second embodiment, the memory cell MC is formed by the memory cell transistor MT and the selection transistor ST .

In the second to fourth embodiments, the case where the memory cell MC is formed by the memory cell transistor MT and the selection transistor ST has been described as an example. However, as in the first embodiment, May be formed.

Industrial availability

A nonvolatile semiconductor memory device and a method for recording the same according to the present invention are useful for providing a nonvolatile semiconductor memory device having a high operating speed.

2: memory cell array region 4: peripheral circuit region
6: region where high breakdown voltage transistor is formed
6N: region where a high-breakdown-voltage N-channel transistor is formed
6P: region where the high breakdown voltage P-channel transistor is formed
7: region where the sector select transistor is formed
8: region where the low-voltage transistor is formed, region where the first low-voltage transistor is formed
8N: region where the low-voltage N-channel transistor is formed, region where the first low-voltage N-channel transistor is formed
8P: a region where the low-voltage P-channel transistor is formed, a region where the first low-voltage P-channel transistor is formed
9: region where the second low-voltage transistor is formed
9N: region where the second low-voltage N-channel transistor is formed
9P: region where the second low-voltage P-channel transistor is formed
11: region where the voltage buffering transistor is formed
12: Thermal decoder 13: Sense amplifier
14: a row decoder, a first row decoder 15: a first voltage application circuit
16: second row decoder 17: second voltage application circuit
18: third row decoder 19: third voltage applying circuit
20: semiconductor substrate 21: element region
22: element isolation region 23: control circuit, first control circuit
24: N-type well, N-type diffusion layer 25: N-type well, N-type diffusion layer
26: P-type well 27: region where a column decoder is formed
28: tunnel insulating film 28a: tunnel insulating film
28b: gate insulating film 28c: gate insulating film
29: second control circuit 30: polysilicon film
30a: floating gate 30b: select gate
30c: gate electrode 32: insulating film, ONO film
32a, 32b, 32c: insulating film 34: polysilicon film
34a: control gate 34b: polysilicon film, conductive layer
34c, 34d: gate electrode 34e: polysilicon film, conductive layer
36a: impurity diffusion layer, source diffusion layer
36b: impurity diffusion layer, source / drain diffusion layer
36c: an impurity diffusion layer, a drain diffusion layer
36d: impurity diffusion layer, source / drain diffusion layer
37: side wall insulating film 38a: silicide layer, source electrode
38b: silicide layer, drain electrode 38c, 38d: silicide layer
38e: source / drain electrode 38f: silicide layer
40: interlayer insulating film 42: contact hole
44: conductor plug 46: wiring (first metal wiring layer)
48: interlayer insulating film 50: contact hole
52: conductor plug 54: wiring (second metal wiring layer)
56: interlayer insulating film 58: contact hole
60: conductor plug 62: wiring (third metal wiring layer)
64: thermal oxide film 66: silicon nitride film
68: groove 69: sacrificial oxide film
70: buried diffusion layer 72P: P-type well
72PS: P-type well 72N: N-type well
74P: P-type well 74N: N-type well
74PS: P-type well 74PB: P-type well
76: Gate insulating film 78: Gate insulating film
80: antireflection film 82: silicon oxide film
84: silicon nitride film, sidewall insulation film 86: low concentration diffusion layer
88: low concentration diffusion layer 90, 90a: low concentration diffusion layer
92, 92a: low concentration diffusion layer
93: a silicon oxide film, a sidewall insulation film
94: high concentration diffusion layer 96: source / drain diffusion layer
98: high concentration diffusion layer 100: source / drain diffusion layer
102: high concentration diffusion layer 104: source / drain diffusion layer
106: high concentration diffusion layer 108: source / drain diffusion layer
110N: High breakdown voltage N-channel transistor 110P: High breakdown voltage P-channel transistor
111N: first low voltage N-channel transistor
111P: first low-voltage P-channel transistor
112N: Low-voltage N-channel transistor 112P: Low-voltage P-channel transistor
113N: second low voltage N-channel transistor
113P: second low-voltage P-channel transistor
114: silicon nitride film 116: silicon oxide film
118: Silicon oxide film 120: Silicon oxide film
122: silicon oxide film 124: silicon oxide film
126: silicon oxide film 128: silicon oxide film
130: interlayer insulating film 132: contact hole
134: conductor plug 136: wiring (fourth metal wiring layer)
138: Silicon oxide film 140: Silicon oxide film
142: interlayer insulating film 143: contact hole
144: conductor plug 145: wiring
146: Silicon oxide film 148: Silicon nitride film
202: memory cell array region
207: region where the Selter Select transistor is formed
212: column decoder 213: sense amplifier
214: Row decoder 215: Voltage applying circuit
217: area where a column decoder is formed 220: semiconductor substrate
222: Element isolation region 223: Control circuit
224: buried diffusion layer, N-type well 226: P-type well
228a: tunnel insulating film
236a and 236c: source / drain diffusion layers
230a: floating gate 232a: insulating film
234a: control gate 234d: gate electrode
274P: P channel 276: gate insulating film
278: gate insulating film 304: source / drain diffusion layer
312N: N-channel transistor

Claims (11)

A substrate;
A memory cell array in which a plurality of memory cells having memory cell transistors are arranged in a matrix,
A plurality of first bit lines commonly connected to the drain sides of the plurality of memory cells existing in the same column,
A plurality of word lines which commonly connect the control gates of the plurality of memory cell transistors in the same row,
A column decoder connected to the plurality of second bit lines for controlling the potential of the plurality of second bit lines,
A row decoder connected to the plurality of word lines to control a potential of the plurality of word lines,
A plurality of first transistors each provided between the first bit line and the second bit line, the source of the first transistor being electrically connected to the first bit line, the drain of the first transistor being connected to the second bit A first transistor electrically connected to the column decoder through a line,
A first control unit for controlling a potential of a gate of the plurality of first transistors;
Lt; / RTI >
The memory cell transistor is formed on a first well,
The first transistor being formed on a second well electrically isolated from the first well,
Wherein the first well and the second well are formed in the substrate and are electrically separated from the substrate,
A first voltage application unit for applying a voltage to the first well,
And a second voltage application unit for applying a voltage to the second well,
Wherein the film thickness of the gate insulating film of the first transistor is thinner than the film thickness of the gate insulating film of the second transistor provided in the row decoder and connected to the word line. The semiconductor device according to claim 1, further comprising: a third transistor provided between the first transistor and the column decoder, the source of the third transistor being electrically connected to the drain of the first transistor, And a third transistor electrically connected to the column decoder. The semiconductor device according to claim 2, wherein the third transistor is formed on a third well electrically isolated from the first well and the second well,
A third voltage application unit for applying a third voltage to the third well,
And a second control unit for controlling a potential of a gate of the third transistor. The nonvolatile semiconductor memory device according to claim 3, wherein a film thickness of the gate insulating film of the third transistor is thinner than a film thickness of the gate insulating film of the first transistor. The method according to any one of claims 1 to 4, wherein the first well is set to a first potential, the gate electrode of the first transistor is set to a second potential lower than the first potential, And erasing information recorded in the memory cell while setting the well to a third potential lower than the first potential. The method according to claim 3 or 4, wherein the first well is set to a first potential, the gate electrode of the first transistor is set to a second potential lower than the first potential, The third transistor is set to a third potential lower than the first potential while the gate electrode of the third transistor is set to a fourth potential lower than the third potential and the third well is set to a fifth potential lower than the third potential, And erases the information recorded in the memory cell. The memory cell transistor according to any one of claims 1 to 4, wherein the memory cell transistor comprises: a floating gate formed on the first well via a tunnel insulating film; and a control gate formed on the floating gate via a first insulating film Lt; / RTI &
The gate insulating film of the first transistor is formed of the same insulating film as the tunnel insulating film,
The gate electrode of the first transistor is formed of the same conductive film as the floating gate,
The first transistor may further include a conductive layer formed on the gate electrode via a second insulating film,
The second insulating film of the first transistor is formed of the same insulating film as the first insulating film of the memory cell transistor,
Wherein the conductive layer of the first transistor is formed of the same conductive film as the control gate of the memory cell transistor. delete The memory cell array according to any one of claims 1 to 4, wherein the memory cell array is divided into a plurality of sectors,
Wherein the first transistor is a sector selection transistor for selecting the sector. A semiconductor memory device comprising: a substrate; a memory cell array in which a plurality of memory cells having memory cell transistors are arranged in a matrix; a plurality of first bit lines commonly connecting the drain sides of the plurality of memory cells in the same column; A plurality of word lines connected to the control gates of the plurality of memory cell transistors in common; a column decoder connected to the plurality of second bit lines for controlling the potential of the plurality of second bit lines; A plurality of first transistors each provided between the first bit line and the second bit line, the source of the first transistor being electrically connected to the first bit line And a drain of the first transistor is electrically connected to the column decoder through the second bit line, And a first control unit for controlling a potential of a gate of the plurality of first transistors, wherein the memory cell transistor is formed on a first well, and the first transistor is electrically isolated from the first well Wherein the first well and the second well are formed in the substrate and are electrically separated from the substrate, and the film thickness of the gate insulating film of the first transistor is set within the row decoder And the gate insulating film of the second transistor connected to the word line is thinner than the film thickness of the gate insulating film of the second transistor connected to the word line,
The first well is set to a first potential, the gate electrode of the first transistor is set to a second potential or floating lower than the first potential, and the second well is set to a third potential lower than the first potential And erasing the information recorded in the memory cell while setting the erasing period of the nonvolatile semiconductor memory device. 11. The semiconductor device according to claim 10, further comprising: a third transistor provided between the first transistor and the column decoder, the source of the third transistor being electrically connected to the drain of the first transistor, And a third transistor electrically connected to the column decoder,
The third transistor is formed on a third well electrically isolated from the first well and the second well,
When erasing the information recorded in the memory cell, the gate electrode of the third transistor is set to a fourth potential lower than the third potential, and the third well is set to a fifth potential lower than the third potential And said erasing step of erasing said nonvolatile semiconductor memory device.

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