KR101392183B1 - Liquid crystal display - Google Patents

Abstract

The present invention relates to a liquid crystal display device. A liquid crystal display device according to the present invention is a liquid crystal display device including first and second pixels, comprising: a plurality of gate lines for transmitting gate signals; and a plurality of pairs of gate lines crossing the gate lines, Wherein each of the first and second pixels includes a plurality of pixel electrodes each including first and second sub-pixel electrodes, a plurality of pixel electrodes disposed on the right side of the first data line, A first drain electrode, and a second drain electrode positioned on the left side of the second data line, wherein the first pixel is connected to the first drain electrode and the first sub-pixel electrode, 2 drain electrode and the second sub-pixel electrode are connected to each other, the second pixel is connected to the first drain electrode and the second sub-pixel electrode, and the second drain electrode and the first sub- And the shapes of the first and second drain electrodes of the first pixel are substantially the same as those of the first and second drain electrodes of the second pixel.

Description

[0001] LIQUID CRYSTAL DISPLAY [0002]

The present invention relates to a liquid crystal display device.

2. Description of the Related Art A liquid crystal display device is one of the most widely used flat panel display devices and is composed of two display panels in which electric field generating electrodes such as a pixel electrode and a common electrode are formed and a liquid crystal layer interposed therebetween, To generate an electric field in the liquid crystal layer, thereby determining the orientation of the liquid crystal molecules in the liquid crystal layer and controlling the polarization of the incident light to display an image.

The liquid crystal display device further includes a switching element connected to each pixel electrode, and a plurality of signal lines such as a gate line and a data line for controlling the switching element to apply a voltage to the pixel electrode.

In order to improve moving picture display characteristics, various methods have been attempted in such liquid crystal display devices, and high-speed driving is under development. In high-speed driving, since the power consumption is high as the frame rate is high, an attempt is made to minimize power consumption by introducing column inversion in the inversion driving method.

However, when the column inversion driving is performed, if a box with a higher gray scale is displayed on the screen of a low gray scale, a vertical crosstalk phenomenon may occur in which the gray scale is different from that of the desktop on the upper and lower sides of the box. Also, when the data voltage of the same polarity is applied in the longitudinal direction and the data voltage of the positive polarity and the data voltage of the negative polarity are different, a phenomenon of flickering in a vertical line may appear.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a liquid crystal display device in which optical characteristics of all the pixels are uniform without deterioration of image quality during thermal inversion driving.

According to an aspect of the present invention, there is provided a liquid crystal display device including a first pixel and a second pixel, the liquid crystal display including a plurality of gate lines for transmitting a gate signal, Wherein each pair of data lines of the plurality of pairs of data lines includes a first data line and a second data line intersecting the gate line, the first data line and the second data line are connected to the first pixel and the second pixel, The first pixel and the second pixel each include a pixel electrode including a pair of first sub-pixel electrodes and a second sub-pixel electrode, and a pair of first drain electrodes And a second drain electrode, wherein the first drain electrode is located to the right of the first data line, the second drain electrode is located to the left of the second data line, and the first Wherein the first drain electrode is connected to the first sub-pixel electrode through a first contact hole, the second drain electrode is connected to the second sub-pixel electrode through a second contact hole, Pixel, the first drain electrode is connected to the second sub-pixel electrode through a third contact hole, the second drain electrode is connected to the first sub-pixel electrode through a fourth contact hole, The first portion constituted by the first drain electrode and the second drain electrode of the first pixel has substantially the same shape as the second portion constituted by the first drain electrode and the second drain electrode of the second pixel, Wherein the first sub-pixel electrode and the second sub-pixel electrode are located on the same side with respect to the gate line, and the position of the first contact hole in the first pixel and the position of the fourth contact hole in the second pixel, The positions of the contact holes are equal to each other, and the position of the second contact hole in the first pixel and the position of the third contact hole in the second pixel are equal to each other.

The first drain and the second drain may each include at least one dummy portion.

Wherein each of the first drain electrode and the second drain electrode of the first pixel or the second pixel includes a contact hole connected to the pixel electrode of the first pixel or the second pixel, And at least one first branch extending from the first branch.

The dummy portion may include at least one second branch located between the first drain electrode or the second drain electrode and the contact portion.

The first data voltage applied to the first data line may be different from the second data voltage applied to the second data line.

The voltage polarity of the first data line may be opposite to the voltage polarity of the second data line.

Wherein the first unit and the second unit are alternately arranged in the column direction, the first unit includes at least two first pixels arranged consecutively in the column direction, and the second unit is arranged in the column direction And at least two second pixels arranged in series.

Wherein the voltage polarity of the first sub-pixel electrode in the first pixel is opposite to the voltage polarity of the second sub-pixel electrode, and the voltage polarity of the first sub- May be opposite to the voltage polarity.

The voltage polarities of the first sub-pixel electrodes adjacent to each other in the column direction may be changed every column or more.

The first subpixel electrode of the first pixel or the second pixel may have an area different from that of the first subpixel electrode or the second subpixel electrode of the second pixel.

According to the present invention, the optical characteristics of all the pixels can be made uniform without degrading the image quality in the thermal inversion driving.

1 is a block diagram of a liquid crystal display according to an embodiment of the present invention;
2 is an equivalent circuit diagram of two sub-pixels of a liquid crystal display according to an embodiment of the present invention.
3 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an embodiment of the present invention.
4 is a schematic diagram showing pixel arrangement and pixel polarity of a liquid crystal display according to an embodiment of the present invention.
5 is a schematic view showing pixel arrangement and pixel polarity of a liquid crystal display according to another embodiment of the present invention;
6 is a layout diagram of a thin film transistor panel of one pixel in a liquid crystal display according to an embodiment of the present invention.
7 is a layout view of a common electrode panel of one pixel in a liquid crystal display according to an embodiment of the present invention.
FIG. 8 is a layout view of a liquid crystal display device including the thin film transistor panel of FIG. 6 and the common electrode panel of FIG. 7;
Figs. 9 and 10 are cross-sectional views of the liquid crystal display device shown in Fig. 6 taken along lines IX-IX and X-X.
11 is a layout diagram showing another example of a pixel of a liquid crystal display device according to an embodiment of the present invention.
12 is a layout diagram showing an example of a pixel of a liquid crystal display device according to another embodiment of the present invention.
13 is a sectional view cut along the line XIII-XIII in the liquid crystal display device shown in Fig. 12; Fig.
14 is a layout diagram showing another example of a pixel of a liquid crystal display device according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. Like parts are designated with like reference numerals throughout the specification. It will be understood that when an element such as a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the element directly over another element, Conversely, when a part is "directly over" another part, it means that there is no other part in the middle.

Now, a liquid crystal display according to an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a liquid crystal display according to an embodiment of the present invention. FIG. 2 is an equivalent circuit diagram of two sub-pixels of a liquid crystal display according to an embodiment of the present invention. 1 is an equivalent circuit diagram of one pixel of a liquid crystal display device according to an embodiment.

1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400 connected to the liquid crystal panel assembly 300, a data driver 500, a data driver A gradation voltage generator 800 connected to the gradation voltage generator 500, and a signal controller 600 for controlling the gradation voltage generator 800 and the gradation voltage generator 800.

The liquid crystal display panel assembly 300 includes a plurality of display signal lines G ₁ -G _n and D ₁ -D _2m and a plurality of pixels PX connected to the display signal lines G ₁ -G _n and D ₁ -D _2m , . 2, the liquid crystal panel assembly 300 includes lower and upper display panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The display signal lines G ₁ -G _n and D ₁ -D _2m are connected to a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also referred to as a "scan signal") and a data line D _1- D _2m ). The gate lines G ₁ -G _n extend in a substantially row direction, are substantially parallel to each other, and the data lines D ₁ -D _2m extend in a substantially column direction and are substantially parallel to each other. A pair of data lines D ₁ -D _2m are arranged on both sides of one pixel PX.

Each pixel PX includes a pair of sub-pixels PEa and PEb. Each of the sub-pixels PEa and PEb includes a switching element (not shown) connected to the signal lines GL and DL, a liquid crystal capacitor Clca and a storage capacitor Cst connected thereto, . The storage capacitor Cst can be omitted if necessary.

The switching element is a three-terminal element such as a thin film transistor provided in the lower panel 100. The control terminal is connected to the gate line GL, the input terminal is connected to the data line DL, Is connected to the liquid crystal capacitors Clca and Clcb and the storage capacitor Cst.

The liquid crystal capacitors Clca and Clcb are formed by connecting the sub-pixel electrode PEa / PEb of the lower panel 100 and the common electrode CE of the upper panel 200 as two terminals, And the liquid crystal layer 3 between the electrodes CE function as a dielectric. The pair of sub-pixel electrodes PEa and PEb are separated from each other and form one pixel electrode PE. The common electrode CE is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. 2, the common electrode 270 may be provided on the lower panel 100. At this time, at least one of the two electrodes 191 and 270 may be linear or bar-shaped. The liquid crystal layer 3 may have a negative dielectric anisotropy and the liquid crystal molecules of the liquid crystal layer 3 may be oriented so that their long axes are perpendicular to the surface of the two display plates in the absence of an electric field.

The storage capacitor Cst serving as an auxiliary capacitor of the liquid crystal capacitor Clc is formed by superimposing a separate signal line (not shown) and a pixel electrode 191 provided on the lower panel 100 with an insulator interposed therebetween, A predetermined voltage such as the common voltage Vcom is applied to the separate signal lines. However, the storage capacitor Cst can be formed by overlapping the pixel electrode PE with the preceding gate line immediately above via an insulator.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of primary colors (space division), or each pixel PX alternately displays a basic color (time division) So that the desired color is recognized by the spatial and temporal sum of these basic colors. Examples of basic colors include red, green, and blue. 2 shows that each pixel PX has a color filter 230 indicating one of the basic colors in an area of the upper panel 200 corresponding to the pixel electrode 191 as an example of space division. 2, the color filter 230 may be formed on or below the pixel electrode 191 of the lower panel 100. [

A polarizer (not shown) is provided on the outer surfaces of the display panels 100 and 200, and the polarization axes of the two polarizers can be orthogonal. In the case of the reflection type liquid crystal display device, one of the two polarizers 12 and 22 may be omitted. In case of an orthogonal polarizer, incident light entering the liquid crystal layer 3 without an electric field is blocked.

Referring again to FIG. 1, the gradation voltage generator 800 generates two sets of gradation voltages (or a set of reference gradation voltages) related to the transmittance of the pixel PX. One of the two has a positive value for the common voltage (Vcom) and the other has a negative value.

The gate driver 400 is connected to the gate line of the liquid crystal panel assembly 300 and applies a gate signal Vg formed by a combination of the gate-on voltage Von and the gate-off voltage Voff to the gate line.

The data driver 500 is connected to the data lines D ₁ -D _2m of the liquid crystal panel assembly 300 and selects the gradation voltage from the gradation voltage generator 800 and supplies it as a data signal to the data line D ₁ -D _2m . However, when the gradation voltage generator 800 provides only a predetermined number of reference gradation voltages instead of providing all the voltages for all gradations, the data driver 500 divides the reference gradation voltage and supplies the gradation voltage And selects a data signal among them.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Each of the driving devices 400, 500, 600, and 800 may be directly mounted on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or may be a flexible printed circuit film (not shown) Or may be attached to the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP), or may be mounted on a separate printed circuit board (not shown). Alternatively, these driving devices 400, 500, 600, and 800 may be integrated in the liquid crystal panel assembly 300. In addition, the drivers 400, 500, 600, 800 may be integrated into a single chip, in which case at least one of them, or at least one circuit element constituting them, may be outside of a single chip.

Hereinafter, the structure of such a liquid crystal panel assembly will be described in detail with reference to FIGS. 3 to 9 and FIGS. 1 and 2 described above.

3 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an embodiment of the present invention.

3, the liquid crystal panel assembly according to the present embodiment includes a signal line including a plurality of gate lines GL, a plurality of data lines DLa and DLb and a plurality of sustain electrode lines SL, And a pixel PX.

Each pixel PX includes a pair of subpixels PXa and PXb and each of the subpixels PXa and PXb is connected to the corresponding gate line GL and the data lines DLa / And a storage capacitor Csta / Cstb connected to the switching element Qa / Qb, the liquid crystal capacitor Clca / Clcb connected thereto, and the switching element Qa / Qb and the storage electrode line SL.

Each switching element Qa / Qb is a three-terminal element such as a thin film transistor provided in the lower panel 100. The control terminal is connected to the gate line GL and the input terminal is connected to the data line DLa / DLb And the output terminal is connected to the liquid crystal capacitor Clca / Clcb and the storage capacitor Csta / Cstb.

The storage capacitors Csta and Cstb serving as auxiliary capacitors of the liquid crystal capacitors Clca and Clcb are formed by overlapping the sustain electrode lines SL and the pixel electrodes PE provided on the lower panel 100 with an insulator interposed therebetween A predetermined voltage such as the common voltage Vcom is applied to the sustain electrode line SL. However, the storage capacitors Csta and Cstb may be formed by superposing the sub-pixel electrodes PEa and PEb on the immediately preceding gate line via an insulator.

The liquid crystal capacitors (Clca, Clcb) and the like have been described above, and a detailed description thereof will be omitted.

In the liquid crystal display device including such a liquid crystal display panel assembly, the signal controller 600 receives the input image signals R, G, and B for one pixel PX and outputs the signals PXa and PXb for the two sub- Converted into a video signal (DAT), and transmitted to the data driver 500. Alternatively, the gradation voltage generator 800 may separately generate a set of gradation voltages for the two sub-pixels PXa and PXb and alternately provide the set of gradation voltages to the data driver 500. Alternatively, Different voltages can be applied to the sub-pixels PXa and PXb. However, it is preferable to correct the image signal so that the composite gamma curve of the two sub-pixels PXa and PXb is close to the reference gamma curve at the front, or to form a gray scale voltage set. For example, the composite gamma curve at the front is coincident with the reference gamma curve at the front determined best for this liquid crystal panel assembly, and the composite gamma curve at the side is closest to the reference gamma curve at the front.

Various arrangements of such a liquid crystal panel assembly will now be described in detail with reference to FIGS. 4 and 5. FIG.

FIG. 4 is a diagram illustrating pixel layout of a liquid crystal panel assembly according to an exemplary embodiment of the present invention. Referring to FIG.

Referring to FIG. 4, the data voltages (for example, D _j and D _{j +1} ) connected to the pair of sub-pixel electrodes PEa and PEb constituting one pixel electrode PE The polarities are opposite. That is, the polarity of the data voltage flowing in the data line D _j located on the left side with respect to one pixel electrode PE is positive (+), and the polarity of the data voltage flowing in the data line D _{j +} The polarity of the voltage is negative (-). However, the polarities of the data voltages flowing in the two data lines (for example, D _{j + 1} and D _{j + 2} ) arranged between two adjacent pixel electrodes PE are the same. As a result, a plurality of data lines D _j , _{J +1} polarity of the D, D _{j +2, +3} D _j, D _{j +4, +5} D _j, D _{j + 6,} D _{j +7, +8} D _j) is "+, -, - , +, +, -, -, + 'after the same polarity is repeated once. Since the polarities of the adjacent data lines are the same, the load of the data line is reduced, so that the charging delay of the data voltage can be prevented and the driving margin of the data driver 500 is increased.

Each first sub-pixel electrode PEa is connected to the first switching device Qa and each second sub-pixel electrode PEb is connected to the second switching device Qb.

The first switching element Qa is connected to the data lines D _j and D _{j +2} located on the left side of the pixel electrodes PE, D _{j +4} , Is connected to the D _{j + 6),} the second switching device (Qb) is data which is located on the right side relative to the pixel electrodes (PE) line _{(D j + 1, D j} + 3, D j +5, D j ₊₇ ). Hereinafter, a pixel having such a connection relationship is referred to as a first pixel PXa.

The first switching element Qa is connected to the right data lines D _{j +1} , D _{j +3} , and D _j with respect to each pixel electrode PE, _+5, and is connected to D _{j + 7),} the second switching device (Qb) is data which is located on the left relative to the pixel electrodes (PE) line (D _j, D _{j + 2,} D _{j +4} , D _{j + 6} ). Hereinafter, a pixel having such a connection relationship is referred to as a second pixel PXb.

In the third row, the first pixels PXa are repeatedly arranged in the same manner as the first row, and the second pixels PXb are repeatedly arranged in the fourth row as in the second row.

4, the row including the first pixel PXa and the row including the second pixel PXb are alternately arranged.

Accordingly, the polarities of the first and second sub-pixel electrodes PEa and PEb adjacent in the row direction are opposite to each other. The polarities of the first sub-pixel electrodes PEa adjacent to each other in the column direction are also opposite to each other, and the polarities of the second sub-pixel electrodes PEb adjacent to each other in the column direction are also opposite to each other.

FIG. 5 is a diagram illustrating pixel layout of a liquid crystal panel assembly according to another embodiment of the present invention.

The liquid crystal panel assembly of FIG. 5 includes two data lines (for example, D _j and D _{j + 1} ) connected to a pair of sub-pixel electrodes PEa and PEb forming a pixel electrode PE ) Are opposite to each other. The polarities of the data voltages flowing through two data lines (for example, D _{j +1} and D _{j + 2} ) disposed between adjacent two pixel electrodes PE are the same.

Each first sub-pixel electrode PEa is connected to the first switching device Qa and each second sub-pixel electrode PEb is connected to the second switching device Qb.

Referring to the pixel electrode PE disposed in the first row, the first pixel PEa is repeatedly arranged in the same manner as the first row of the liquid crystal panel assembly of FIG.

However, unlike FIG. 4, the second row has the first pixels PEa repeatedly arranged like the first row. In the third row, the second pixel PXb is repeatedly arranged in the same manner as the second row in FIG. 4, and the fourth row is the same as the third row.

That is, the row including the first pixel PXa and the row including the second pixel PXb are repeatedly arranged twice.

Accordingly, the polarities of the first and second sub-pixel electrodes PEa and PEb adjacent in the row direction are opposite to each other. However, the polarities of the first sub-pixel electrodes PEa adjacent in the column direction are changed twice and the polarities of the second sub-pixel electrodes PEb adjacent in the column direction are also changed twice and the same. That is, the polarities of the first sub-pixel electrode PEa or the second sub-pixel electrode PEb adjacent to each other in the column direction are represented by "++ -" or "++".

Now, a liquid crystal panel assembly according to an embodiment of the present invention will be described in detail with reference to FIGS. 6 to 11. FIG.

FIG. 6 is a layout diagram of a thin film transistor panel of a second pixel PXb in a liquid crystal display according to an embodiment of the present invention, and FIG. 7 is a cross-sectional view of a second pixel PXb among liquid crystal display devices according to an embodiment of the present invention. 8 is a layout diagram of a liquid crystal display device comprising a thin film transistor panel of FIG. 6 and a common electrode panel of FIG. 7, and FIGS. 9 and 10 are views of a second pixel PXb shown in FIG. Sectional view taken along lines IX-IX and X-X.

A liquid crystal display according to an embodiment of the present invention includes a thin film transistor display panel 100, a common electrode panel 200 facing the same, and a liquid crystal layer 3 interposed between the two display panels 100 and 200.

First, the thin film transistor display panel 100 will be described in detail with reference to FIGS. 6, 8, 9, and 10. FIG.

A plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on an insulating substrate 110 made of transparent glass or the like.

The gate lines 121 extend mainly in the lateral direction and are separated from each other and transfer gate signals. Each gate line 121 includes a plurality of protrusions constituting a plurality of gate electrodes 124a and 124b and a wide end portion 129 for connection with another layer or an external driving circuit.

The sustain electrode line 131 extends mainly in the lateral direction and includes a plurality of protrusions constituting the sustain electrode 137. A predetermined voltage such as a common voltage Vcom applied to a common electrode 270 of the common electrode panel 200 of the liquid crystal display is applied to the sustain electrode line 131. [

The gate line 121 and the storage electrode line 131 may be formed of a metal of aluminum series such as aluminum (Al) and aluminum alloy, a series metal of silver (Ag) and silver alloy, a copper series metal such as copper , Molybdenum metal such as molybdenum (Mo) and molybdenum alloy, chromium (Cr), titanium (Ti), tantalum (Ta). However, the gate line 121 and the sustain electrode line 131 may have a multi-film structure including two conductive films (not shown) having different physical properties. One conductive film may be formed of a metal having a low resistivity such as an aluminum-based metal, a silver-based metal, a copper-based metal, or the like so as to reduce signal delay or voltage drop of the gate line 121 and the storage electrode line 131 Is made. Alternatively, the other conductive film may be made of a material having excellent contact properties with other materials, especially ITO (indium tin oxide) and IZO (indium zinc oxide), such as molybdenum metal, chromium, titanium, tantalum and the like. A good example of such a combination is a chromium bottom film, an aluminum (alloy) top film, an aluminum (alloy) bottom film and a molybdenum (alloy) top film. However, the gate line 121 and the sustain electrode line 131 may be made of various metals and conductors.

It is preferable that the side surfaces of the gate line 121 and the storage electrode line 131 are inclined with respect to the surface of the substrate 110 and the inclination angle thereof is about 30-80 °.

A gate insulating layer 140 made of silicon nitride (SiNx) or the like is formed on the gate line 121 and the sustain electrode line 131.

On the gate insulating film 140 are formed a plurality of island-like semiconductors 154a and 154b made of hydrogenated amorphous silicon (abbreviated as a-Si for amorphous silicon) or polysilicon.

A plurality of island-shaped resistive ohmic contacts 163b and 165b made of a material such as n + hydrogenated amorphous silicon having a high concentration of silicide or n-type impurities such as phosphorus are formed on the semiconductors 154a and 154b . The island-like resistive contact members 163b and 165b are respectively disposed on the semiconductors 154a and 154b in pairs.

The side surfaces of the semiconductors 154a and 154b and the resistive contact members 163b and 165b are inclined with respect to the surface of the substrate 110 and the inclination angle thereof is 30-80 degrees.

A plurality of pairs of first and second data lines 171a and 171b and a plurality of pairs of first and second drain electrodes are formed on the resistive contact members 163b and 165b and the gate insulating layer 140 175a and 175b, and a plurality of pairs of first and second electrode members 177a and 177b.

The data lines 171a and 171b extend mainly in the vertical direction and intersect the gate line 121 and the sustain electrode line 131 to transmit a data voltage. The data lines 171a and 171b are connected to a plurality of source electrodes 173a and 173b extending toward the gate electrodes 124a and 124b and a plurality of source electrodes 173a and 173b, Portions 179a and 179b.

The drain electrodes 175a and 175b are separated from the data lines 171a and 171b and face the source electrodes 173a and 173b around the gate electrodes 124a and 124b, respectively.

The first and second drain electrodes 175a and 175b each have a rod end located above the semiconductor 154a and 154b and the rod end is partially surrounded by U-shaped source electrodes 173a and 173b.

The first drain electrode 175a extends from the end of the bar-shaped portion and extends substantially parallel to the first data line 171a, is bent counterclockwise vertically and extends in parallel with the gate line 124, Section 174a. The first drain electrode 175a includes a branch portion 178a projecting vertically in the counterclockwise direction near the rod end portion and an extension portion 176a extending in the counterclockwise direction in the extension portion 174a do.

The second drain electrode 175b extends in parallel to the gate line 124 in a clockwise direction at the end of the rod end and extends in the direction of the extension 174b and the extension 174b, Lt; / RTI >

The first and second electrode members 177a and 177b are formed apart from the first and second drain electrodes 175a and 175b and overlap the sustain electrode 137. [

The first / second gate electrode 124a / 124b, the first / second source electrode 173a / 173b and the first / second drain electrode 175a / 175b are connected to the first / And a channel of the thin film transistor Qa / Qb is connected to the first / second source electrode 173a / 173b and the first / second thin film transistor (TFT) Drain electrodes 175a / 175b of the semiconductor layers 154a / 154b.

The data lines 171a and 171b, the drain electrodes 175a and 175b and the first and second electrode members 177a and 177b are made of a refractory metal such as molybdenum, chromium, tantalum and titanium or an alloy thereof And may have a multi-film structure including a refractory metal film (not shown) and a low-resistance conductive film (not shown). Examples of the multilayer structure include a double film of a chromium or molybdenum (alloy) lower film and an aluminum (alloy) upper film, a molybdenum (alloy) lower film, an aluminum (alloy) intermediate film and a molybdenum (alloy) lower film. However, the data line 171 and the drain electrodes 1175a and 175b may be made of various other metals or conductors.

The side surfaces of the data lines 171a and 171b and the drain electrodes 175a and 175b and the first and second electrode members 177a and 177b are formed at a side surface of about 30-80 ° Respectively.

On the other hand, the interval between the adjacent two data lines 171a and 171b is kept to a minimum interval considering the manufacturing process capability and the yield, thereby minimizing the reduction of the aperture ratio due to the increase in the number of the data lines 171a and 171b.

The resistive contact member 165b is present only between the semiconductor layers 151a and 151b and the data lines 171a and 171b and the drain electrodes 175a and 175b on the lower part thereof and serves to lower the contact resistance.

A passivation layer 180 is formed on the data lines 171a and 171b, the drain electrodes 175a and 175b, the first and second electrode members 177a and 177b, and the exposed semiconductor layers 154a and 154b. . The protective film 180 is made of an inorganic insulating material such as silicon nitride or silicon oxide, an organic insulating material, or a low dielectric constant insulating material. The dielectric constant of the organic insulating material and the low dielectric constant insulating material is preferably 4.0 or less, and examples of the low dielectric insulating material include a-Si: C: O, a-Si: O which is formed by plasma enhanced chemical vapor deposition (PECVD) : F and the like. The protective film 180 may be made of photosensitivity among organic insulating materials, and the surface of the protective film may be flat. However, the protective film 180 may have a bilayer structure of the lower inorganic film and the upper organic film so as to prevent the exposed portions of the semiconductors 154a and 154b while making good use of the insulating property of the organic film.

The protective film 180 is provided with a plurality of contact holes 182a, 182b and 185a for exposing the end portions 179a and 179b of the data lines 171a and 171b and the first and second electrode members 177a and 177b, A plurality of contact holes 181 are formed in the passivation layer 180 and the gate insulating layer 140 to expose the end portions 129 of the gate lines 121.

A plurality of pixel electrodes 191 including first and second subpixel electrodes 191a and 191b, shielding electrodes (not shown), and a plurality of A contact assistant 81, 82a, 82b of the contact member 80 is formed. These are made of a transparent conductive material such as ITO or IZO, or a reflective metal such as aluminum, silver or an alloy thereof.

The first and second sub-pixel electrodes 191a and 191b are electrically and physically connected to the first and second drain electrodes 175a and 175b through the contact holes 185a and 185b, RTI ID = 0.0 > 175a / 175b. ≪ / RTI > Different data voltages previously set for one input video signal are applied to the pair of sub-pixel electrodes 191a and 191b, and the size thereof is set according to the size and shape of the sub-pixel electrodes 191a and 191b . The areas of the sub-pixel electrodes 191a and 191b may be different from each other. For example, the second sub-pixel electrode 191b receives a higher voltage than the first sub-pixel electrode 191a and has a smaller area than the first sub-pixel electrode 191a.

The data voltages applied to the sub-pixel electrodes 191a and 191b together with the common electrode 270 generate an electric field to determine the alignment of the liquid crystal molecules in the liquid crystal layer 3 between the two electrodes 191a / 191b and 270. [

As described above, the sub-pixel electrodes 191a and 191b and the common electrode 270 constitute liquid crystal capacitors Clca and Clcb to maintain the applied voltage even after the thin film transistors Qa and Qb are turned off. The storage capacitor Csta.Cstb connected in parallel with the liquid crystal capacitors Clca and Clcb is connected to the first and second sub-pixel electrodes 191a and 191b and the first and second electrodes 191a and 191b connected thereto, Overlapping the members 177a and 177b and the sustain electrode 137, and the like.

Each pixel electrode 191 has a substantially rectangular outer boundary.

A pair of first and second sub-pixel electrodes 191a and 191b constituting one pixel electrode 191 are interdigitated with a gap 94 therebetween, and the first sub-pixel electrode 191a And is inserted in the center of the second sub-pixel electrode 191b.

The second sub-pixel electrode 191b is formed with a central cutout 91, upper cutouts 92a and 93a and lower cutouts 92b and 93b. The second sub- Are partitioned into a plurality of partitions by a plurality of optical fibers 91 to 93b. The cutout portions 91 to 93b are substantially inversely symmetrical with respect to the sustain electrode line 131. [

The lower and upper cutouts 92a to 93b extend obliquely from the right side of the pixel electrode 191 to the left side, the upper side, or the lower side. The lower and upper cutouts 92a to 93b are located at the lower half and upper half of the sustain electrode line 131, respectively. The lower and upper cutouts 92a to 93b extend perpendicularly to each other at an angle of about 45 with respect to the gate line 121. [

The central cutout portion 91 extends along the sustain electrode line 131 and has an inlet on the left side. The central incision 91 includes a central transverse portion and a pair of oblique portions. The central transverse portion extends approximately from the right side of the pixel electrode 191 to the left along the storage electrode line 131 and the pair of oblique portions extend from the end of the central transverse portion toward the left side of the pixel electrode 191, Extending substantially in parallel with the portions 92a to 93b.

The lower half of the pixel electrode 191 is divided into five regions by the central cutout 91, the gap 94 and the lower cutouts 92b and 93b and the upper half is also divided into the central cutout 91, The gap 94, and the lower cutouts 92b and 93b. In this case, the number of regions or the number of cut-out portions may vary depending on design factors such as the size of the pixel, the length ratio of the transverse and longitudinal sides of the pixel electrode, and the type and characteristics of the liquid crystal layer 3.

The contact assistants 81 and 82 are connected to the end portion 129 of the gate line 121 and the end portion 179 of the data line 171 through the contact holes 181 and 182, respectively. The contact assistant members 81 and 82 complement and protect the adhesion between the data line 171 and the end portions 179 and 129 of the gate line 121 and the external device.

Next, the common electrode display panel 200 will be described with reference to Figs. 7, 8, and 9. Fig.

A light blocking member 220 is formed on an insulating substrate 210 made of transparent glass or plastic. The light shielding member 220 is also called a black matrix and blocks light leakage. The light shielding member 220 includes a linear portion 221 corresponding to the data line 171 and a planar portion corresponding to the thin film transistor and has a light shielding portion between the pixel electrode 191 and the opening facing the pixel electrode 191 Define the area. However, the light shielding member 220 may have a plurality of openings (not shown) facing the pixel electrode 191 and having substantially the same shape as the pixel electrode 191.

A plurality of color filters 230 are further formed on the substrate 210. The color filter 230 is mostly present in a region surrounded by the light shielding member 230 and can be elongated in the longitudinal direction along the column of the pixel electrodes 191. Each color filter 230 may display one of the primary colors, such as the three primary colors of red, green, and blue.

An overcoat 250 is formed on the color filter 230 and the light shielding member 220. The cover film 250 can be made of (organic) insulation and prevents the color filter 230 from being exposed and provides a flat surface. The cover film 250 may be omitted.

A common electrode 270 is formed on the lid 250. The common electrode 270 is made of a transparent conductor such as ITO or IZO.

The common electrode 270 is formed with a plurality of cutouts 71, 72, 73a, 73b, 74a, 74b.

One set of cutouts 71 to 74b faces one pixel electrode 191 and includes first and second central cutouts 71 and 72, upper cutouts 73a and 74a, and lower cutouts 73b and 73b. 74b. Each of the cutouts 71 to 74b is disposed between adjacent cutouts 91 to 94b of the pixel electrode 191. [ Each cutout portion 71 to 74b includes at least one oblique branch extending in parallel with the lower cutout portions 93a and 94a or the upper cutouts 93b and 94b of the pixel electrode 191. [

Each of the lower and upper cutouts 73a-74b includes a diagonal branch, a horizontal branch, and a vertical branch. The oblique line extends substantially in parallel with the lower or upper cutout portions 92a to 93b of the pixel electrode 191 to the left, upper, or lower side on the right side of the pixel electrode 191. [ The horizontal and vertical branches extend from the respective ends of the oblique branch along the sides of the pixel electrode 191 and form an obtuse angle with an oblique branch.

The first and second central cutouts 71 include a central transverse branch, a pair of diagonal branch branches, and a pair of longitudinal branch branches. The center horizontal line extends approximately from the right side of the pixel electrode 191 to the left along the horizontal center line of the pixel electrode 191 and the pair of diagonal lines extends from the end of the center horizontal line toward the left side of the pixel electrode 191 And extend substantially in parallel with the lower and upper cutouts 73a, 73b, 74a, and 74b. The vertical longitudinal branch extends from the respective ends of the oblique branch to the left side of the pixel electrode 191 while overlapping the oblique branch and forming an obtuse angle.

A triangular notch is formed in the hatched portion of the cutouts 71-74b. These notches may have a rectangular, trapezoidal or semicircular shape and may be convex or concave. These notches determine the alignment direction of the liquid crystal molecules 3 positioned at the region boundaries corresponding to the cutouts 71-74b.

The number and direction of the cutouts 71-74b may also vary depending on the design element.

Alignment layers 11 and 21 are coated on the inner surfaces of the display panels 100 and 200 and may be vertical alignment layers.

Polarizers 12 and 22 are provided on the outer surfaces of the display panels 100 and 200. The transmission axes of the two polarizers 12 and 22 are orthogonal and one of the transmission axes is parallel to the gate line 121 desirable.

The liquid crystal display device may include polarizers 12 and 22, display panels 100 and 200, and a backlight unit (not shown) that supplies light to the liquid crystal layer 3.

The liquid crystal layer 3 has a negative dielectric anisotropy and the liquid crystal molecules of the liquid crystal layer 3 are oriented such that their long axes are perpendicular to the surfaces of the two display panels 100 and 200 in the absence of an electric field. Therefore, the incident light is blocked without passing through the orthogonal polarizers 12 and 22.

When a common voltage is applied to the common electrode 270 and a data voltage is applied to the pixel electrode 191, an electric field (electric field) substantially perpendicular to the surfaces of the display panels 100 and 200 is generated. Liquid crystal molecules are oriented in response to an electric field so that their long axes are perpendicular to the direction of the electric field. In the following, the pixel electrode 191 and the common electrode 271 are collectively referred to as an electric field generating electrode.

On the other hand, the cutouts 91 to 93b of the pixel electrodes of the electric field generating electrodes 191 and 270 and the cutouts 71 to 74b of the common electrode and the hypotenuse of the pixel electrode 191 parallel to these cuts the electric field, It produces a horizontal component that determines the direction of the slope of the molecules. The horizontal component of the electric field is perpendicular to the hypotenuse of the cutouts 91 to 93b and 71 to 74b and the hypotenuse of the pixel electrode 191. [

1, one common electrode cutout set 71 to 74b and a pixel electrode cutout set 91 to 93b divides the pixel electrode 191 into a plurality of sub-areas, Region has two major edges oblique to the periphery of the pixel electrode 191. Since most of the liquid crystal molecules on each sub-region are tilted in the direction perpendicular to the circumference, the direction of tilting is approximately four directions. When the direction in which the liquid crystal molecules are tilted is varied in this way, the reference viewing angle of the liquid crystal display device is increased.

At least one cutout 91-93b, 71-74b may be replaced by a protrusion or depression, and the shape and arrangement of the cutouts 91-93b, 71-74b may be modified.

A first pixel PXa of the liquid crystal display according to an embodiment of the present invention will now be described in detail with reference to FIG.

11 is a layout diagram of a first pixel PXa in a liquid crystal display according to an embodiment of the present invention.

11, the first pixel PXa of the liquid crystal display device according to an embodiment of the present invention is also provided between a lower panel (not shown) and an upper panel (not shown) And a liquid crystal layer (not shown).

The layered structure of the liquid crystal panel assembly according to this embodiment is generally the same as the layered structure of the liquid crystal panel assembly shown in Figs. 6 to 10.

Describing the lower display panel, a plurality of gate conductors including a plurality of gate lines 121 and a plurality of sustain electrode lines 131 is formed on an insulating substrate (not shown). Each gate line 121 includes a gate electrode 124 and an end portion 129 and each sustain electrode line 131 includes a sustain electrode 137. A gate insulating film (not shown) is formed on the gate conductors 121 and 131. First and second island-shaped semiconductors 154a and 154b are formed on the gate insulating film, and a plurality of resistive contact members (not shown) are formed thereon. A plurality of first and second data lines 171a and 171b and a plurality of first and second drain electrodes 175a and 175b and first and second electrode members 177a and 177b are formed on the resistive contact member and the gate insulating film, A data conductor is formed. The first and second data lines 171a and 171b include a plurality of first and second source electrodes 173a and 173b and end portions 179a and 179b. A protective film (not shown) is formed on the portions of the data conductors 171a, 171b, 175a, 175b, 177a and 177b and the exposed semiconductor 154. A plurality of contact holes 181, 182a, 182b, 185a, 185b, 187a, 187b are formed. On the protective film, first and second sub-pixel electrodes 191a and 191b and a plurality of contact assistants 81 and 82 are formed. An alignment film (not shown) is formed on the pixel electrode 191, the contact assistants 81 and 82, and the protective film.

The first pixel PXa shown in FIG. 11 differs from the second pixel PXb shown in FIG. 6 through FIG. 10 in that a first data line 171a is provided on the left side of the pixel electrode 191, A line 171b is disposed. That is, the first thin film transistor Qa including the first semiconductor 154a, the first source electrode 173a, and the first drain electrode 175a is disposed on the left side of the pixel electrode 191 and the second semiconductor 154b, The second source electrode 173b and the second drain electrode 175b is disposed on the right side of the pixel electrode 191. The second thin film transistor Qb is formed on the right side of the pixel electrode 191. [

The first drain electrode 175a extends from the end of the rod end to extend substantially parallel to the first data line 171a and extend in parallel with the gate line 124 in a clockwise direction, (174a). The first drain electrode 175a also has a branch portion 178c protruding clockwise vertically near the rod end and an extension portion 174c bent in the clockwise direction and then vertically bent clockwise again in the extension portion 174a 176c.

The second drain electrode 175b extends in parallel to the gate line 124 in a counterclockwise direction perpendicular to the rod end and extends in the direction of the extension 174b and the extension 174b, And a portion 176d.

8 and 11, although the positions of the first and second data lines 171a and 171b and the first and second thin film transistors Qa and Qb are different from each other, the first and second drain electrodes 175a , 175b are substantially the same. That is, the electro-optical characteristics of the pixels PXa and PXb are different from those of the pixel electrodes 191 and the first and second thin film transistors Qa and Qb in the first and second pixels PXa and PXb, Can be adjusted in the same manner. Therefore, there is no difference in luminance or the like in the front view or the viewing angle direction of each of the first and second pixels PXa and PXb.

Although the first and second drain electrodes 175a and 175b have been described with reference to FIGS. 8 and 11, the present invention is not limited to this, and the planar shape of the first and second pixels PXa and PXb These same many forms can be employed variously.

The display operation of such a liquid crystal display device will now be described in detail.

Referring again to FIG. 1, the signal controller 600 receives an input control signal for controlling the display of the input image signals R, G, and B from an external graphic controller (not shown), for example, a vertical synchronization signal Vsync A horizontal synchronizing signal Hsync, a main clock MCLK, a data enable signal DE, and the like. G and B on the basis of the input image signals R, G and B of the signal controller 600 and the input control signals according to the operating conditions of the liquid crystal panel assembly 300, The data driver 500 generates the signal CONT1 and the data control signal CONT2 and then outputs the gate control signal CONT1 to the gate driver 400 and the video signal DAT processed with the data control signal CONT2 to the data driver 500 ).

The gate control signal CONT1 includes a scan start signal STV indicating the start of scanning of the gate on voltage Von and a gate clock signal CPV controlling the output timing of the gate on voltage Von and a gate on voltage Von An output enable signal OE that defines the width of the output enable signal OE, and the like.

The data control signal CONT2 includes a horizontal synchronization start signal STH for notifying the transfer of data to the sub-pixels PXa and PXb of one row and a load signal STS for applying the corresponding data voltage to the data lines D _{1 to} D _2m . (LOAD) and a data clock signal (HCLK). The data control signal CONT2 also includes an inverted signal RVS for inverting the polarity of the data voltage to the common voltage Vcom (hereinafter referred to as "polarity of the data voltage with respect to the common voltage" .

The data driver 500 sequentially receives and shifts the image data DAT for the sub-pixels PXa and PXb of one row according to the data control signal CONT2 from the signal controller 600, 800 to convert the image data DAT into corresponding analog data voltages, and applies the analog data voltages to the corresponding data lines D ₁ -D _2m .

The gate driver 400 sequentially applies the gate-on voltage Von to the gate lines G ₁ -G _n in accordance with the gate control signal CONT 1 from the signal controller 600 to sequentially apply the gate lines G ₁ -G _n The switching elements Qa and Qb connected to the data lines D _{1 to} D _2m are turned on so that the data voltages applied to the data lines D _{1 to} D _2m are applied to the corresponding subpixels PXa and PXb .

The difference between the data voltage applied to the sub-pixels PXa and PXb and the common voltage Vcom is supplied to each of the liquid crystal capacitors C _LCa , C _LCb ), i.e., the sub pixel voltage. The liquid crystal molecules have different arrangements according to the magnitude of the sub-pixel voltage, and thus the polarization of light passing through the liquid crystal layer 3 changes. Such a change in polarization is caused by a change in the transmittance of light by the polarizers 12 and 22 attached to the display panels 100 and 200.

One input image data is converted into a pair of output image data, which gives different transmittances to the pair of subpixels PXa and PXb. Therefore, the two subpixels PXa and PXb represent different gamma curves, and the gamma curve of one pixel PX is a composite curve thereof. The composite gamma curve at the front is made to coincide with the reference gamma curve at the front determined to be most suitable, and the composite gamma curve at the side is made closest to the reference gamma curve at the front. By converting the image data as described above, the side viewability is improved. As described above, since the area of the second sub-pixel electrode 191b, which receives a relatively high data voltage, is made smaller than the area of the first sub-pixel electrode 191a, the distortion of the composite gamma curve at the side can be reduced .

After one horizontal period (or "1H ") (one cycle of the horizontal synchronization signal Hsync and the data enable signal DE), the data driver 500 and the gate driver 400 drive the sub- PXb are repeated. In this manner, the gate-on voltage Von is sequentially applied to all the gate lines G ₁ -G _n during one frame to apply the data voltage to all the sub-pixels PXa and PXb. At the end of one frame, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 so that the polarity of the data voltage applied to each of the sub-pixels PXa and PXb is opposite to the polarity of the previous frame ("Frame inversion").

In addition to the frame inversion, the data driver 500 inverts the polarity of the data voltage that rides on the neighboring data lines D ₁ -D _2m within one frame, and accordingly the polarity of the sub-pixel voltage applied with the data voltage also changes . The polarity reversal pattern of the data driver 500 and the polarity reversal pattern of the sub pixel voltage appearing on the screen of the liquid crystal panel assembly 300 are changed according to the connection relationship between the data driver 500 and the data lines D _{1 to} D _2m Appear differently. Hereinafter, the inversion in the data driver 500 is referred to as " driver inversion ", and the inversion on the screen is referred to as "apparent inversion ". The polarity of the subpixel voltage in the subpixels PXa and PXb is referred to as the polarity of the subpixels PXa and PXb and the polarity of the pixel voltage in the pixel PX is referred to as the pixel PX) ".

Since the polarity of the first and second sub-pixel electrodes PEa and PEb is described in FIGS. 4 and 5, the description of the apparent inversion of the liquid crystal display according to various embodiments of the present invention is omitted.

Now, another embodiment of the present invention will be described in detail with reference to FIGS. 12 to 14. FIG.

FIG. 12 is a layout diagram showing a second pixel PXb of a liquid crystal display device according to another embodiment of the present invention, and FIG. 13 is a cross-sectional view of the liquid crystal display device of FIG. 12 cut along the line XIII-XIII.

12 and 13, the second pixel PXb of the liquid crystal display according to an embodiment of the present invention also includes a lower display panel (not shown) and an upper display panel (not shown) facing each other, And a liquid crystal layer (not shown) interposed therebetween.

The layered structure of the liquid crystal panel assembly according to this embodiment is generally the same as the layered structure of the liquid crystal panel assembly shown in Figs. 6 to 10.

Describing the lower display panel, a plurality of gate conductors including a plurality of gate lines 121 and a plurality of sustain electrode lines 131 is formed on an insulating substrate (not shown). Each gate line 121 includes a gate electrode 124 and an end portion 129 and each sustain electrode line 131 includes a sustain electrode 137. A gate insulating film (not shown) is formed on the gate conductors 121 and 131. First and second island-shaped semiconductors 154a and 154b are formed on the gate insulating film, and a plurality of resistive contact members (not shown) are formed thereon. A plurality of first and second data lines 171a and 171b and a plurality of first and second drain electrodes 175a and 175b and first and second electrode members 177a and 177b are formed on the resistive contact member and the gate insulating film, A data conductor is formed. The first and second data lines 171a and 171b include a plurality of first and second source electrodes 173a and 173b and end portions 179a and 179b. A protective film (not shown) is formed on the data conductors 171a, 171b, 175a and 175b and the exposed semiconductor 154, and a plurality of contact holes 181, 182a, 182b, 185a, 185b are formed. On the protective film, first and second sub-pixel electrodes 191a and 191b and a plurality of contact assistants 81 and 82 are formed. An alignment film (not shown) is formed on the pixel electrode 191, the contact assistants 81 and 82, and the protective film.

In the liquid crystal display device shown in Fig. 12, the protection film 180 is removed at a portion where the sustain electrode 137 and the electrode members 177a and 177b overlap, unlike Fig. That is, only the gate insulating film 140 exists between the sustain electrode 137 and the electrode members 177a and 177b. Further, no contact hole for connecting the pixel electrode 191 and the electrode members 177a and 177b is formed.

The storage capacitor Cst is formed by the sustain electrode 137 and the electrode members 177a and 177b with the gate insulating film 140 as a dielectric and the distance between the sustain electrode 137 and the electrode members 177a and 177b 8, the voltage holding ability is improved.

Referring now to FIG. 14, a second pixel PXb of a liquid crystal display according to another embodiment of the present invention will be described.

14 is a layout diagram showing a first pixel PXa of a liquid crystal display according to another embodiment of the present invention.

14, a first pixel PXa of a liquid crystal display according to an exemplary embodiment of the present invention may also include a lower display panel (not shown) and an upper display panel (not shown) And a liquid crystal layer (not shown).

The layered structure of the liquid crystal panel assembly according to this embodiment is generally the same as the layered structure of the liquid crystal panel assembly shown in Figs. 6 to 10.

Describing the lower display panel, a plurality of gate conductors including a plurality of gate lines 121 and a plurality of sustain electrode lines 131 is formed on an insulating substrate (not shown). Each gate line 121 includes a gate electrode 124 and an end portion 129 and each sustain electrode line 131 includes a sustain electrode 137. A gate insulating film (not shown) is formed on the gate conductors 121 and 131. First and second island-shaped semiconductors 154a and 154b are formed on the gate insulating film, and a plurality of resistive contact members (not shown) are formed thereon. A plurality of first and second data lines 171a and 171b and a plurality of first and second drain electrodes 175a and 175b and first and second electrode members 177a and 177b are formed on the resistive contact member and the gate insulating film, A data conductor is formed. The first and second data lines 171a and 171b include a plurality of first and second source electrodes 173a and 173b and end portions 179a and 179b. A protective film (not shown) is formed on the data conductors 171a, 171b, 175a and 175b and the exposed semiconductor 154, and a plurality of contact holes 181, 182a, 182b, 185a, 185b are formed. On the protective film, first and second sub-pixel electrodes 191a and 191b and a plurality of contact assistants 81 and 82 are formed. An alignment film (not shown) is formed on the pixel electrode 191, the contact assistants 81 and 82, and the protective film.

In the second pixel PXb of FIG. 14, the protective film 180 is removed at a portion where the sustain electrode 137 and the electrode members 177a and 177b overlap, like the first pixel PXa of FIGS. 12 and 13 The voltage holding ability of the holding capacitor is improved.

12 and 13 and the first pixel PXa of FIG. 14 are the same as the second pixel PXb of FIGS. 6 to 10 and the first pixel PXa of FIG. 11, the second pixel PXb of FIG. 1 and the second drain electrodes 175a and 175b are substantially the same. Therefore, even if the connection structures of the first pixel PXa and the second pixel PXb are different, the optical and electrical parameters of the two pixels PXa and PXb can be controlled in the same manner.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, Of the right.

12, 22: Polarizer 11, 21: Orientation film
71, 72, 73a, 73b, 74a, 74b:
81, 82a, 82b:
91, 92a, 92b, 93a, 93b: pixel electrode cut-
94: Clearance
110, 210: substrate 121, 129: gate line
124: gate electrode 131: sustain electrode line
137: sustain electrode 140: gate insulating film
154a, 154b: semiconductor 163b, 165b: resistive contact member
171a, 171b, 179a and 179b: data lines 173a and 173b:
175a, 175b: drain electrode 177a, 177b: electrode member
180: Shield
181, 182a, 182b, 185a, 185b, 187a, 187b:
191, 191a, and 191b:
220: a light shielding member 230: a color filter
250: cover film 270: common electrode
300: liquid crystal panel assembly 400: gate driver
500: Data driver 600: Signal controller
800: a gradation voltage generating section

Claims (10)

A liquid crystal display device comprising a first pixel and a second pixel,
A plurality of gate lines for transmitting gate signals, and
A plurality of pairs of data lines,
Wherein each pair of data lines of the plurality of pairs of data lines includes a first data line and a second data line intersecting with the gate line and the first data line and the second data line are connected to the first pixel and the second pixel Facing each other,
Wherein each of the first pixel and the second pixel includes:
A pixel electrode including a pair of first sub-pixel electrodes and a second sub-pixel electrode, and a pair of first and second drain electrodes,
The first drain electrode is located on the right side of the first data line, the second drain electrode is located on the left side of the second data line,
In the first pixel, the first drain electrode is connected to the first sub-pixel electrode through a first contact hole, and the second drain electrode is connected to the second sub-pixel electrode through a second contact hole ,
In the second pixel, the first drain electrode is connected to the second sub-pixel electrode through a third contact hole, and the second drain electrode is connected to the first sub-pixel electrode through a fourth contact hole ,
The first portion constituted by the first drain electrode and the second drain electrode of the first pixel has substantially the same shape as the second portion constituted by the first drain electrode and the second drain electrode of the second pixel ,
Wherein the first sub-pixel electrode and the second sub-pixel electrode are located on the same side with respect to the gate line,
Wherein the position of the first contact hole in the first pixel and the position of the fourth contact hole in the second pixel are the same and the position of the second contact hole in the first pixel and the position of the second contact hole in the second pixel, 3 The positions of the contact holes are the same,
Wherein the first sub-pixel electrode of the first pixel and the first sub-pixel electrode of the second pixel are the same as each other in the pixel, and the second sub-pixel electrode of the first pixel and the first sub- And the second sub-pixel electrodes of the second pixel are located in the respective pixels. The method of claim 1,
Wherein the first drain electrode and the second drain electrode each include at least one dummy portion,
The dummy portion of the first drain electrode corresponds to the second drain electrode of the second pixel when the dummy portion is included in the first drain electrode of the first pixel,
And when the dummy portion is included in the second drain electrode of the first pixel, the dummy portion of the second drain electrode corresponds to the first drain electrode of the second pixel. 3. The method of claim 2,
Wherein each of the first drain electrode and the second drain electrode of the first pixel or the second pixel includes a contact portion connected to the pixel electrode of the first pixel or the second pixel and the dummy portion extends from the contact portion And at least one first branch formed on the substrate. 4. The method of claim 3,
Wherein the dummy portion includes at least one second branch located between the first drain electrode or the second drain electrode and the contact portion. The method of claim 1,
Wherein the first data voltage applied to the first data line is different from the second data voltage applied to the second data line. The method of claim 1,
Wherein the voltage polarity of the first data line is opposite to the voltage polarity of the second data line. The method of claim 1,
Wherein the first unit and the second unit are alternately arranged in the column direction, the first unit includes at least two first pixels arranged consecutively in the column direction, and the second unit is arranged in the column direction And at least two second pixels successively arranged. The method of claim 1,
Wherein the voltage polarity of the first sub-pixel electrode in the first pixel is opposite to the voltage polarity of the second sub-pixel electrode, and the voltage polarity of the first sub- The liquid crystal display device being opposite to the polarity of the voltage. The method of claim 1,
And the voltage polarities of the first sub-pixel electrodes adjacent to each other in the column direction are different for every column or more columns. The method of claim 1,
And the first sub-pixel electrode of the first pixel or the second pixel has an area different from that of the first sub pixel electrode or the second sub pixel electrode of the second pixel.

Images