KR101389466B1 - Array Substrate for COT type Liquid Crystal Display Device and Method of Fabricating the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a method of manufacturing an array substrate for a liquid crystal display (COT) structure, in which a color filter is formed on the same substrate as a thin film transistor (TFT). It is about.

The present invention solves the problem of leakage current by forming an island-shaped semiconductor layer (particularly an active layer) on the gate electrode without increasing the mask process compared with the conventional method for manufacturing an array substrate for a COT structure liquid crystal display device. In addition, the semiconductor layer is formed so as not to protrude below the data line, thereby solving the problem of noise reduction and aperture ratio reduction.

COT, wave noise, leakage current

Description

Array Substrate for COT type Liquid Crystal Display Device and Method of Fabricating the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and in particular, an array substrate for a liquid crystal display (COT) structure and a method of manufacturing the same, wherein the color filter is formed on the same substrate as a thin film transistor (TFT) as a switching element. It is about.

Generally, the driving principle of a liquid crystal display device utilizes the optical anisotropy and polarization properties of a liquid crystal. Since the liquid crystal has a long structure, it has a directionality in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, when the molecular alignment direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular alignment direction of the liquid crystal by optical anisotropy, so that image information can be expressed.

Currently, an active matrix liquid crystal display device (AM-LCD: abbreviated to an active matrix LCD, abbreviated as a liquid crystal display device) in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner has the best resolution and video performance. It is attracting attention.

The liquid crystal display includes an upper substrate on which color filters, a common electrode, etc. are formed, a lower substrate on which switching elements, pixel electrodes, etc. are formed, and a liquid crystal interposed between the two substrates. It is excellent in characteristics such as transmittance and aperture ratio in such a manner that the liquid crystal is driven by an electric field applied up and down.

In addition, a technique for forming a color filter and a switching element formed on each of the upper and lower substrates on the same substrate has been proposed. This is a so-called COT (Color filter On TFT) structure, in which a color filter is formed on the lower substrate on which the switching element is formed. This aims to improve the aperture ratio by reducing the bonding margin considered in the process of bonding the upper and lower substrates.

A conventional COT structure liquid crystal display device will be described with reference to FIGS. 1 and 2 below.

1 is a plan view illustrating an array substrate of a COT structure hierarchical liquid crystal display device according to the related art.

As illustrated, the array substrate 10 of the COT structure liquid crystal display device is formed on the transparent substrate 12 while the gate wiring 14 and the data wiring 30 cross each other to define the pixel region P. The thin film transistor T is formed at the intersection of the gate line 14 and the data line 30. The thin film transistor T includes a gate electrode 16 semiconductor layer 24, and a source electrode 32 and a drain electrode 34 spaced apart from each other. The semiconductor layer 24 is formed under the source and drain electrodes 32 and 34 and the data line 30, and an active layer (not shown) of the semiconductor layer 24 is a source and drain electrode 32 due to the manufacturing process. 34 and the data line 30 protrude from each other. That is, the active layer (not shown) has a width wider than the widths of the source and drain electrodes 32 and 34 and the data line 30, which causes problems such as leakage current, wave noise, and aperture ratio reduction. The detailed reason is explained with reference to FIGS. 2A to 2G, which illustrate the manufacturing process.

In the pixel region P, a pixel electrode 50 connected to the drain electrode 34 of the thin film transistor T and the first contact hole CH1 is formed. The pixel electrode 50 overlaps the gate wiring 14 of the front end, and has an arrangement in which an island-shaped metal pattern 36 formed below the second electrode hole 36 is connected to the pixel electrode 36. Capacitor Cst is configured. Color filters R, G, and B having any one of red, green, and blue colors are formed in each pixel area P, thereby forming a COT structure liquid crystal display array substrate 10.

As described above, since the color filter, which is usually formed on the upper substrate, is formed on the lower substrate together with the thin film transistor, which is a switching element, due to the characteristics of the COT structure, the upper substrate generally includes a black matrix to cover a non-display area such as a thin film transistor and a pixel electrode. Only the common electrode forming the electric field together with 50 is formed.

2A to 2G are cross-sectional views of manufacturing processes of portions cut along the line II-II of FIG. 1.

In the case of the COT structure in which the color filter is formed on the lower substrate, the number of mask processes is inevitably increased due to the process for forming the color filter. It is formed by the mask process of, which is shown in Figures 2a to 2g.

2A shows a first mask process. As shown, the gate wiring 14 is formed on the substrate 12 by forming a first metal layer (not shown) on the substrate 12 and patterning the first metal layer (not shown) by the first mask process. And a gate electrode 16 connected thereto. The pixel region P on which the pixel electrode is positioned and becomes an image display area on the substrate 12 is defined, the switching region S on which a thin film transistor serving as a switching element is to be formed, and the capacitor region C on which a storage capacitor is to be defined. It is. Therefore, the gate electrode 16 is formed in the switching region S, and the gate wiring 14 is formed in the capacitor region C along the boundary of the pixel region P. As shown in FIG. Subsequently, the gate insulating layer 18 is formed on the entire surface of the substrate 12 while covering the gate electrode 16 and the like.

2B-2D show a second mask process.

As shown in FIG. 2B, the pure amorphous silicon layer 20, the impurity amorphous silicon layer 21, and the second metal layer 22 are sequentially stacked on the gate insulating film 18, and a photoresist layer is formed on the gate insulating film 18. The material is applied to form a photoresist layer (not shown). The mask M having the transmissive part TA, the transflective part HTA, and the blocking part BA is positioned on the photoresist layer (not shown). Here, the transflective portion HTA is smaller than the transmissive portion HT and has a transmittance larger than the cutoff portion BA. By exposing and developing the photoresist layer (not shown) using the mask M including the transflective portion HTA as described above, the first and second thicknesses t1 and t2 are respectively provided, and the blocking portions BA are respectively. ) And the first and second photoresist patterns 72a and 72b are formed at positions corresponding to the X and the transflective portion HTA. The first photoresist pattern 72a is formed in the switching region S and the capacitor region C, and has a second thickness t2 smaller than the first thickness t1 of the first photoresist pattern 72a. The two photoresist pattern 72b is formed corresponding to the center portion of the switching region S, that is, the gate electrode 16. Outside the first and second photoresist patterns 72a and 72b, all of the photoresist layers (not shown) corresponding to the transmission portion TA of the mask M are removed to expose the second metal layer 22.

Next, as shown in FIG. 2C, the second metal layer (22 of FIG. 2B) exposed to the outside of the first and second photoresist patterns (72a and 72b of FIG. 2B) and the impurity amorphous silicon layer below it (FIG. 2B). 21) and the pure amorphous silicon layer (20 of FIG. 2B) are sequentially removed, thereby sequentially depositing the first pure amorphous silicon pattern 20a, the first impurity amorphous silicon pattern 21a, and the first One metal pattern 22a is formed on the gate insulating film 18. At the same time, the second pure amorphous silicon pattern 20b, the second impurity amorphous silicon pattern 21b, and the second metal pattern 22b sequentially stacked on the capacitor region C are formed on the gate insulating film 18. Therefore, the gate insulating film 18 is exposed to the outside in the region where the first and second photoresist patterns 72a and 72b of FIG. 2B are not formed.

Then, the ashing process is performed on the first and second photoresist patterns (72a and 72b of FIG. 2B) to remove the second photoresist pattern (72b of FIG. 2B) having the second thickness to form a gate. The first metal pattern 22a corresponding to the electrode 16 is exposed. At the same time, the first photoresist pattern 72b of FIG. 2B is also ashed to form a third photoresist pattern 72c having a third thickness t3. At this time, the ashing process is also performed on the end surface of the first photoresist pattern (72b of FIG. 2B), so that the first and second metal patterns 22a and 22b are exposed around the third photoresist pattern 72c. do.

Next, as illustrated in FIG. 2D, the source metals 32 spaced apart from each other by removing the exposed first metal pattern 22a of FIG. 2C corresponding to the gate electrode 16 in the switching region S. Referring to FIG. And forming the drain electrode 34 and removing the first impurity amorphous silicon pattern (21a in FIG. 2C) using the source and drain electrodes 32 and 34 as masks, thereby removing the first pure amorphous silicon pattern (Fig. 2c of 20a) is exposed. Here, the first impurity amorphous silicon pattern (21a of FIG. 2C) is removed to form an ohmic contact layer 24b spaced apart from each other under the source and drain electrodes 32 and 34, and the first pure amorphous silicon pattern (FIG. 20a of 2c is exposed between the ohmic contact layer 24b to become the active layer 24a in which the channel region is defined. The ohmic contact layer 24b and the active layer 24a constitute a semiconductor layer 24. That is, in the switching region S, the semiconductor layer 24, the source electrode 32, and the drain electrode 34 including the gate electrode 16, the gate insulating film 18, the active layer 24a, and the ohmic contact layer 24b are provided. ) Is laminated, which constitutes a thin film transistor (T) that is a switching element.

Meanwhile, also in the capacitor region C, the second metal pattern (22b of FIG. 2C) and the second impurity amorphous silicon pattern (21b of FIG. 2C) exposed around the third photoresist pattern (72c of FIG. 2C) may be formed. It is removed to expose the bottom end of the second pure amorphous silicon pattern (20b in FIG. 2C), and corresponding to the gate wiring 14, the gate insulating film 18, the first semiconductor pattern 26a and the second The semiconductor pattern 26 and the metal pattern 36 which consist of the semiconductor pattern 26b are laminated | stacked.

Although not shown, data lines are formed at the boundary of the pixel region P to cross the gate wiring 14 to define the pixel region P and extend from the source electrode 32. As described above, since the data line extends from the source electrode 32, the data line has the same stacked structure as the portion where the source electrode 32 is formed. That is, a third semiconductor pattern extending from the active layer 24a and a fourth semiconductor pattern extending from the ohmic contact layer 24b are formed under the data line. Next, the third photoresist pattern 72c is removed.

2E shows a third mask process. As shown, the third photoresist pattern (72c in FIG. 2D) is removed. Before forming the color filter, the first and second electrodes may be formed of an inorganic insulating material including silicon nitride or silicon oxide on the source and drain electrodes 32 and 34, the data line (not shown), and the metal pattern 36. The protective layer 38 is formed. If the color filter is formed without forming the first protective layer 38, the exposed active layer 24a, which determines the characteristics of the thin film transistor T, is contaminated during the formation of the color filter. This results in deterioration of the characteristics of the transistor T. Therefore, formation of the first protective layer 38 is an essential process.

Next, the green color filter G corresponding to the pixel region P is formed by applying a green pigment onto the first protective layer 38 and patterning the same by a third mask process. Although not shown, red and blue color filters are formed in the adjacent pixel areas P by using the fourth and fifth mask processes.

2F shows a sixth mask process. As shown, the second protective layer 42 is formed on the green color filter G and the red and blue color filters (not shown) by using an inorganic insulating material, and the switching region ( First and second contact holes CH1 and CH2 are formed to expose the drain electrode 34 of S) and the metal pattern 36 of the capacitor region C, respectively. The second protective layer 42 serves to prevent a problem that the pigment material is eluted from the green color filter G and the red and blue color filters (not shown) to contaminate the liquid crystal.

Next, as shown in FIG. 2G illustrating the seventh mask process, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is formed on top of the second protective layer 42. The deposition and the seventh mask process are performed to form the pixel electrode 50 in the pixel region P. The pixel electrode 50 is connected to the thin film transistor T by contacting the drain electrode 34 through the first contact hole CH1 and the metal pattern 36 through the second contact hole CH2. Here, the gate wiring 16 and the metal pattern 36 overlap each other vertically to form a storage capacitor Cst.

By the above process, an array substrate for a liquid crystal display device having a COT structure is completed. As described above, the semiconductor layer, the source, and the drain electrode are formed as one mask in order to reduce the burden of the manufacturing process by the mask process, which is inevitably increased according to the CTO structure, which causes some problems. .

That is, in FIG. 2G showing the completed array substrate, the active layer 24a made of pure amorphous silicon, referred to as the so-called active tail, is exposed around the source electrode 32 and the drain electrode 34. This is caused by the exposure of the light supplied from the backlight unit (not shown) located below the substrate 12 and the external light to generate a leakage current (Ioff), resulting in the deterioration of the characteristics of the thin film transistor (T). In addition, even around the data line (not shown), pure semiconductor is made of pure silicon, and the semiconductor pattern extending to the active layer protrudes to be exposed to light, which is a wavy noise between the pixel electrodes 50. ) Will cause a problem, resulting in degradation of image quality. In addition, in order to cover the semiconductor pattern exposed around the data line (not shown), a larger black matrix must be present in the upper electrode, thereby causing a problem of reducing the aperture ratio.

An object of the present invention is to provide an array substrate for a COT structure liquid crystal display device having improved quality without increasing the number of mask processes in the manufacturing process of the array substrate for the COT structure liquid crystal display device.

That is, a COT structure liquid crystal display device capable of providing excellent quality images by preventing leakage currents, wave noise, and reduction of aperture ratio caused by amorphous silicon materials protruding around the source electrode, drain electrode, and data wiring. The present invention proposes a dyd array substrate and a method of manufacturing the same. In particular, while the source electrode and the semiconductor layer are formed as one mask, the active layer made of amorphous silicon is prevented from being exposed between the source electrode and the data line to prevent deterioration of characteristics of the thin film transistor.

In order to solve the above problems, the present invention includes a gate wiring and a data wiring crossing each other on the substrate to define a pixel region; A gate electrode connected to the gate wiring; An active layer having an island shape on the gate electrode; An ohmic contact layer spaced apart from each other on the active layer; Source and drain electrodes spaced apart from each other and having the same shape as the ohmic contact layer on the ohmic contact layer; A source electrode connection pattern connecting the source electrode and the data line; A pixel electrode extending from the drain electrode to the pixel region; An array substrate for a COT structure liquid crystal display device including a color filter formed in the pixel area is proposed.
Alternatively, the present invention provides a semiconductor device comprising: a gate wiring and a data wiring crossing each other on a substrate to define pixel regions; A gate electrode connected to the gate wiring; An active layer having an island shape on the gate electrode; An ohmic contact layer spaced apart from each other on the active layer; Source and drain electrodes spaced apart from each other and having the same shape as the ohmic contact layer on the ohmic contact layer; A source electrode connection pattern connecting the source electrode and the data line; A common wiring spaced apart in parallel with the gate wiring; A plurality of common electrodes connected to the common wiring and positioned in the pixel area; A plurality of pixel electrodes connected to the drain electrodes and alternately arranged with the plurality of common electrodes; An array substrate for a COT structure liquid crystal display device including a color filter formed in the pixel area is proposed.
In the array substrate for a COT structure liquid crystal display device, the semiconductor layer has the same or smaller area as the gate electrode and is completely overlapped with the gate electrode.
The source electrode may be formed of the same material on the same layer as the data line, and the source electrode connection pattern may be formed of the same material on the same layer as the pixel electrode.
A gate pad positioned at one end of the gate line and connected to the gate line; And a data pad positioned at one end of the data line and connected to the data line.
The pixel electrode overlaps the common wiring with the gate insulating layer interposed therebetween to form a storage capacitor.
On the other hand, the present invention comprises the steps of forming a gate wiring extending in one direction on the substrate, a gate electrode connected to the gate wiring, and common wiring spaced apart in parallel with the gate wiring; Forming a gate insulating film on an entire surface of the substrate on which the gate wiring, the gate electrode and the common wiring are formed; A pure amorphous silicon pattern, an impurity amorphous silicon pattern, and a metal pattern which are successively stacked in the same shape corresponding to the gate electrode on the gate insulating layer, and are separated from the metal pattern and cross the gate wiring to define a pixel region Forming a data line; Forming a color filter pattern on a substrate on which the metal pattern and the data line are formed; Forming a first passivation layer covering the color filter pattern and exposing the metal pattern; Source and drain electrodes spaced apart from the metal pattern, a source electrode connection pattern connecting the source electrode and the data line, a pixel electrode connected to the drain electrode and extending to the pixel region, and connected to the common wiring And forming a first common electrode which is alternately arranged in parallel with the pixel electrode.
The method of manufacturing an array substrate for a COT structure liquid crystal display device, wherein the forming of the gate wiring comprises: second and third common electrodes extending in parallel with the data wiring from both ends of the common wiring; And forming a common electrode connection wiring connecting the third common electrode, wherein the first common electrode is connected to the common electrode connection wiring.
The forming of the first passivation layer may include forming first and second contact holes exposing the common electrode connection wiring and the data wiring, respectively, wherein the first common electrode is the first contact. The electrode may be connected to the common electrode connection line through a hole, and the source electrode connection pattern may be connected to the data line through the second contact hole.
The first common electrode is positioned between the second and third common electrodes, and the pixel electrode is positioned between the first and second common electrodes and between the first and third common electrodes. do.
The forming of the first protective layer may include forming an insulating layer and a photoresist layer using an inorganic insulating material on the entire surface of the substrate on which the color filter is formed; By partially removing the photoresist layer, a first photoresist pattern having a first thickness and corresponding to both sides of the pixel region and the data line, and a second thickness smaller than the first thickness, correspond to the metal pattern. Forming a second photoresist pattern and exposing an insulating layer on the data line; Exposing the data line by removing the exposed insulating layer; Removing the second photoresist pattern by exposing the first and second photoresist patterns to expose an insulating layer over the metal pattern, and having a third thickness smaller than the first thickness from the first photoresist pattern. Forming a photoresist pattern; Etching the insulating layer over the metal pattern; And removing the third photoresist pattern.
The forming of the source and drain electrodes, the source electrode connection pattern, the pixel electrode, and the first common electrode may include forming a transparent conductive material layer on an entire surface of the substrate on which the first protective layer is formed. ; Removing the transparent conductive material layer corresponding to a center portion of the metal pattern and a region between the pixel electrode and the first common electrode; And removing the impurity amorphous silicon pattern at the center and the lower portion of the metal pattern to expose the pure amorphous silicon pattern.
In addition, by stacking and patterning a photoresist layer on the transparent conductive material layer, a first photoresist pattern having a first thickness corresponding to the pixel electrode and the first common electrode, both sides of the metal pattern, and the Forming a second photoresist pattern corresponding to a data line and having a second thickness smaller than the first thickness, thereby forming the transparent conductive material layer corresponding to a region between the metal pattern center portion and the pixel electrode and the first common electrode; And exposing the step.
In addition, after the exposure of the pure amorphous silicon pattern, the first and second photoresist patterns are ashed to remove the second photoresist pattern and have a thickness smaller than the first thickness from the first photoresist pattern. Forming a third photoresist pattern; Forming a second protective layer using an inorganic insulating material on an entire surface of the substrate on which the third photoresist pattern is formed; And simultaneously removing the third photoresist pattern and the second passivation layer thereon by the lift-off method.
The forming of the second protective layer may include depositing silicon nitride using a sputter.
The forming of the gate line may include forming a gate pad connected to the gate line at one end of the gate line, and forming the data line at one end of the data line. And forming a data pad connected to the data line, wherein forming the pixel electrode includes forming a gate pad terminal and a data pad terminal in contact with the gate and the data pad, respectively. It is done.
Each of the pure amorphous silicon pattern, the impurity amorphous silicon pattern, and the metal pattern may have a cross-sectional area equal to or smaller than that of the gate electrode and be completely overlapped with each other.
On the other hand, the present invention comprises the steps of forming a gate wiring extending in one direction on the substrate and a gate electrode connected to the gate wiring; Forming a gate insulating film on a substrate on which the gate wiring and the gate electrode are formed; A pure amorphous silicon pattern, an impurity amorphous silicon pattern, and a metal pattern which are successively stacked in the same shape corresponding to the gate electrode on the gate insulating layer, and are separated from the metal pattern and cross the gate wiring to define a pixel region Forming a data line; Forming a color filter pattern on a substrate on which the metal pattern and the data line are formed; Forming a first passivation layer covering the color filter pattern and exposing the metal pattern; Forming source and drain electrodes spaced apart from each other from the metal pattern, a source electrode connection pattern connecting the source electrode and the data line, and a pixel electrode connected to the drain electrode and extending into the pixel region; A method of manufacturing an array substrate for a COT structure liquid crystal display device is proposed.
In the method of manufacturing the array substrate for a COT structure liquid crystal display device, the forming of the first protective layer may include forming an insulating layer and a photoresist layer on the entire surface of the substrate on which the color filter is formed by using an inorganic insulating material. Making a step; By partially removing the photoresist layer, a first photoresist pattern having a first thickness and corresponding to both sides of the pixel region and the data line, and a second thickness smaller than the first thickness, correspond to the metal pattern. Forming a second photoresist pattern and exposing an insulating layer on the data line; Exposing the data line by removing the exposed insulating layer; Removing the second photoresist pattern by exposing the first and second photoresist patterns to expose an insulating layer over the metal pattern, and having a third thickness smaller than the first thickness from the first photoresist pattern. Forming a photoresist pattern; Etching the insulating layer over the metal pattern; And removing the third photoresist pattern.
The forming of the source and drain electrodes, the source electrode connection pattern, and the pixel electrode may include forming a transparent conductive material layer on an entire surface of the substrate on which the first protective layer is formed; Removing the transparent conductive material layer corresponding to the central portion of the metal pattern; And removing the impurity amorphous silicon pattern at the center and the lower portion of the metal pattern to expose the pure amorphous silicon pattern.
And stacking and patterning a photoresist layer on the transparent conductive material layer, corresponding to the pixel electrode, and having a first thickness, a first photoresist pattern having a first thickness, both sides of the metal pattern, and the data wiring; Forming a second photoresist pattern having a second thickness smaller than the first thickness, thereby exposing the transparent conductive material layer to correspond to the center portion of the metal pattern and the pixel electrode. Method of manufacturing an array substrate for an apparatus.
After the exposure of the pure amorphous silicon pattern, the first and second photoresist patterns are ashed to remove the second photoresist pattern and have a thickness smaller than the first thickness from the first photoresist pattern. Forming a third photoresist pattern; Forming a second protective layer using an inorganic insulating material on an entire surface of the substrate on which the third photoresist pattern is formed; And simultaneously removing the third photoresist pattern and the second passivation layer thereon by the lift-off method.
In the forming of the second protective layer, silicon nitride is deposited using a sputter.
The forming of the gate wiring may include forming a gate pad connected to the gate wiring at one end of the gate wiring, and forming the data wiring at one end of the data wiring, And forming a data pad connected to the data line, wherein forming the pixel electrode includes forming a gate pad terminal and a data pad terminal in contact with the gate and the data pad, respectively. It is done.
The pure amorphous silicon pattern, the impurity amorphous silicon pattern, and the metal pattern may each have a cross-sectional area equal to or smaller than that of the gate electrode and be completely overlapped with each other.

The present invention solves the problem of leakage current and wave noise without increasing the number of masks, and has a COT structure liquid crystal display device having an improved aperture ratio, compared to the conventional technique of simultaneously forming a semiconductor layer, a source, and a drain electrode. It is possible to provide an array substrate.

That is, by forming a semiconductor layer having an island shape on the gate electrode, the problem caused by the exposure of the semiconductor layer (particularly the active layer) is solved. In addition, while forming the source electrode and the semiconductor layer as one mask, the semiconductor layer does not exist in the region between the source electrode and the data wiring, thereby reducing the characteristics of the thin film transistor.

In the manufacturing process of the thin film transistor, by changing the active layer forming process after the color filter is formed, the protective layer that must be formed before the color filter is formed to protect the active layer can be omitted.

The present invention solves the problems of reducing leakage current, wave noise and aperture ratio by providing an island-shaped semiconductor layer, and also omits a protective layer for protecting the active layer of the thin film transistor in a color filter forming process. The manufacturing process of the array substrate for a COT structure liquid crystal display device of a structure is provided.

3 is a schematic plan view of an array substrate for a COT structure liquid crystal display according to an exemplary embodiment of the present invention.

As shown, the array substrate 100 of the COT structure liquid crystal display device is formed by crossing the gate wiring 112 and the data wiring 130 on the transparent substrate 110 to define the pixel region P. The thin film transistor T is formed at the intersection of the gate line 112 and the data line 130. The data line 130 has a shape bent in the middle portion of the pixel region P, thereby enabling a multi-domain structure. However, the shape of the data line 130 is not limited thereto and may be a straight line having no bent portion. The thin film transistor T includes a gate electrode 114 connected to the gate wire 112, a semiconductor layer 124 over the gate electrode 114, and a data wire 130 over the semiconductor layer 124. ) And a drain electrode 134 spaced apart from the source electrode 132. The source electrode 132 covers the data and extends into the data line 130 to contact the data line 130 through the fourth contact hole CH4 to contact the data line 130. It is connected to the wiring 130.

Here, in the array substrate 100 according to the present invention, unlike the conventional array substrate illustrated in FIG. 1, the semiconductor layer 124 including the active layer (not shown) has an island shape only on the gate electrode 114. Is done. That is, although the source electrode 132 and the semiconductor layer 124 are formed using one mask, the source electrode 132 is not directly connected to the data line 130, and the source electrode connection pattern 156 Indirectly connected by The active layer (not shown) has an area equal to or smaller than the gate electrode and is completely overlapped, and the source and drain electrodes 132 and 134 are formed on the active layer (not shown). That is, the semiconductor layer 124 including the active layer (not shown) and the source and drain electrodes 132 and 134 are both disposed in an island shape on the gate electrode 114. As a result, the semiconductor layer 124 does not exist in the region between the source electrode 132 and the data line 130, thereby preventing deterioration of characteristics of the thin film transistor T.

As described above, since the semiconductor layer 124 having an island shape is formed only in the gate electrode 114, there is no possibility of a problem of deterioration due to leakage current in the thin film transistor T as in the prior art, and furthermore, the data wiring ( 130) Since the semiconductor pattern does not protrude to the periphery, the problem of wave noise is solved, and it is not necessary to increase the width of the black matrix to cover the problem, thereby reducing the aperture ratio.

In addition, a drain electrode 134 and a pixel electrode 150 of the thin film transistor T are formed in the pixel region P, and the pixel electrode 150 is overlapped with the gate wiring 112 of the front end. The pattern 136 and the third contact hole CH3 are connected to each other. Here, an overlapping portion of the gate wiring 112 is used as the first electrode, an overlapping portion of the pixel electrode 150 is used as the second electrode, and an insulating layer (not shown) interposed between the first and second electrodes is disposed. The storage layer Cst is formed as the dielectric layer.

Further, color filters R, G, and B having any one of red, green, and blue colors are formed in each pixel region P. FIG. That is, due to the characteristics of the COT structure, the color filters R, G, and B are formed on the same substrate 110 on which the thin film transistor T is formed.

In addition, a gate pad 118 for applying a signal to the gate wiring 112 is formed at one end of the gate wiring 112, and a gate connected to the gate pad 118 through the first contact hole CH1. The pad terminal 152 is formed. In addition, a data pad 119 for applying a signal to the data wire 130 is formed at one end of the data wire 130, and data connected to the data pad 119 through the second contact hole CH2. The pad terminal 154 is formed.

The biggest feature in the embodiment of the present invention relates to a manufacturing method capable of forming an island-shaped semiconductor layer without increasing the mask process, which is shown in FIGS. 4A to 4H, 5A to 5H, and 6A to 6A. It demonstrates with reference to FIG. 6H.

4A to 4H are cross-sectional views of manufacturing portions cut along the line IV-IV of FIG. 3, and FIGS. 5A to 5H are cross-sectional views of the manufacturing processes of portions cut along VV of FIG. 3, and FIGS. 6A to 4H. 6h is a cross-sectional view of each part of the manufacturing process taken along the line VI-VI of FIG. 3. For convenience of description, a pixel region P including a switching region S in which a thin film transistor is formed, a capacitor region C in which a storage capacitor is formed, and a gate in which a gate pad and a data pad are formed on a substrate, respectively. The pad part GP and the data pad part DP are defined.

4A, 5A, and 6A show a first mask process. As illustrated, a first metal layer (not shown) is formed and patterned on the substrate 110 to extend in one direction along the boundary of the pixel region P, and to form a gate wiring 112 and the switching region S. FIG. A gate electrode 114 is formed on the gate line 112. The gate line 112 is positioned corresponding to the capacitor region C. The first metal layer (not shown) is made of at least one material of aluminum, aluminum alloy, tungsten, chromium and molybdenum. In addition, a gate pad 118 is formed in the gate pad part GP by being connected to one end of the gate line 112.

Next, an inorganic insulating material such as silicon nitride or silicon oxide is deposited on the entire surface of the substrate 110 on which the gate wiring 112, the gate electrode 114, and the gate pad 118 are formed to form the gate insulating film 120. Form.

4B, 5B and 6B show a second mask process. As shown in FIGS. 4B, 5B, and 6B, a pure amorphous silicon layer (not shown), an impurity amorphous silicon layer (not shown), and a second metal layer (not shown) are successively deposited on the gate insulating layer 120. By patterning, the first pure amorphous silicon pattern 121a, the first impurity amorphous silicon pattern 122a, and the metal pattern 123a overlapping with each other and having the same area and the same shape and completely overlap each other. And a second pure amorphous silicon pattern 121b, a second impurity amorphous silicon pattern 122b, and a data line 130, spaced apart from the metal pattern 123a. In addition, a third pure amorphous silicon pattern 121c, a third impurity amorphous silicon pattern 122c, and a storage pattern 136 are formed on the gate wiring 112 in the capacitor region C. The data pad A fourth pure amorphous silicon pattern 121d, a fourth impurity amorphous silicon pattern 122d, and a data pad 119 are formed in the portion DP on the gate insulating layer 120. The gate insulating layer 120 is exposed in the pixel region P and the gate pad part GP.

Next, FIGS. 4C, 5C and 6C show a third mask process. As illustrated, a green pigment is coated on the gate insulating layer 120 on which the metal pattern 123a, the data line 130, the storage pattern 136, and the data pad 119 are formed, and a third mask process is performed. By patterning by the above, the green color filter G corresponding to the pixel region P is formed. Next, although not illustrated, the red and blue color filters are formed in the neighboring pixel areas P through the fourth and fifth mask processes. Here, the order of forming the red, green, and blue color filters is not determined.

In the manufacture of the conventional COT structure array substrate, the formation of the protective layer was required before the formation of the color filter for the protection of the active layer, but in the present embodiment, the active layer is not opened before the formation of the color filter. It does not require formation of a protective layer for protection.

4D and 4E, 5D and 5E, 6D and 6E show a sixth mask process.

First, as shown in FIGS. 4D, 5D, and 6D, an inorganic insulating material such as silicon nitride or silicon oxide is deposited to sequentially stack the first protective layer 124 and the photoresist layer (not shown), and the upper portion thereof. The mask M which has the permeation | transmission part TA, the transflective part HTA, and the blocking part BA is arrange | positioned at the side. Here, the transflective portion HTA is smaller than the transmissive portion HT and has a transmittance larger than the cutoff portion BA. The transmissive part HTA transmits light so that the photoresist layer (not shown) is completely chemically changed, that is, completely exposed by light, and the blocking part BA functions to completely block light. In addition, the semi-transmissive part HTA forms a slit shape or a semi-transparent film on the mask M, thereby lowering the intensity of light or lowering the amount of light transmitted, thereby incompletely exposing the photoresist layer (not shown). Function By exposing and developing the photoresist layer (not shown) by using the mask M including the transflective portion HTA as described above, the first and second thicknesses t1 and t2 are respectively, and the difference ends BA are respectively. ) And the first and second photoresist patterns 182a and 182b at positions corresponding to the transflective portion HTA are formed. The first photoresist pattern 182a may be formed on both sides of the data line 130, the pixel region P, both sides of the storage pattern 136, both sides of the gate pad 118, and the data pad. Corresponding to both sides of 119, the second photoresist pattern 182b has a position corresponding to the metal pattern 123a of the switching region S. Referring to FIG. Accordingly, the first passivation layer 124 is exposed to correspond to the central portions of the data line 130, the storage pattern 136, the gate pad 118, and the data pad 119, and the exposed first passivation layer ( By removing the 124, the first to fourth contact holes CH1, CH2, and CH3 may be exposed to expose center portions of the gate pad 118, the data pad 119, the storage pattern 136, and the data line 130. CH4).

Next, as shown in FIGS. 4E, 5E and 6E, an ashing process is performed on the first and second photoresist patterns (182a and 182b of FIGS. 4D, 5D and 6D) to form the second photoresist pattern 182b. ), The first protective layer 124 of the switching region S is exposed, and the first photoresist pattern 182b of FIGS. 4D, 5D, and 6D is reduced in thickness to have a third thickness t3. The third photoresist pattern 182c is formed. Thereafter, the exposed first protective layer 124 is removed to expose the metal pattern 123a of the switching region S. FIG. The third photoresist pattern 182c is removed.

4F-4H, 5F-5H and 6F-6H show a seventh mask process.

First, as shown in FIGS. 4F, 5F, and 6F, after removing the third photoresist pattern (182c of FIGS. 4E, 5E, and 6E), the entire surface of the substrate 110 having the first protective layer 124 formed thereon. A transparent conductive material layer 126 made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) and a photoresist layer (not shown) are successively stacked, and then stacked thereon. A mask (not shown) having a transflective portion is positioned. A fourth photoresist pattern 184a having a fourth thickness corresponding to each of the pixel region P, the gate and the data pads 118 and 119 by a patterning process using the mask (not shown), A fifth photoresist pattern 184b corresponding to the data line 130 and having a fifth thickness smaller than the fourth thickness is formed. As a result, a center portion of the metal pattern 123a of the switching region S, a center portion of the storage pattern 136, both ends of the gate pad 118, and both ends of the data pad 119 correspond to each other. The transparent conductive material layer 126 is exposed.

Next, as shown in FIGS. 4G, 5G, and 6G, the transparent conductive exposed by performing a wet etching process using the fourth and fifth photoresist patterns (184a and 184b of FIGS. 4F, 5F and 6F) as a mask. The material layer 126 is removed. In the switching region S, a channel is formed by exposing the first pure amorphous silicon pattern 121a by removing the central impurity amorphous silicon pattern 122a and the lower portion of the metal pattern 123a. Define the area.

As a result, the active layer 124a having a channel region defined on the gate electrode 114, the ohmic contact layer 124b spaced apart from the active layer 124a by exposing the active layer 124a, Source and drain electrodes 132 and 134 are spaced apart from each other on the ohmic contact layer 124b. The active layer 124a and the ohmic contact layer 124b form a semiconductor layer 124, and the gate electrode 114, the semiconductor layer 124, the source electrode 132, and the drain electrode 134 are a thin film transistor ( Constitute T). In addition, the transparent conductive material layer 126 of FIGS. 4F, 5F, and 6F is also removed from one end of the strip pattern 136, thereby covering the color filter G of the pixel region P, and covering the drain electrode ( The pixel electrode 150 connected to the 134 is formed. The pixel electrode 150 extends into the capacitor region C and contacts the storage pattern 136 overlapping the gate line 112 of the capacitor region C through the third contact hole CH3. Here, the storage capacitor Cst having the overlapping portion of the gate wiring 1122 as the first electrode, the overlapping portion of the storage pattern 136 as the second electrode, and the gate insulating film 120 therebetween as the dielectric layer is consist of.

In addition, a source electrode connection pattern 162 connected to the source electrode 132 and contacting the data line 130 through the fourth contact hole CH4 is configured to form the source electrode 132 and the data. The wiring 130 is electrically connected. In addition, the transparent conductive material layers (FIGS. 4F, 5F, and 6F) on both sides of the gate and data pad parts GP and DP are removed, thereby allowing the gate to pass through each of the first and second contact holes CH1 and CH2. And a gate pad terminal 152 and a data pad terminal 154 in contact with the data pads 118 and 119.

In addition, an ashing process is performed on the fourth and fifth photoresist patterns 184a and 184b of FIGS. 4F, 5F, and 6F to form the pixel region P, the gate pad 118, and the data pad 119. ) To form a sixth photoresist pattern 184c having a sixth height only. The second protective layer 128 is formed on the entire surface of the substrate 110 by depositing an inorganic insulating material such as silicon nitride or silicon oxide using a sputter. Generally, the inorganic insulating material is deposited by chemical vapor deposition (CVD), but chemical vapor deposition is usually performed at a high temperature of 350 ° C. or higher, and such high temperature conditions have a melting point of about 200 ° C., the sixth photoresist pattern 184c. By damaging the shape, the desired pattern cannot be obtained. Therefore, in the present embodiment, since the formation of the second protective layer 128 proceeds to a relatively low temperature process of about 150 ° C. or less using sputtering, a desired pattern can be obtained without damaging the sixth photoresist pattern 184c. It becomes possible.

In this case, as shown in part A, due to the wet etching process of the transparent conductive material layer 126 of the pixel region P (126 of FIGS. 4F, 5F, and 6F), the pixel inside the sixth photoresist pattern 184c. The electrode 150 may be scraped off, and thus the second protective layer 128 may have a discontinuous portion at the boundary between the sixth photoresist pattern 184c and the pixel electrode 150. Similarly, in the gate and data pad portions GP and DP, the second passivation layer 128 is formed at discrete boundaries between the sixth photoresist pattern 184c and the gate and data pad terminals 152 and 154, respectively. Will have In addition, although the second protective layer 128 is seen as continuous at the boundary between the drain electrode 134 and the sixth photoresist pattern 184c, the side surface of the drain electrode 134, which is not shown in the drawing, is formed by wet etching. Since it is in the removed state, the second protective layer 128 also has a discontinuous portion even at the boundary between the drain electrode 134 and the sixth photoresist pattern 184c. In the above structure, the strip liquid for removing the sixth photoresist pattern 184c penetrates into the discontinuous portion of the second protective layer 128, and the sixth photoresist pattern 184c is the pixel electrode 150. The second protective layer 128 is also removed from the gate pad terminal 152 and the data pad terminal 154 at the same time, which is commonly referred to as a lift off process.

Next, as shown in FIGS. 4H, 5H, and 6H, the second protective layer 128 thereon is removed by a process of removing the sixth photoresist pattern (184c of FIGS. 4G, 5G, and 6G) by a lift-off process. In addition, the pixel electrode 150, the gate pad terminal 152, and the data pad terminal 154 may be exposed.

By the above process, the array substrate for the COT structure liquid crystal display device according to the exemplary embodiment of the present invention is completed. The lower substrate, which is an array substrate, is bonded to the upper substrate on which the black matrix and the common electrode are formed and the liquid crystal layer is interposed therebetween to form a liquid crystal display device. The black matrix serves to block a non-display area such as a thin film transistor of a lower substrate, and unlike the prior art of FIG. 1, since the semiconductor layer protruding from the data line does not exist, the width of the black matrix can be narrowed. Therefore, the opening ratio is increased. In addition, the common electrode serves to form an electric field driving the pixel electrode of the lower substrate and the liquid crystal layer. Here, in order to maintain the thickness (cell gap) of the liquid crystal layer uniformly before bonding of the upper and lower substrates, a step of forming columnar column spacers on any one of the upper and lower substrates is included.

The above liquid crystal display device has a narrow viewing angle because the liquid crystal layer is driven using an electric field formed vertically between the pixel electrode and the common electrode, and the pixel electrode and the common electrode are disposed on the same substrate to solve the problem. An in-plane switching type liquid crystal display device using a horizontal electric field therebetween has been proposed.

7 is a schematic plan view of an array substrate for a COT structure transverse field type liquid crystal display according to an exemplary embodiment of the present invention.

As shown, the array substrate 200 of the COT structure transverse field type liquid crystal display device is formed on the transparent substrate 210 by crossing the gate wiring 212 and the data wiring 230 to define the pixel region P. The thin film transistor T is formed at the intersection of the gate line 212 and the data line 230. The data line 230 has a shape bent in the middle portion of the pixel region P, thereby enabling a multi-domain structure. However, the shape of the data line 230 is not limited thereto and may be a straight line having no bent portion. The thin film transistor T is spaced apart from each other on the gate electrode 214 connected to the gate wiring 212, the semiconductor layer 224 on the gate electrode 214, and on the semiconductor layer 224. A source electrode 232 and a drain electrode 234 are included. Here, the source electrode 232 is shown as having a U-shape, the drain electrode 234 is shown as having a bar shape that is inserted into the opening of the U-shape. However, the shape of the source and drain electrodes is not limited thereto, and any shape may be used as long as the source and drain electrodes have a structure spaced apart from each other while overlapping the semiconductor layer.

Similar to the array substrate 100 of the present invention described with reference to FIG. 3, the semiconductor layer 224 including an active layer (not shown) has an island shape only on the gate electrode 214, and also has a source and a drain electrode. 232 and 234 also have an island shape on the semiconductor layer 224. That is, the semiconductor layer 224 has the same or smaller cross-sectional area as the gate electrode 214 and is formed to overlap completely, and the source and drain electrodes 232 and 234 are also formed only on the gate electrode 214. Since the source electrode 232 is located in an island shape on the gate electrode 214, the source electrode 232 is spaced apart from the data line 230. Accordingly, the source electrode connection pattern 264 is formed by contacting the data line 230 through the fourth contact hole CH4 extending from the source electrode 232 and corresponding to the data line 230. The source electrode 232 is electrically connected to the data line 230. As a result, the semiconductor layer 224 does not exist in the region between the source electrode 232 and the data line 230, thereby preventing deterioration of characteristics of the thin film transistor.

As described above, since the semiconductor layer 224 having an island shape is formed only in the gate electrode 214, there is no problem of deterioration of characteristics due to leakage current in the thin film transistor as in the prior art, and also around the data line 230. As the semiconductor pattern does not protrude, the problem of the wavy noise is solved, and the width of the black matrix is not required to cover it, thereby reducing the aperture ratio.

In addition, the common wiring 216 is formed to be spaced apart in parallel to the gate wiring 212, and the first and second common electrodes (parallel to the data wiring 230 from both ends of the common wiring 216). 217a and 217b are comprised. That is, the first and second common electrodes 217a and 217b have a shape in which a central portion thereof is bent. In addition, the common electrode connection wiring 217c is formed in parallel with the common wiring 216 while connecting the ends of the first and second common electrodes 217a and 217b. That is, the common wiring 216, the first and second common electrodes 217a and 217b, and the common electrode connection wiring 217c have a structure surrounding the pixel area P. In addition, a third common electrode 250 is formed at a central portion of the common electrode connection wiring 217c through a third contact hole CH3 and parallel to the first and second common electrodes 217a and 217b. It is.

In the pixel region P, a pixel electrode 260 connected to the thin film transistor T is disposed between the first and third common electrodes 217a and 250 and the second and third common electrodes 217b, 250). That is, the common electrodes 217a, 217b, 250 and the pixel electrodes 260 are spaced apart in parallel to each other, and drive a liquid crystal layer (not shown) by forming a parallel electric field therebetween by applying a voltage. Let's do it.

The pixel electrode 260 is connected to the drain electrode 234 of the thin film transistor T. To this end, the pixel electrode 260 extends from the drain electrode 234 and overlaps the common wiring 216. ) Is configured. That is, the pixel electrode 260 is connected to the drain electrode 234 of the thin film transistor T through the pixel electrode connection wiring 262. As described above, the pixel electrode connection wiring 262 overlaps the common wiring 216, and the overlapping portion of the common wiring 216 is the first electrode, and the overlapping portion of the pixel electrode connection wiring 262. Is the second electrode, and the storage capacitor Cst is formed using the insulating layer (not shown) between the first and second electrodes as the dielectric layer.

In addition, a green color filter G is formed in the pixel region P, and red or blue color filters R and B are formed in each of the adjacent pixel regions P. FIG. That is, due to the characteristics of the COT structure, the color filters R, G, and B are formed on the same substrate 210 as the thin film transistor T.

In addition, a gate pad 218 for applying a signal to the gate wire 212 is formed at one end of the gate wire 212, and a gate connected to the gate pad 218 through the first contact hole CH1. The pad terminal 252 is formed. In addition, at one end of the data line 230, a data pad 219 for applying a signal to the data line 230 is formed, and data connected to the data pad 219 through the second contact hole CH2. The pad terminal 254 is formed.

Next, a manufacturing process for the array substrate of the COT structure transverse electric field type liquid crystal display device having the above configuration will be described.

8A to 8H are cross-sectional views of manufacturing portions cut along the line VIII-VIII of FIG. 7, and FIGS. 9A to 9H are cross-sectional views of the manufacturing processes of portions cut along the line IX-IX of FIG. 7. For convenience of description, the pixel region P including the switching region S in which the thin film transistor is formed and the capacitor region C in which the storage capacitor is formed are defined on the substrate. In addition, since the manufacturing method for the gate and data pad unit in which the gate pad 218 of FIG. 7 and the data pad 219 of FIG. 7 are formed is the same as that described with reference to FIGS. 5A to 5H and 6A to 6H, Omit it. In addition, since it is similar to the manufacturing process described above except for the process of forming the common wiring and the common electrode will be described briefly.

8A and 9A show a first mask process. As illustrated, a first metal layer (not shown) is formed and patterned on the substrate 210 to extend in one direction along the boundary of the pixel region P, and to form a gate wiring (not shown) and the switching region S. A gate electrode 214 connected to the gate line (not shown) is formed. In addition, a common wiring 216 spaced apart in parallel with the gate wiring (not shown) and first and second common electrodes (not shown) extending from the common wiring 216 are formed. Two common electrodes (not shown) are connected to both ends and a common electrode connection wiring 217c parallel to the common wiring 216 is formed. In this case, the common wiring 216 is also formed in the capacitor region C. The first metal layer (not shown) is made of at least one material of aluminum, aluminum alloy, tungsten, chromium and molybdenum.

Next, an inorganic insulating material such as silicon nitride or silicon oxide on the entire surface of the substrate 210 on which the gate wiring (not shown), the gate electrode 214, the common wiring 216, and the common electrode connection wiring 217c are formed. Deposited to form a gate insulating film 220.

8B-8D and 9B-9D show a second mask process.

8B and 9B, a pure amorphous silicon layer (not shown), an impurity amorphous silicon layer (not shown), and a second metal layer (not shown) are successively deposited and patterned on the gate insulating layer 120. The first pure amorphous silicon pattern 221a, the first impurity amorphous silicon pattern 222a, and the metal pattern 223a are formed to correspond to the gate electrode 214 and have the same area and the same shape and completely overlap each other. The second pure amorphous silicon pattern 221b, the second impurity amorphous silicon pattern 222b, and the data line 230 are formed to be spaced apart from the metal pattern 223a. The gate insulating layer 220 is exposed in the pixel region P, the capacitor region C, and the common electrode connection wiring 217c.

8C and 9C show a third mask process. As illustrated, the green pigment is coated on the gate insulating layer 220 on which the metal pattern 223a and the data line 230 are formed and patterned by a third mask process to correspond to the pixel region P. FIG. The green color filter G is formed. Next, although not shown, red and blue color filters (not shown) are formed in the adjacent pixel areas P through fourth and fifth mask processes. Here, the order of forming the red, green, and blue color filters is not determined. In the manufacture of the conventional COT structure array substrate, the formation of the protective layer was required before the formation of the color filter for the protection of the active layer, but in the present embodiment, the active layer is not opened before the formation of the color filter. It does not require formation of a protective layer for protection.

8D and 8E, 9D and 9E show a sixth mask process.

First, as shown in FIGS. 8D and 9D, an inorganic insulating material such as silicon nitride or silicon oxide is deposited to successively laminate the first protective layer 224 and the photoresist layer (not shown), and a transmissive portion thereon. (TA), a mask (M) having a transflective portion (HTA) and a blocking portion (BA) is positioned. By exposing and developing a photoresist layer (not shown) using the mask M, the photoresist layer has first and second thicknesses t1 and t2, respectively, and corresponds to the blocking part BA and the transflective part HTA, respectively. The first and second photoresist patterns 282a and 282b are formed at the positions. The first photoresist pattern 282a corresponds to both sides of the data line 230, the pixel region P, and both sides of the common electrode connection wiring 217c, and the second photoresist pattern 282b. ) Has a position corresponding to the metal pattern 223a of the switching region S. Therefore, the first passivation layer 224 is exposed to correspond to the central portion of each of the data line 230 and the common electrode connection line 217c. The third contact hole exposing the center portion of the common electrode connection wiring 217c by removing the exposed first protective layer 224 and the gate insulating layer 220 below the common electrode connection wiring 217c. The fourth contact hole CH4 exposing the center portion of the data line 230 is formed by forming CH3 and simultaneously removing the exposed first protective layer 224 on the data line 230.

Next, as shown in FIGS. 8E and 9E, an ashing process is performed on the first and second photoresist patterns 282a and 282b of FIGS. 8D and 9D to form the first protective layer of the switching region S. 224). At this time, the thickness of the first photoresist pattern 282b of FIGS. 8D and 9D is reduced to form a third photoresist pattern 282c having a third thickness t3. Thereafter, the exposed first protective layer 224 is removed to expose the metal pattern 223a of the switching region S.

8F-8H and 9F-9H show a seventh mask process.

First, as shown in FIGS. 8F and 9F, after removing the third photoresist pattern 282c of FIGS. 8E and 9E, indium-tin is formed on the entire surface of the substrate 210 on which the first protective layer 224 is formed. After successively laminating a transparent conductive material layer 226 made of a transparent conductive material such as -oxide (ITO) or indium-zinc-oxide (IZO) and a photoresist layer (not shown), and having a transflective portion thereon Place a mask (not shown). A region in which the pixel electrode connection wiring (262 of FIG. 7), the pixel electrode (260 of FIG. 7) and the third common electrode (250 of FIG. 7) are to be formed by a patterning process using the mask (not shown); A fourth photoresist pattern 284a corresponding to one side of the common electrode connection wiring 217c and having a fourth thickness t4, and corresponding to both sides of the data line 230 and the switching region S. A fifth photoresist pattern 284b having a fifth thickness t5 smaller than four thicknesses t4 is formed. As a result, a center portion of the metal pattern 223a of the switching region S, the other side of the common electrode connection wiring 217c, and an area corresponding to the area between the pixel electrode 260 of FIG. 7 and the common electrode 250 of FIG. The transparent conductive material layer 226 is exposed.

Next, as shown in FIGS. 8G and 9G, the transparent conductive material layer exposed by performing a wet etching process using the first and second photoresist patterns 284a and 284b of FIGS. 8F and 9F as masks (FIG. 8f, 9f, 226) are removed. In the switching region S, the first pure non-seed portion is removed by removing the central portion of the metal pattern 223a of FIGS. 8F and 9F and the first impurity amorphous silicon pattern 222a of FIGS. 8F and 9F. The channel region is defined by exposing the vaginal silicon pattern (221a in FIGS. 8F and 9F).

As a result, an active layer 224a having a channel region defined on the gate electrode 214, an ohmic contact layer 224b spaced apart from the active layer 224a by exposing the active layer 224a, and Source and drain electrodes 232 and 234 are spaced apart from each other on the ohmic contact layer 224b. The active layer 224a and the ohmic contact layer 224b form a semiconductor layer 224, and the gate electrode 214, the semiconductor layer 224, the source electrode 232, and the drain electrode 234 are a thin film transistor ( Constitute T). In addition, the pixel electrode connection wiring 262 connected to the drain electrode 234 and overlapping the common wiring 216, the pixel electrode 260 extending from the pixel electrode connection wiring 262, and the pixel. A third common electrode 250 spaced apart from the electrode is formed. The overlapping portion of the common wiring 216 is a first electrode, the overlapping portion of the pixel electrode connection wiring 262 is a second electrode, and the gate insulating layer 220 therebetween is a dielectric layer. Cst is configured. In addition, the third common electrode 250 is connected to the common electrode connection wiring 217c through the third contact hole CH3. In addition, a source electrode connection pattern 262 connected to the source electrode 232 and contacting the data line 230 through the fourth contact hole CH4 is configured to form the source electrode 232 and the data. The wiring 230 is electrically connected.

The ashing process is performed on the fourth and fifth photoresist patterns 284a and 284b to correspond to the pixel electrode connection wiring 262, the pixel electrode 260, and the third common electrode 250. A sixth photoresist pattern 284c having six heights is formed. The second protective layer 228 is formed on the entire surface of the substrate 210 by laminating an inorganic insulating material such as silicon nitride or silicon oxide using a sputter. In general, the use of a sputter without using chemical vapor deposition (CVD) used to deposit an inorganic insulating material is to prevent damage to the sixth photoresist pattern 284c as described above.

In this case, as shown in part B, the third common inside of the sixth photoresist pattern 284c is formed due to the wet etching process of the transparent conductive material layer (226 of FIGS. 8F and 9F) of the pixel region P. The electrode 250 may be scraped off, and thus, the second protective layer 228 may have a discontinuous portion at the boundary between the sixth photoresist pattern 284c and the third common electrode 250. Similarly, in the pixel electrode connection wiring 262 and the pixel electrode 260, the second protective layer 228 also at the boundary between the sixth photoresist pattern 284c, the pixel electrode connection wiring 262, and the pixel electrode 260. ) Has a discontinuous part. In addition, as described with reference to FIG. 4G, the second protective layer 228 has discontinuous portions even at the boundary between the drain electrode 234 and the sixth photoresist pattern 284c. In the above structure, the strip liquid for removing the sixth photoresist pattern 284c penetrates into the discontinuous portion of the second protective layer 228, and the sixth photoresist pattern 284c is connected to the pixel electrode connection wiring 262. The second protective layer 228 is also removed from the pixel electrode 260 and the third common electrode 250 while being removed from the pixel electrode 260 and the third common electrode 250. This is commonly referred to as a lift off process.

Next, as shown in FIGS. 8H and 9H, the second protective layer 228 is also removed thereon by a process of removing the sixth photoresist pattern (284c in FIGS. 8G and 9G) by a lift-off process. The pixel electrode connection wiring 262, the pixel electrode 260, and the third common electrode 250 are exposed.

By the above process, the array substrate of the COT structure transverse electric field type liquid crystal display device according to the present invention is completed. As described above, according to the present invention, the semiconductor layer (particularly the active layer) and the source and drain electrodes thereon are formed in an island shape on the gate electrode in one mask process, thereby preventing leakage current of the thin film transistor without increasing the mask process. Will be solved. In addition, by separating the source electrode and the data wiring, it is possible to prevent the leakage current by the active layer existing between the source electrode and the data wiring conventionally. Since the semiconductor layer exists under the data line but does not protrude from the data line, the conventional problems of wave noise and aperture ratio drop can be solved.

The lower substrate, which is an array substrate, is bonded to the upper substrate on which the black matrix is formed and the liquid crystal layer therebetween to form a liquid crystal display device. The black matrix serves to block a non-display area such as a thin film transistor of a lower substrate, and unlike the prior art of FIG. 1, since the semiconductor layer protruding from the data line does not exist, the width of the black matrix can be narrowed. Therefore, the opening ratio is increased. Here, in order to maintain the thickness (cell gap) of the liquid crystal layer uniformly before bonding of the upper and lower substrates, a step of forming columnar column spacers on any one of the upper and lower substrates is included.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art various modifications and changes of the present invention without departing from the spirit and scope of the present invention described in the claims below I can understand that you can.

1 is a plan view illustrating an array substrate of a COT structure hierarchical liquid crystal display device according to the related art.

2A to 2G are cross-sectional views of manufacturing processes of portions cut along the line II-II of FIG. 1.

3 is a schematic plan view of an array substrate for a COT structure liquid crystal display according to an exemplary embodiment of the present invention.

4A to 4H are cross-sectional views of manufacturing processes taken along the line IV-IV of FIG. 3.

5A to 5H are cross-sectional views of manufacturing processes taken along the line V-V of FIG. 3.

6A to 6H are cross-sectional views of manufacturing processes taken along the line VI-VI of FIG. 3.

7 is a schematic plan view of an array substrate for a COT structure transverse field type liquid crystal display according to an exemplary embodiment of the present invention.

8A to 8H are cross-sectional views of manufacturing processes taken along the line VIII-VIII of FIG. 7.

9A to 9H are cross-sectional views of manufacturing processes of portions cut along IX-IX of FIG. 7, respectively.

Claims (25)

Gate wiring and data wiring crossing the substrate to define pixel regions therebetween; A gate electrode connected to the gate wiring; An active layer having an island shape on the gate electrode; An ohmic contact layer spaced apart from each other on the active layer; Source and drain electrodes spaced apart from each other and overlapping the ohmic contact layer with the same shape as the ohmic contact layer; A source electrode connection pattern connecting the source electrode and the data line; A pixel electrode extending from the drain electrode to the pixel region; A color filter formed in the pixel region Array substrate for a COT structure liquid crystal display device comprising a. Gate wiring and data wiring crossing the substrate to define pixel regions therebetween; A gate electrode connected to the gate wiring; An active layer having an island shape on the gate electrode; An ohmic contact layer spaced apart from each other on the active layer; Source and drain electrodes spaced apart from each other and overlapping the ohmic contact layer with the same shape as the ohmic contact layer; A source electrode connection pattern connecting the source electrode and the data line; A common wiring spaced apart in parallel with the gate wiring; A plurality of common electrodes connected to the common wiring and positioned in the pixel area; A plurality of pixel electrodes connected to the drain electrodes and alternately arranged with the plurality of common electrodes; A color filter formed in the pixel region Array substrate for a COT structure liquid crystal display device comprising a. 3. The method according to claim 1 or 2, And the semiconductor layer including the active layer and the ohmic contact layer has an area equal to or smaller than the gate electrode and completely overlaps the gate electrode. 3. The method according to claim 1 or 2, And the source electrode is made of the same material on the same layer as the data line, and the source electrode connection pattern is made of the same material on the same layer as the pixel electrode. 3. The method according to claim 1 or 2, A gate pad positioned at one end of the gate line and connected to the gate line; And a data pad positioned at one end of the data line and connected to the data line. The method of claim 1, And the pixel electrode overlaps the gate wiring with the gate insulating film interposed therebetween to form a storage capacitor. Forming a gate wiring extending in one direction on the substrate, a gate electrode connected to the gate wiring, and a common wiring spaced apart in parallel with the gate wiring; Forming a gate insulating film on an entire surface of the substrate on which the gate wiring, the gate electrode and the common wiring are formed; A pure amorphous silicon pattern, an impurity amorphous silicon pattern, and a metal pattern which are successively stacked in the same shape corresponding to the gate electrode on the gate insulating layer; Forming a data line; Forming a color filter pattern on a substrate on which the metal pattern and the data line are formed; Forming a first passivation layer covering the color filter pattern and exposing the metal pattern; An ohmic contact layer spaced apart from each other on the active layer from the pure amorphous silicon pattern, and an upper portion of the active layer from the impurity amorphous silicon pattern, source and drain electrodes spaced apart from the metal pattern and overlapping the ohmic contact layer; A source electrode connection pattern connecting the source electrode and the data line, a pixel electrode connected to the drain electrode and extending to the pixel region, and a first common connected to the common line and alternately arranged in parallel with the pixel electrode. Forming an electrode Method of manufacturing an array substrate for a COT structure liquid crystal display device comprising a. The method of claim 7, wherein The step of forming the gate wiring, Forming a second and third common electrode extending in parallel with the data line from both ends of the common line, and a common electrode connection line connecting the second and third common electrodes; And the first common electrode is connected to the common electrode connection wiring. 9. The method of claim 8, The forming of the first passivation layer may include forming first and second contact holes exposing the common electrode connection wiring and the data wiring, respectively, wherein the first common electrode is configured to form the first contact hole. And the source electrode connection pattern is connected to the data line through the second contact hole. 9. The method of claim 8, The first common electrode is positioned between the second and third common electrodes, and the pixel electrode is positioned between the first and second common electrodes and between the first and third common electrodes. A method of manufacturing an array substrate for a structure liquid crystal display device. The method of claim 7, wherein Forming the first protective layer, Forming an insulating layer and a photoresist layer by using an inorganic insulating material on the entire surface of the substrate on which the color filter is formed; By partially removing the photoresist layer, a first photoresist pattern having a first thickness and corresponding to both sides of the pixel region and the data line, and a second thickness smaller than the first thickness, correspond to the metal pattern. Forming a second photoresist pattern and exposing an insulating layer on the data line; Exposing the data line by removing the exposed insulating layer; Removing the second photoresist pattern by exposing the first and second photoresist patterns to expose an insulating layer over the metal pattern, and having a third thickness smaller than the first thickness from the first photoresist pattern. Forming a photoresist pattern; Etching the insulating layer over the metal pattern; A method of manufacturing an array substrate for a liquid crystal display device including a COT structure comprising the step of removing the third photoresist pattern. The method of claim 7, wherein Forming the active layer, the ohmic contact layer, the source and drain electrodes, the source electrode connection pattern, the pixel electrode, and the first common electrode, Forming a transparent conductive material layer on an entire surface of the substrate on which the first protective layer is formed; Removing the transparent conductive material layer corresponding to a center portion of the metal pattern and a region between the pixel electrode and the first common electrode; And exposing the pure amorphous silicon pattern by removing the impurity amorphous silicon pattern at a central portion and a lower portion of the metal pattern. 13. The method of claim 12, Stacking and patterning a photoresist layer on the transparent conductive material layer, the first photoresist pattern having a first thickness corresponding to the pixel electrode and the first common electrode, both sides of the metal pattern, and the data line And a second photoresist pattern having a second thickness smaller than the first thickness to expose the transparent conductive material layer corresponding to a region between the center of the metal pattern, the pixel electrode, and the first common electrode. A method of manufacturing an array substrate for a liquid crystal display device having a COT structure comprising the step. 14. The method of claim 13, After exposure of the pure amorphous silicon pattern, Ashing the first and second photoresist patterns, removing the second photoresist pattern, and forming a third photoresist pattern having a thickness smaller than the first thickness from the first photoresist pattern; Forming a second protective layer using an inorganic insulating material on an entire surface of the substrate on which the third photoresist pattern is formed; And simultaneously removing the third photoresist pattern and the second protective layer thereon by a lift-off method. 15. The method of claim 14, Wherein forming the second passivation layer comprises: A method of manufacturing an array substrate for a COT structure liquid crystal display device comprising depositing silicon nitride using a sputter. The method of claim 7, wherein The forming of the gate wiring may include forming a gate pad connected to the gate wiring at one end of the gate wiring, The forming of the data line may include forming a data pad connected to the data line at one end of the data line, The forming of the pixel electrode may include forming a gate pad terminal and a data pad terminal in contact with the gate and the data pad, respectively. The method of claim 7, wherein And the pure amorphous silicon pattern, the impurity amorphous silicon pattern, and the metal pattern each have a cross-sectional area equal to or smaller than that of the gate electrode and are completely overlapped with each other. Forming a gate wiring extending in one direction on the substrate and a gate electrode connected to the gate wiring; Forming a gate insulating film on a substrate on which the gate wiring and the gate electrode are formed; A pure amorphous silicon pattern, an impurity amorphous silicon pattern, and a metal pattern which are successively stacked in the same shape corresponding to the gate electrode on the gate insulating layer; Forming a data line; Forming a color filter pattern on a substrate on which the metal pattern and the data line are formed; Forming a first passivation layer covering the color filter pattern and exposing the metal pattern; An ohmic contact layer spaced apart from each other on the active layer from the pure amorphous silicon pattern, and an upper portion of the active layer from the impurity amorphous silicon pattern, source and drain electrodes spaced apart from the metal pattern and overlapping the ohmic contact layer; Forming a source electrode connection pattern connecting the source electrode and the data line and a pixel electrode connected to the drain electrode and extending to the pixel region; Method of manufacturing an array substrate for a COT structure liquid crystal display device comprising a. 19. The method of claim 18, Forming the first protective layer, Forming an insulating layer and a photoresist layer by using an inorganic insulating material on the entire surface of the substrate on which the color filter is formed; By partially removing the photoresist layer, a first photoresist pattern having a first thickness and corresponding to both sides of the pixel region and the data line, and a second thickness smaller than the first thickness, correspond to the metal pattern. Forming a second photoresist pattern and exposing an insulating layer on the data line; Exposing the data line by removing the exposed insulating layer; Removing the second photoresist pattern by exposing the first and second photoresist patterns to expose an insulating layer over the metal pattern, and having a third thickness smaller than the first thickness from the first photoresist pattern. Forming a photoresist pattern; Etching the insulating layer over the metal pattern; A method of manufacturing an array substrate for a liquid crystal display device including a COT structure comprising the step of removing the third photoresist pattern. 19. The method of claim 18, The forming of the active layer, the ohmic contact layer, the source and drain electrodes, the source electrode connection pattern, and the pixel electrode may include: Forming a transparent conductive material layer on an entire surface of the substrate on which the first protective layer is formed; Removing the transparent conductive material layer corresponding to the central portion of the metal pattern; And exposing the pure amorphous silicon pattern by removing the impurity amorphous silicon pattern at a central portion and a lower portion of the metal pattern. 21. The method of claim 20, Stacking and patterning a photoresist layer on the transparent conductive material layer, the first photoresist pattern having a first thickness and corresponding to the pixel electrode, both sides of the metal pattern, and the data wiring, respectively; And forming a second photoresist pattern having a second thickness smaller than the thickness to expose the transparent conductive material layer corresponding to the center portion of the metal pattern and the pixel electrode. Method of manufacturing an array substrate. 22. The method of claim 21, After exposure of the pure amorphous silicon pattern, Ashing the first and second photoresist patterns, removing the second photoresist pattern, and forming a third photoresist pattern having a thickness smaller than the first thickness from the first photoresist pattern; Forming a second protective layer using an inorganic insulating material on an entire surface of the substrate on which the third photoresist pattern is formed; And simultaneously removing the third photoresist pattern and the second protective layer thereon by a lift-off method. 23. The method of claim 22, Wherein forming the second passivation layer comprises: A method of manufacturing an array substrate for a COT structure liquid crystal display device comprising depositing silicon nitride using a sputter. 19. The method of claim 18, The forming of the gate wiring may include forming a gate pad connected to the gate wiring at one end of the gate wiring, The forming of the data line may include forming a data pad connected to the data line at one end of the data line, The forming of the pixel electrode may include forming a gate pad terminal and a data pad terminal in contact with the gate and the data pad, respectively. 19. The method of claim 18, And the pure amorphous silicon pattern, the impurity amorphous silicon pattern, and the metal pattern each have a cross-sectional area equal to or smaller than that of the gate electrode and are completely overlapped with each other.

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