KR101380206B1 - High efficiency amplifier comprising drain bias modulation circuit - Google Patents

Abstract

According to an embodiment of the invention, the drain bias modulation circuit for outputting a voltage corresponding to the power supply voltage or a multiple of the power supply voltage according to the magnitude of the input signal; And a power amplifier having an output voltage of the drain bias modulation circuit applied to a drain and having an amplifying transistor for amplifying and outputting the input signal input to a gate, wherein the drain bias modulation circuit applies the power supply voltage to a drain. At least one transistor having a source coupled to the drain of the amplifying transistor; And an envelope detector which detects the magnitude of the input signal and inputs it to the gate of the one or more transistors.

Description

HIGH EFFICIENCY AMPLIFIER COMPRISING DRAIN BIAS MODULATION CIRCUIT

The present invention relates to a high frequency power amplifier to which a drain bias modulation circuit is applied, and more particularly, to a high frequency power amplifier to which a drain bias modulation circuit having a simplified circuit structure without limiting power capacity is applied.

High frequency power amplifiers for base stations generally require good linearity and efficiency characteristics. The efficiency is closely related to the heat generated by the power device, and if the efficiency is not good, a lot of heat is generated. This consequently degrades the device's properties and durability. Therefore, in order to suppress such a problem, an expensive cooling system must be provided. Conversely, a highly efficient linear power amplifier reduces the cost and maintenance costs of the system and ensures the performance and durability of the power device.

Many efforts have been made to improve the efficiency of high frequency power amplifiers. The typical method is to reduce the drain bias voltage of the amplifier when the input signal is small, and increase the average efficiency by increasing the drain bias voltage of the amplifier when the input signal is large.

Specifically, a method of sampling the RF input signal, extracting an amplitude of the envelope, that is, amplifying the amplitude, and then adjusting the drain bias voltage of the power amplifier.

One example of a conventional drain bias modulation scheme is a method in which an additional voltage is added to an applied voltage supplied from the outside to set a drain bias voltage, and the added voltage is generated through a regulator or a direct current converter. Typically, the power capacity of regulators or direct-current converters is limited, requiring the connection of several devices for large power generation. Thus, there has been a problem that the volume of the circuit design becomes large. In addition, since the level of the drain bias of the power amplifier is determined only by the power supply voltage and the voltage added thereto, it has been adjusted to only two levels.

Jin Ho Jung, "A New Drain Bias Technique for Improving the Linearity of Envelope Tracking Power Amplifiers," Journal of the Korean Institute of Electronics Engineers, Vol. 46, No. 381, March 2009: pp.40-47.

SUMMARY OF THE INVENTION The present invention has been made to solve all the problems of the prior art described above.

It is an object of the present invention to provide a drain bias modulation circuit that is not limited in power capacity.

It is another object of the present invention to adjust the output voltage of the drain bias modulation circuit of the high frequency power amplifier, that is, the drain bias applied voltage of the power amplifier in multiple stages.

Still another object of the present invention is to improve the efficiency and linearity of the power amplifier by adjusting the drain bias voltage according to the RF input signal more precisely in the high frequency power amplifier.

According to an embodiment of the invention, the drain bias modulation circuit for outputting a voltage corresponding to the power supply voltage or a multiple of the power supply voltage according to the magnitude of the input signal; And a power amplifier having an output transistor of the drain bias modulation circuit applied to a drain and having an amplifying transistor for amplifying and outputting the input signal input to a gate, wherein the drain bias modulation circuit includes a power supply voltage at a drain. One or more transistors applied and whose source is connected to the drain of the amplifying transistor; And an envelope detector configured to detect the magnitude of the input signal and input it to the gate of the one or more transistors.

delete

The one or more transistors have different threshold voltages, and may be selectively turned on or off according to a signal from the envelope detector.

A capacitor may be connected between the source of the one or more transistors and the drain of the amplifying transistor, respectively.

A voltage supplied from a source of the at least one transistor and the power supply voltage may be applied to the drain of the amplifying transistor.

The power amplifier may include an inductor connected to the drain of the amplifying transistor, the power supply voltage may be applied to one end of the inductor, and the source of the one or more transistors may be connected to the other end of the inductor.

The gate of the amplifying transistor may be connected to the input of the envelope detector.

At least one of an inductor or a capacitor may be connected between the gate of the amplifying transistor and the input terminal of the envelope detector.

According to the present invention, the power capacity of the drain bias modulation circuit of the high frequency power amplifier is not limited, and the drain bias voltage of the transistor included in the power amplifier can be adjusted to two or more levels.

Further, according to the present invention, even if the magnitude of the RF input signal of the power amplifier changes in real time, it becomes possible to improve the power efficiency without relatively decreasing the linearity.

1 is a block diagram illustrating an operation of a drain bias modulation circuit of a general high frequency power amplifier.
FIG. 2 is a circuit diagram of the block diagram shown in FIG. 1.
3 is a circuit diagram illustrating a configuration of a high frequency power amplifier to which a drain bias modulation circuit according to a first embodiment of the present invention is applied.
4 is a circuit diagram illustrating a configuration of a high frequency power amplifier to which a drain bias modulation circuit according to a second embodiment of the present invention is applied.
FIG. 5 is a diagram for describing an operation of the drain bias modulation circuit of FIG. 4.
6 is a graph illustrating one characteristic of a transistor that may be included in a high frequency power amplifier of the present invention.

The following detailed description of the invention refers to the accompanying drawings, which illustrate, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different, but need not be mutually exclusive. For example, certain features, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the invention in connection with an embodiment. It is also to be understood that the position or arrangement of the individual components within each disclosed embodiment may be varied without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is to be limited only by the appended claims, along with the full scope of equivalents to which such claims are entitled, if properly explained. In the drawings, like reference numerals refer to the same or similar functions throughout the several views.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the present invention.

[Preferred Embodiment of the Present Invention]

Common high frequency power amplification device

1 is a view for explaining the operating principle of a high frequency power amplifier to which a general drain bias modulation circuit is applied.

Referring to FIG. 1, it may be said that the drain bias modulation circuit 10 modulates the drain bias of the power amplifier 20 as a whole.

The input signal of the high frequency power amplifier may be a high frequency signal (RF signal), and the drain bias modulation circuit 10 receives the RF signal and outputs envelope information, that is, change information of magnitude of the corresponding signal. Based on this, the magnitude of the drain bias voltage of the transistor included in the power amplifier 20 is adjusted. The input RF signal may be a sampled signal, and a power supply voltage Vs may be supplied for the operation of the drain bias modulation circuit 10. In general, the drain bias voltage of a transistor or the like included in a communication high frequency power amplifier is fixed. However, a signal such as a code division multiple access (CDMA) or the like changes in size in real time. Although the magnitude of the input signal changes in real time, a constant drain bias voltage magnitude of the transistor included in the amplifier leads to a decrease in efficiency. The drain bias modulation circuit 10 functions to prevent the efficiency of the power amplifier from being lowered for a signal whose magnitude changes in real time. Specifically, the drain bias modulation circuit 10 detects a change in the magnitude of the input signal, lowers the drain bias voltage of the power amplifier 20 when the magnitude of the input signal is small, and conversely, when the magnitude of the input signal is large, the power amplifier. The drain bias voltage of 20 is raised to increase the average efficiency.

FIG. 2 is a circuit diagram of a high frequency power amplifier to which the drain bias modulation circuit of FIG. 1 is applied.

Referring to FIG. 2, the drain bias modulation circuit 10 selectively turns on / off an output signal of an envelope detector 11 and an envelope detector 11 that receive an RF signal and output envelope information thereof as a gate input. The first transistor TR1 and the power supply voltage Vs are applied to the DC converter 12 and the source of the first transistor TR1 which converts the voltage into a predetermined magnitude and inputs the drain of the transistor TR1. Capacitor C1 is included. In addition, the power amplifier 20 includes a second transistor TR2 that receives an RF signal as a gate and amplifies and outputs the RF signal. The power supply voltage Vs and the voltage applied to the source of the first transistor TR1 are applied together to the drain of the second transistor TR2. As shown in FIG. 2, an inductor L is positioned at a drain of the second transistor TR2, one end of the inductor L is connected to a power supply voltage Vs, and the other end of the inductor L is connected to a capacitor. It may be connected to the source of the first transistor TR1.

The first transistor TR1 of the drain bias modulation circuit 10 may have a threshold voltage VT of a predetermined magnitude. When the output signal of the envelope detector 11 is greater than the threshold voltage V _{T When} the first transistor TR1 is ON and the output signal of the envelope detector 11 is smaller than the threshold voltage V _T. The first transistor TR1 is turned off. When the DC converter 12 receives the power supply voltage Vs (eg, 24V) and outputs the first voltage Vadd (eg, 8V), the drain of the first transistor TR1 is discharged. The first voltage Vadd is applied. When the magnitude of the RF input signal is large, since the first transistor TR1 is turned on, a voltage equal to the first voltage Vadd is additionally applied to the drain of the second transistor TR2. That is, the second transistor TR2 is applied with a voltage equal to the sum of the power supply voltage Vs and the first voltage Vadd. In this principle, when the size of the RF input signal is large, a high voltage is applied to the drain of the second transistor TR2. When the size of the RF input signal is small, a low voltage is applied to the drain of the second transistor TR2.

1st Example

3 is a diagram illustrating a configuration of a high frequency power amplifier to which the drain bias modulation circuit according to the first embodiment of the present invention is improved.

Referring to FIG. 3, the high frequency power amplifier according to the embodiment of the present invention also includes a drain bias modulation circuit 100 and a power amplifier 200.

The drain bias modulation circuit 100 receives an RF signal and outputs envelope information of the envelope detector 110 and a first transistor TR1 selectively turned on / off by using the output signal of the envelope detector 110 as a gate input. It includes. The capacitor C1 is connected to the source of the first transistor TR1. The DC converter is not included in the high frequency power amplifier of FIG. 3. That is, the power supply voltage Vs is directly applied to the drain terminal of the first transistor TR1.

The power amplifier 200 includes a second transistor TR2 that receives an RF signal as a gate and amplifies and outputs the RF signal. A sample signal having the same magnitude and phase information as the RF signal input to the gate of the second transistor TR2 may be input to the envelope detector 110 of the drain bias modulation circuit 100. The power supply voltage Vs and the voltage applied to the source of the first transistor TR1 are applied together to the drain of the second transistor TR2. As shown in FIG. 3, an inductor L is positioned at the drain of the second transistor TR2, one end of the inductor L is connected to a power supply voltage Vs, and the other end of the inductor L is connected to a capacitor. It may be connected to the source of the first transistor TR1. The drain of the second transistor TR2 may further include a decoupler 210 to prevent coupling. In addition, a capacitor C2 for DC bias voltage blocking may be connected to a gate of the second transistor TR2, and a capacitor C3 having the same function may be connected to an output terminal of the power amplifier 200. A capacitor C4 may be further connected between the drain of the second transistor TR2 and the ground to remove noise or prevent backflow.

The operation of the high frequency power amplifier of FIG. 3 is as follows. The envelope detector 110 detects the magnitude of the input RF signal in real time and applies it to the gate of the first transistor TR1. That is, if the size of the RF input signal is large, a large signal is applied to the gate of the first transistor TR1. If the size of the RF input signal is small, a small signal is applied to the gate of the first transistor TR1. Since the first transistor TR1 has a threshold voltage V _T of a predetermined magnitude, when the voltage input to the gate is greater than or equal to the threshold voltage V _T , the first transistor TR1 is turned ON and is smaller than the threshold voltage V _T. OFF. When the first transistor TR1 is in an OFF state, a power supply voltage Vs is applied to a drain of the second transistor TR2 included in the power amplifier 200. On the other hand, when the first transistor TR1 is turned on, a voltage corresponding to the source terminal of the first transistor TR1 is added to the drain of the second transistor TR2 included in the power amplifier 200. (Vadd), the power supply voltage (Vs) is directly supplied to the drain of the first transistor (TR1), the additional voltage (Vadd) is equal to the power supply voltage (Vs). As a result, a voltage 2Vs corresponding to twice the power supply voltage Vs is applied to the drain of the second transistor TR2.

If the magnitude of the power supply voltage Vs is 24V, when the magnitude of the RF input signal is small, only 24V is applied to the drain of the transistor TR2 of the power amplifier 200, and when the magnitude of the RF input signal is large. A voltage of 48V is applied to the drain of the transistor TR2 of the power amplifier 200.

By doing so, efficient amplification can be achieved compared to a power amplifier having a fixed drain bias voltage for an RF input signal whose magnitude changes in real time.

In addition, according to the embodiment shown in Figure 3, there is no need for a DC converter or a regulator that performs a similar operation. Since a DC converter or a regulator has a limited power capacity, it is necessary to use several elements for generating a large power. Therefore, the size of the circuit becomes very large. In the embodiment shown in FIG. 3, the power supply voltage Vs that can be supplied from a system to which an external high frequency power amplification device is applied is used as it is. It can be powered up enough and can be simplified in terms of circuit design.

Second Example

4 is a diagram illustrating a configuration of a high frequency power amplifier using a drain bias modulation circuit according to a second embodiment of the present invention.

4, in the high frequency power amplifier according to the second embodiment, N transistors may be included in the drain bias modulation circuit 100. In FIG. 4, a case in which four transistors TR1, TR2, TR3, and TR4 are included for convenience of description, is sufficient if two or more transistors are included. Meanwhile, an RF signal input to the gate of the transistor TR5 included in the power amplifier 200 may be sampled and input to the envelope detector 110 of the drain bias modulation circuit 100. For this purpose, the power amplifier 200 An inductor L and a capacitor C7 may be further included in the gate of the transistor TR5. One end of the inductor L may be connected to the gate of the transistor TR5, and the other end thereof may be connected to the input terminal of the envelope detector 110. The capacitor C7 may be connected between the other end of the inductor L and the connection path of the envelope detector 110. The capacitor C7 enables sampling of the RF input signal targeted for envelope detection and is also responsible for blocking the gate bias voltage.

The output signals of the envelope detector 110 are all applied to the gates of the transistors TR1, TR2, TR3, and TR4, the drains are all connected to the power supply voltage Vs, and the sources are all transistors of the power detector 200. (TR5) is connected to the drain. Capacitors C1, C2, C3, and C4 may be connected between the sources of the transistors TR1, TR2, TR3, and TR4 of the drain bias modulation circuit 100 and the drain of the transistor TR5 of the power detector 200, respectively.

By using a plurality of transistors (TR1, TR2, TR3, TR4) having different threshold voltages (V _T1 , V _T2 , V _T3 , V _T4 ), selective on / off of the transistors TR1, TR2, TR3, TR4 can be achieved. It becomes possible.

FIG. 5 is a diagram for describing an on / off operation and output voltages of the plurality of transistors TR1, TR2, TR3, and TR4 included in the drain bias modulation circuit 100.

It is assumed that the threshold voltages of the transistors TR1, TR2, TR3, and TR4 are V _T1 , V _T2 , V _T3 , and V _T4 , respectively, and the magnitude of each threshold voltage is V _T1 <V _T2 <V _T3 <V _T4 .

Referring to FIG. 5, when the magnitude S of the RF input signal is smaller than the threshold voltage V _T1 of the first transistor TR1, all the transistors TR1, TR2, TR3, and TR4 of the drain bias module circuit 100 are included. ) Is turned off. Accordingly, only the power supply voltage Vs is applied to the transistor drain of the power amplifier 200. That is, the drain bias voltage Vout of the power amplifier 200 becomes Vs.

On the other hand, when the magnitude S of the RF input signal is V _T1 ≤ S <V _T2 , only the first transistor TR1 is turned on. Accordingly, the voltage Vs from the source of the first transistor TR1 is additionally applied to the drain of the transistor TR5 of the power amplifier 200 together with the power supply voltage Vs. In other words, the drain bias voltage Vout of the transistor TR5 is 2Vs.

When the magnitude S of the RF input signal is V _T2 ≤ S <V _T3 , the first transistor TR1 and the second transistor TR2 are turned on. Accordingly, the drain of the transistor TR5 of the power amplifier 200 is supplied from the source of the second transistor TR2 and the voltage Vs supplied from the source of the first transistor TR1 together with the power supply voltage Vs. The voltage Vs is additionally applied. In other words, the drain bias voltage Vout of the transistor TR5 is 3Vs.

When the magnitude S of the RF input signal is V _T3 ≤ S <V _T4 , the first transistor TR1, the second transistor TR2, and the third transistor TR3 are turned on. Accordingly, in the drain of the transistor TR5 of the power amplifier 200, together with the power supply voltage Vs, from the source of the first transistor TR1, the source of the second transistor TR2, and the source of the third transistor TR3. The voltage Vs supplied is additionally taken. That is, the drain bias voltage Vout of the transistor TR5 is 4Vs.

When the magnitude S of the RF input signal is V _T4 ≤ S, all of the first to fourth transistors TR1, TR2, TR3, and TR4 are turned on. Accordingly, the voltage Vs supplied from the sources of the first to fourth transistors TR1, TR2, TR3, and TR4 is additionally applied to the drain of the transistor TR5 of the power amplifier 200 along with the power supply voltage Vs. do. In other words, the drain bias voltage Vout of the transistor TR5 is 5Vs.

According to this configuration, that is, the configuration in which the drain bias modulation circuit 100 includes N transistors having different characteristics, the N transistors are selectively turned on / off according to the magnitude of the RF input signal. Therefore, the transistor drain voltage of the power amplifier 200 is adjusted in N + 1 steps. For example, when the magnitude of the power supply voltage Vs is 8V, the transistor drain voltage of the power amplifier 200 may be 8V, 16V, 24V, 32V, and 40V according to the magnitude of the RF input signal. According to this, since the transistor drain bias of the power amplifier 200 is sensitively adjusted according to the size of the RF input signal, a decrease in amplification efficiency can be prevented to the maximum. The amplification efficiency can be improved as much as possible.

In the above, the transistor included in the high frequency power amplifier according to the embodiment of the present invention is illustrated as a field effect transistor (FET) (eg, LDMOS FET, GaAs FET, GaN HEMT FET), but this is BJT. (Bipolar Junction Transistor) and the like may be implemented. When implemented by being replaced with BJT, the drain, gate and source in the above description may be replaced by collector, base and emitter, respectively.

FIG. 6 is a diagram illustrating an efficiency of an output power among characteristics of an LDMOS FET as an example. As an example, this graph shows the output power vs. drain power efficiency of Freescale's LMDOS FET (Part number: MRFE6VP61k25HR6).

As shown in FIG. 6, when the output power is high, the efficiency is high when the drain bias voltage VDD is large. When the output power is low, the efficiency is high when the drain bias voltage VDD is low.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, Those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.

Therefore, the spirit of the present invention should not be construed as being limited to the above-described embodiments, and all of the equivalents or equivalents of the claims, as well as the following claims, I will say.

100: drain bias modulation circuit
110: envelope detector
200: power amplifier
210: decoupler

Claims (8)

delete A drain bias modulation circuit for outputting a voltage corresponding to a power supply voltage or a multiple of the power supply voltage according to the magnitude of the input signal; And
An output voltage of the drain bias modulation circuit is applied to a drain, and includes a power amplifier having an amplifying transistor for amplifying and outputting the input signal input to a gate;
The drain bias modulation circuit,
At least one transistor to which the power supply voltage is applied to a drain, and a source of which is connected to the drain of the amplifying transistor; And
And an envelope detector for detecting the magnitude of said input signal and inputting it to a gate of said at least one transistor. 3. The method of claim 2,
Wherein said at least one transistor has a different threshold voltage and is selectively turned on or off in response to a signal from the envelope detector. 3. The method of claim 2,
And a capacitor is respectively connected between the source of the one or more transistors and the drain of the amplifying transistor. 3. The method of claim 2,
And a power source voltage and a voltage supplied from a source of the one or more transistors are applied to a drain of the amplifying transistor. 3. The method of claim 2,
The power amplifier includes an inductor connected to the drain of the amplifying transistor,
The power supply voltage is applied to one end of the inductor, and the other end of the inductor is a high frequency power amplifier to which a drain bias modulation circuit is applied. The method according to claim 6,
And a gate of the amplifying transistor is connected to an input of the envelope detector. 8. The method of claim 7,
At least one of an inductor or a capacitor is connected between a gate of the amplifying transistor and an input terminal of the envelope detector.

Images