KR101374103B1 - Liquid crystal display device and driving method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a driving method thereof which can simplify a structure and reduce power consumption.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes: a liquid crystal panel including a plurality of pixel cells configured to display color images by combining monochrome images displayed on adjacent horizontal lines during first to third subframes of one frame; A driving integrated circuit mounted on the liquid crystal panel and inverted in polarity of an image signal in units of the sub-frame, and supplied to each pixel cell; and connected to a horizontal line of the liquid crystal panel to control the driving integrated circuit. And a gate driving circuit for driving.

With this arrangement, the present invention can improve the charging characteristics of the pixel cells and reduce the power consumption by dividing one frame into subframes for red, green, and blue and inverting the polarity of the image signal in each subframe unit. have.

Integrated circuit, pixel cell, charge, pixel electrode, image signal, polarity

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY DEVICE AND DRIVING METHOD THEREOF}

1 illustrates a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a diagram illustrating a driving integrated circuit according to a first embodiment of the present invention illustrated in FIG. 1.

FIG. 3 is a diagram illustrating a signal controller shown in FIG. 2. FIG.

4 is a view showing the gate drive circuit shown in Fig.

5 is a driving waveform diagram of an N frame in a method of driving a liquid crystal display according to a first embodiment of the present invention;

FIG. 6 is a diagram showing a polar pattern of an image signal displayed on a liquid crystal panel according to the driving method shown in FIG.

7 is a driving waveform diagram of an N + 1 frame in a method of driving a liquid crystal display according to a first embodiment of the present invention.

8 is a diagram illustrating a driving integrated circuit according to a second exemplary embodiment of the present invention illustrated in FIG. 1.

FIG. 9 is a diagram illustrating a boost circuit shown in FIG. 8. FIG.

10 is a view for explaining a liquid crystal display and a driving method thereof according to the second embodiment of the present invention.

FIG. 11 is another diagram for describing a liquid crystal display and a driving method thereof according to the second embodiment of the present invention; FIG.

12 illustrates a liquid crystal display according to a third exemplary embodiment of the present invention.

FIG. 13 is a view showing the gate driving circuit shown in FIG. 12; FIG.

14 is a waveform diagram illustrating a method of driving a liquid crystal display according to a third exemplary embodiment of the present invention.

15 is a diagram illustrating a liquid crystal display according to a fourth exemplary embodiment of the present invention.

FIG. 16 is a view showing the gate driving circuit shown in FIG.

17 is a waveform diagram illustrating a method of driving a liquid crystal display according to a fourth exemplary embodiment of the present invention.

Description of the Related Art [0002]

100: liquid crystal panel 102: lower substrate

104: upper substrate 110: pixel cell

112: thin film transistor 114: pixel electrode

120: gate driving circuit 130: driving integrated circuit

200: flexible printed circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof capable of simplifying a structure and reducing power consumption.

In general, a liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field.

To this end, a liquid crystal display device includes a liquid crystal panel composed of pixel cells in which liquid crystal is formed between two glass substrates and arranged in a matrix form, and switch elements for switching signals supplied to the pixel cells, And a back light unit (back light unit) for irradiating light to the liquid crystal panel.

In recent years, the number of signal lines or the number of circuit components of a liquid crystal panel has been reduced, so that a thin, light and inexpensive liquid crystal display device has been developed. Accordingly, Korean Unexamined Patent Application Publication No. 2003-39972 discloses that by installing one integrated driving chip for driving the liquid crystal panel in the peripheral area of the display area, it is possible to reduce the process time and the defect rate required for mounting the chip, On glass single chip liquid crystal display device has been proposed.

However, the on-glass single chip liquid crystal display has the following problems.

First, there is a disadvantage in that the number of data lines supplying image signals to the liquid crystal panel is large because the different color pixels constituting the unit pixels are arranged in the horizontal direction (gate line direction) of the liquid crystal panel.

Second, since the size of the integrated driving chip is increased due to the increase in the number of data lines, there is a problem that it cannot be applied to anything other than a small liquid crystal panel (e.g., a resolution of 360 x 160).

Third, there is a disadvantage that an additional circuit such as a selection circuit is required to reduce the number of data lines.

Fourth, during the active period of the gate line, the analog pixel data is supplied to the plurality of data lines by time division using the selection circuit to reduce the charging time of the pixel data, and the resolution of the liquid crystal panel must be designed in consideration of the charging time of the pixel data .

Fifth, there is a problem that power consumption is high by inverting the analog pixel data output from each channel of the integrated driving chip in units of horizontal lines.

Accordingly, in order to solve the above problems, the present invention is to provide a liquid crystal display and a driving method thereof that can simplify the structure and reduce the power consumption.

In addition, the present invention provides a liquid crystal display device and a driving method thereof for improving data charging characteristics.

A liquid crystal display according to an exemplary embodiment of the present invention for achieving the above technical problem is a plurality of display of a color image by combining a single color image displayed on adjacent horizontal lines during the first to third sub-frame of one frame A liquid crystal panel having pixel cells formed thereon, a driving integrated circuit mounted on the liquid crystal panel and inverting polarities of image signals in the sub-frame units, and supplied to the pixel cells, and connected to a horizontal line of the liquid crystal panel; And a gate driving circuit driving the horizontal line by controlling the integrated circuit.

In a method of driving a liquid crystal display according to an exemplary embodiment of the present invention, pixel cells of the same color are repeatedly arranged along a direction of a gate line corresponding to a horizontal line direction, and each other along a direction of a data line crossing the gate line. And a liquid crystal panel in which three pixel cells of different colors are repeatedly arranged, and using one driving integrated circuit mounted on the liquid crystal panel, divides one frame into first to third subframes, and in each of the subframes. And displaying a color image by displaying another monochrome image, wherein the monochrome images of adjacent sub-frames have different polarities.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings and embodiments.

1 is a diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the liquid crystal display according to the first exemplary embodiment of the present invention displays a plurality of pixel cells 110 to display a color image of one frame by combining monochrome images displayed on different horizontal lines during a plurality of subframes. A liquid crystal panel (100) having a panel), a driving integrated circuit (130) mounted on the liquid crystal panel (100), and inverting the polarity of an image signal in units of subframes and supplying the pixel signals to the pixel cells (110) in a horizontal line. A gate driving circuit 120 formed in the liquid crystal panel 100 so as to be connected to the horizontal line of the panel 100 and driving the horizontal line under the control of the driving integrated circuit 130, and attached to the liquid crystal panel 100 to drive the horizontal line. It includes a flexible printed circuit 200 for connecting the integrated circuit 130 to an external drive system (not shown).

The liquid crystal panel 100 includes a lower substrate 102 and an upper substrate 104 which are bonded together to face each other, a spacer (not shown) for maintaining a constant cell gap between the two substrates 102 and 104, And a liquid crystal layer (not shown) formed in the liquid crystal space.

The lower substrate 102 includes a display region corresponding to the upper substrate 104 and a non-display region excluding the display region.

A plurality of data lines DL1 to DLm are formed in the display region of the lower substrate 102 so as to be spaced apart from each other by a predetermined distance in the first direction (vertical direction) A plurality of gate lines GL1 to GLn formed in parallel to each other in a horizontal direction and a plurality of pixel cells 110 formed in each region defined by a plurality of data lines DL1 to DLm and gate lines GL1 to GLn, . At this time, the data lines DL1 to DLm to which the image signals are supplied have a smaller number than the gate lines GL to which the gate-on voltage is supplied.

Each of the pixel cells 110 includes a thin film transistor 112 connected to the gate lines GL1 to GLn and data lines DL1 to DLm and a pixel electrode 114 connected to the thin film transistor 112 .

The thin film transistor 112 includes a gate electrode connected to the gate lines GL1 to GLn, a source electrode connected to the data lines DL1 to DLm, and a drain electrode connected to the pixel electrode 114. Accordingly, each of the thin film transistors 112 is switched in accordance with the gate-on voltage supplied to the gate line GL to supply an image signal supplied from each of the data lines DL1 to DLm to each pixel electrode 114. [

The length of the short side of the pixel electrode 114 parallel to the data lines DL1 to DLm is formed to be shorter than the long side of the gate lines GL1 to GLn. Accordingly, the pixel electrode 114 has a horizontal stripe shape.

In the non-display area of the lower substrate 102, a gate driving circuit 120 connected to each of the plurality of gate lines GL1 to GLn is formed, and a driving integrated circuit 130 is mounted.

The upper substrate 104 includes a color filter, a common electrode, a light shielding layer, and the like. Here, the common electrode may be formed on the lower substrate 102 according to the liquid crystal formed on the liquid crystal layer.

The color filter is formed by repeatedly forming a red (R) color filter, a green (G) color filter and a blue (B) color filter in the direction of the data lines DL1 to DLm and also along the direction of the gate lines GL1 to GLn And are formed in the same color.

The common electrode may be formed on the front surface of the upper substrate 104 or in a line shape so as to face the pixel electrode 114 to form a vertical electric field in the liquid crystal layer. Here, the common electrode may be formed on the lower substrate 102 so as to be in parallel with the pixel electrode 114 to form a horizontal electric field in the liquid crystal layer.

The light shielding layer is formed on the upper substrate 104 so as to overlap with the remaining region except for the opening region overlapping the pixel electrode 114.

The pixel cells of red (R), green (G), and blue (B) in which the red (R) color filter, the green (G) color filter and the blue Thereby forming a unit pixel.

The flexible printed circuit 200 is attached to a pad portion provided in a non-display area of the lower substrate 102. [ The flexible printed circuit 200 transfers the source data signal Data and the synchronization signals DE, DCLK, Hsync, and Vsync supplied from the drive system to the drive integrated circuit 130.

The driving integrated circuit 130 is mounted on an integrated circuit mounting portion formed in a non-display region of the lower substrate 102 so as to have a plurality of input / output pads. Accordingly, the input / output bumps provided in the driving integrated circuit 130 are mounted so as to be electrically connected to the respective input / output pads of the integrated circuit mounting portion.

The driving integrated circuit 130 uses one of the synchronizing signals DE, DCLK, Hsync and Vsync supplied from the flexible printed circuit 200 to generate one frame corresponding to one period of the vertical synchronizing signal Vsync And generates a gate driving signal and a data control signal for driving the first to third subframes.

In addition, the driving integrated circuit 130 aligns the source data signal Data with the red data R, the green data G, and the blue data B corresponding to each of the first to third subframes. Data lines are converted during the active period of the subframe except for the first blanking period that is the first half of the subframe and the second blanking period that is the second half of the subframe by converting the data R, G, and B into an image signal as an analog signal. Supply to (DL). At this time, the image signal has the same polarity within each subframe, but has the polarity reversed in units of subframes. Here, the first blanking section of each subframe is a section between the beginning of each subframe and the first horizontal section, and the second blanking section of each subframe is a section between the last horizontal section of each subframe and the beginning of each subframe. to be.

2 is a block diagram illustrating a driving integrated circuit according to a first embodiment of the present invention.

2, the driving integrated circuit 130 according to the first embodiment of the present invention may include a signal relay 310, a first power generator 320, a clock generator 322, and a reference voltage. The setting unit 324, the second power generator 326, the signal controller 330, the control signal generator 340, the boost circuit 350, the gray voltage generator 360, and the common voltage generator 370. And a data converter 380.

The signal relay unit 310 relays the source data signal Data and the synchronization signals DE, DCLK, Hsync, and Vsync supplied from the flexible printed circuit 200 to the signal control unit 330.

The clock generating unit 322 generates a clock for driving the first and second power generating units 320 and 326.

The first power generator 320 generates the first power source, that is, the first and second power sources, according to the clock supplied from the clock generator 322, using the input power Vin supplied from the flexible printed circuit 200, To generate voltages VSP and VSN. In this case, the passive elements such as the resistor 210, the capacitor 220, and the inductor 230 mounted on the flexible printed circuit 200 may be connected to the first power generator 320 through the power signal lines 321a, 321b, and 321c. ) Is used to bias the first and second reference voltages VSP and VSN generated by the first power generator 320 or to set an option function of the driving integrated circuit 130.

The second power supply generator 326 generates a second power supply necessary for driving the liquid crystal panel 100 using the first and second reference voltages VSP and VSN generated by the first power generator 320, 1 and the second driving voltages Vdd and Vss, the integrated circuit driving voltage Vcc, the gate on voltage Von and the gate off voltage Voff.

The reference voltage setting unit 324 sets the levels of the first and second reference voltages VSP and VSN supplied from the first power generator 320 to the gray voltage generator 360. [

The signal control unit 330 controls the driving of the signal relay unit 310 and controls the internal circuit block of the driving integrated circuit 130.

In addition, the signal controller 330 aligns the source data signal Data supplied from the signal relay 310 to be suitable for driving the liquid crystal panel 100, and arranges the aligned data R, G, and B for each sub. The data is rearranged so as to correspond to the frame and supplied to the data converter 380.

Specifically, the signal controller 330 aligns the source data signal Data supplied from the signal repeater 310 to match the resolution of the liquid crystal panel 100.

The signal controller 330 rearranges the red, green, and blue data R, G, and B of the aligned source data signal Data in units of one horizontal section so as to correspond to each of the first to third subframes. Supply to converter 380. That is, the signal controller 330 rearranges the red data R of the source data signal Data to the first subframe data, and the green data G of the source data signal Data to the second subframe data. The rearrangement is performed, and the blue data B of the source data signal Data is rearranged to the third subframe data.

The signal control unit 330 transmits the synchronization signals DE, DCLK, Hsync, and Vsync supplied from the signal relay unit 310 to the control signal generation unit 340.

As illustrated in FIG. 3, the control signal generator 340 may include a first data enable DE, a first dot clock DCLK, and a first vertical synchronization signal Vsync transmitted from the signal controller 330. And a data control signal DCS and a gate driving signal GDS for supplying an image signal to each pixel cell 110 according to each subframe using at least one of the first horizontal synchronization signal Hsync.

To this end, the control signal generator 340 includes a frequency modulator 342, a data control signal generator 344, and a gate driving signal generator 346.

The frequency modulator 342 applies the first data enable DE, the first dot clock DCLK, the first vertical sync signal Vsync, and the first horizontal sync signal Hsync to be suitable for driving each subframe. Multiply by three times and generate a data control signal by generating the multiplied second data enable DE ', the second dot clock DCLK', the second vertical sync signal Vsync 'and the second horizontal sync signal Hsync'. The unit 344 and the gate driving signal generator 346 are respectively supplied.

The data control signal generator 344 may include the second data enable DE ′, the second dot clock DCLK ′, the second vertical synchronization signal Vsync ′, and the second horizontal signal supplied from the frequency modulator 342. The data control signal DCS for controlling the data converter 380 is generated using at least one of the synchronization signals Hsync '. Here, the data control signal DCS includes a data start signal DST, a data shift clock DSC, a data output signal DOE and a data polarity signal DPS. In this case, the data polarity signal DPS is inverted in units of subframes in order to invert the polarity of the image signals supplied to the data lines DL in units of subframes.

The gate driving signal generator 346 may include the second data enable DE ′, the second dot clock DCLK ′, the second vertical synchronization signal Vsync ′, and the second horizontal signal supplied from the frequency modulator 342. The gate driving signal GDS for driving the gate driving circuit 120 is generated using at least one of the synchronization signals Hsync '. In this case, the gate driving signal GDS includes the gate start signal RVst, the first and second sub frame signals SFS1 and SFS2, and the first to i th clock signals RCLK1 to RCLKi.

The gate start signal Vst is generated only in the initial section of each subframe to start the driving of the gate driving circuit 120.

Each of the first to i th clock signals RCLK1 to RCLKi is sequentially delayed in phase so as to have a pulse width for turning on the thin film transistor in each subframe. In this case, i may be two or more natural numbers according to the gate driving circuit 120.

Each of the first and second subframe signals SFS1 and SFS2 is generated differently according to each subframe of one frame. That is, the gate driving signal generator 346 counts the second vertical synchronization signal in units of frames, and according to the counting result, the first and second sub frame signals SFS1, which are in a low state in the first sub frame, are counted. Create SFS2); Generating a first sub frame signal SFS1 in a low state and a second sub frame signal SFS2 in a high state in a second sub frame; In the third subframe, the first subframe signal SFS1 in the high state and the second subframe signal SFS2 in the low state are generated or the first and second subframe signals SFS1 and SFS2 in the high state. .

The booster circuit 350 uses the gate-on voltage Von and the gate-off voltage Voff supplied from the second power supply generator 326 to generate the gate start signal RVst and the gate- and raises the voltage levels of the i clock signals RCLK1 to RCLKi. Here, the gate-on voltage Von is a voltage for turning on the thin film transistor 112 of each pixel cell 110, and the gate-off voltage Voff is a voltage for turning off the thin film transistor 112 . The voltage booster circuit 350 drives the gate start signal Vst and i clock signals CLK1 to CLKi boosted through the gate driving signal transmission line 140 formed in the non-display area of the lower substrate 102. Supply to the furnace (120).

In addition, the booster circuit 350 bypasses the first and second sub-frame signals SFS1 and SFS2 supplied from the control signal generator 340 to pass the gate driving signal transmission line 140 to the gate driving circuit 120. To feed.

The common voltage generator 370 may control the first and second driving voltages Vdd and Vss and the control signal generator 340 supplied from the second power generator 326 through the passive element of the flexible printed circuit 200. The common voltage Vcom to be supplied to the common electrode of the liquid crystal panel 100 is generated by using the data polarity signal DPS. At this time, the common voltage generator 370 generates the common voltage inverted in units of subframes by inverting the common voltage Vcom to the high state VcomH or the low state VcomL according to the inverted data polarity signal DPS. do. Here, the common voltage Vcom becomes a low state VcomL when the data polarity signal DPS is high, and becomes a high state VcomH when the data polarity signal DPS is low.

The gradation voltage generator 360 divides the first and second reference voltages VSP and VSN supplied from the first power generator 320 into a plurality of gradation voltages and supplies the gradation voltages to the data converter 380. Here, the gradation voltage generator 360 generates ^2N positive (+) gradation voltages and negative (-) gradation voltages when the source data signal Data is N bits.

The data conversion unit 380 includes a shift register 381, a latch unit 383, a digital-analog conversion unit 385, a buffer unit 387, and a selection unit 389.

The shift register 381 sequentially shifts the data start signal DST in accordance with the data shift clock DSC supplied from the control signal generator 340 to generate the shift signal SS. At this time, the shift register 381 may be a bi-directional shift register driven in both directions in accordance with a direction signal supplied from the signal controller 330.

The latch unit 383 sequentially latches subframe data R, G, and B for one horizontal line supplied from the signal control unit 330 according to the shift signal SS supplied from the shift register 381. The latch unit 383 supplies the sub-frame data Rdata for one horizontal line latched in accordance with the data output signal DOE supplied from the control signal generator 340 to the digital-analog converter 385. do.

The digital-analog converting unit 385 converts the latched data Rdata supplied from the latch unit 383 into analog data using the plurality of positive polarity gradation voltages and negative polarity gradation voltages supplied from the gradation voltage generator 360 To the positive polarity and negative polarity image signals (PVS, NVS). At this time, the digital-analog converter 385 selects one gradation voltage corresponding to the gray level value of the latched data Rdata among the plurality of positive polarity gradation voltages as the positive polarity image signal PVS, One of the negative polarity gradation voltages corresponding to the gradation value of the latched data Rdata is selected as the negative polarity image signal NVS.

The buffer unit 387 receives the first and second driving voltages Vdd and Vss supplied from the first power generation unit 320 through the passive elements of the flexible printed circuit 200 to generate the positive and negative polarity images And buffers each of the signals (PVS, NVS). At this time, the buffer unit 387 amplifies and outputs the positive and negative polarity image signals PVS and NVS in consideration of the load of the data line DL.

The selection unit 389 selects the positive or negative polarity image signals PVS and NVS supplied from the buffer unit 387 according to the data polarity signal DPS supplied from the control signal generation unit 340, (DL1 to DLm). At this time, the polarity of the image signal output from the selecting unit 389 is inverted in units of subframes and frames according to the data polarity signal DPS.

In FIG. 1, the gate driving circuit 120 is formed in the non-display area of the lower substrate 102 to be connected to each of the plurality of gate lines GL together with the process of forming the thin film transistor 112. The gate driving circuit 120 generates a gate-on voltage according to the boosted gate driving signals Vst, SFS1, SFS2, CLK1 to CLKi supplied from the driving integrated circuit 130, thereby closing the gate lines GL. Drive in the sub-frame interlace method. In this case, the boosted gate driving signals Vst, SFS1, SFS2, CLK1 to CLKi are supplied to the gate driving circuit 120 through the plurality of gate driving signal transmission lines 140 formed in the non-display area of the lower substrate 102. do.

For this purpose, as shown in FIG. 4, the gate driving circuit 120 includes a selector 622 and n stages 6241 to 624n.

The selector 622 selectively outputs the gate start signal Vst according to the first and second subframe signals SFS1 and SFS2 supplied from the driving integrated circuit 130. That is, the selector 622 supplies the gate start signal Vst to the first stage 6241 according to the first and second subframe signals SFS1 and SFS2 in the low state. The selector 622 supplies the gate start signal Vst to the second stage 6242 according to the first subframe signal SFS1 in the low state and the second subframe signal SFS2 in the high state. In addition, the selector 622 according to the first subframe signal SFS1 in the high state and the second subframe signal SFS2 in the low state or the first and second subframe signals SFS1 and SFS2 in the high state. The gate start signal Vst is supplied to the third stage 6241.

Each of the n stages 6241 to 624n is driven according to the gate start signal Vst to supply a clock signal supplied from one of the i clock signal lines to the corresponding gate line. At this time, the n stages 6241 to 624n are sequentially connected to i clock signal lines three by three. The clock signal supplied to each gate line from each of the stages 6241 to 624n turns on the thin film transistor 112 of the pixel cell 110 as a gate-on voltage.

Each of the 3k-2 stages (6241, 6244, ..., 624n-2) of the n stages 6241 to 624n is connected independently of each other and each clock It is connected sequentially to the signal line. The first stage 6241 of the 3k-2th stages 6241, 6244,..., 624n-2 is driven by the gate start signal Vst from the selector 622 to be driven from the first clock signal line. The first clock signal CLK1 is supplied to the first gate line GL1. In addition, except for the first stage 6241, each of the remaining 3k-2 (where k is 2 to n / 3), and each of the 3rd stages 6242,..., 624n-2 is the previous 3k-2 (where k is 1 to 3). It is driven by the clock signal output from the n / 3-1) th stage 6241, ..., 624n-5, and supplies the clock signal from the corresponding clock signal line to the corresponding gate line. In addition, each of the 3k-2th stages 6241, 6244,..., And 624n-2 is a 3j-2 (where j is k + 1) stage (6244, 6247, ..., 624n + 1). It can be reset by the output signal of. Here, the n + 1th stage (not shown) is a dummy stage for resetting the n-2th stage 624n-2.

Each of the 3k-1st stages 6242, 6245, ..., 624n-1 of the n stages 6241 to 624n is connected to each other and is sequentially connected to each clock signal line. The first stage 6242 of the 3k-1st stages 6242, 6245,..., 624n-1 is driven by the gate start signal Vst from the selector 622 to be driven from the first clock signal line. The first clock signal CLK1 is supplied to the second gate line GL2. In addition, except for the first stage 6242, each of the remaining 3k-1 (where k is 2 to n / 3) and each of the 3rd stages 6245, ..., 624n-1 is the previous 3k-1 (where k is 1 to 3). It is driven by the clock signal output from the n / 3-1) th stage 6242, ..., 624n-4, and supplies the clock signal from the corresponding clock signal line to the corresponding gate line. In addition, each of the 3k-1st stages 6242, 6245,..., And 624n-1 has a value from the 3j-1 (where j is k + 1) stages 6245, 6248,. It can be reset by the output signal of. Here, the n + 2th stage (not shown) is a dummy stage for resetting the n−1th stage 624n−1.

Each of the 3kth stages 6203, 6246, ..., 624n of the n stages 6241 to 624n is connected to each other and sequentially connected to each clock signal line. The first stage 6203 of the 3k th stages 6241, 6246,..., 624n is driven by the gate start signal Vst from the selector 622 to be driven by the first clock signal line from the first clock signal line. The signal CLK1 is supplied to the third gate line GL3. In addition, except for the first stage 6241, each of the remaining 3k stages (k is 2 to n / 3), and each of the 3rd stages 6262, ..., 624n is the previous 3k stage, where k is 1 to n / 3-1. It is driven by the clock signal output from the second stage 6241, ..., 624n-3 to supply the clock signal from the corresponding clock signal line to the corresponding gate line. In addition, each of the 3kth stages 6241, 6246, ..., and 624n is reset by an output signal from the 3jth stage, where j is k + 1. Can be. Here, the n + 3th stage (not shown) is a dummy stage for resetting the nth stage 624n.

5 is a waveform diagram illustrating a method of driving a liquid crystal display according to a first embodiment of the present invention.

The driving method of the liquid crystal display according to the first exemplary embodiment of the present invention will be described with reference to FIG. 5 as follows.

In the Nth frame, during the active period of the first subframe 1SF except for the first and second blanking periods BP1 and BP2, the gate driving circuit 120 is gated under the control of the driving integrated circuit 130. The on voltage is sequentially supplied to the 3k-2 th gate line GL3k-2, and the driving integrated circuit 130 is positively red (R +) according to the data polarity signal DPS in the high state so as to be synchronized with each gate on voltage. ) The image signal Vdata is supplied to the data lines DL1 to DLm. Accordingly, during the first subframe 1SF, each pixel cell 110 connected to the 3k-2 th gate line GL3k-2 has a common voltage VcomL in a low state and a red (R +) image signal having a positive polarity. A positive red image R corresponding to the difference voltage of (Vdata) is displayed.

Subsequently, during the active period of the second subframe 2SF except for the first and second blanking periods BP1 and BP2, the gate driving circuit 120 may set the gate-on voltage 3k− under the control of the driving integrated circuit 130. The driving integrated circuit 130 is sequentially supplied to the first gate line GL3k-1, and the driving integrated circuit 130 has a negative green (G-) image signal according to the data polarity signal DPS in a low state so as to be synchronized with each gate-on voltage. Vdata is supplied to the data lines DL1 to DLm. Accordingly, each pixel cell 110 connected to the 3k-1 th gate line GL3k-1 during the second subframe 2SF has a common voltage VcomH and a negative green (G-) image in a high state. A negative green image G corresponding to the difference voltage of the signal Vdata is displayed.

Subsequently, during the active period of the third subframe 3SF except for the first and second blanking periods BP1 and BP2, the gate driving circuit 120 sets the gate-on voltage according to the control of the driving integrated circuit 130 by 3kth. The driving integrated circuit 130 sequentially supplies the blue line B + image signal Vdata according to the data polarity signal DPS in the high state so as to be synchronized with each gate-on voltage. To DL1 to DLm. Accordingly, each pixel cell 110 connected to the 3kth gate line GL3k during the third subframe 3SF has a difference between the common voltage VcomL in the low state and the blue (B +) image signal Vdata of the positive polarity. A blue image B of positive polarity corresponding to the voltage is displayed.

In the N frame, only the positive red image is displayed during the first subframe 1SF, only the negative green image is displayed during the second subframe 2SF, and the positive blue color is displayed during the third subframe 3SF. By displaying only the image, as shown in FIG. 6, the polarity of the image displayed on the liquid crystal panel 110 is inverted in units of horizontal lines corresponding to the direction of the gate line.

Therefore, in the N frame, a color image in which the red, green, and blue images R, G, and B in the first to third subframes 1SF, 2SF, and 3SF are combined is displayed. In other words, in the N frame, a color image is displayed by combining the red, green, and blue images R, G, and B displayed in different horizontal lines during the first to third subframes 1SF, 2SF, and 3SF. All.

On the other hand, in the N + 1 frame, as shown in Fig. 7, the driving is inverted to the N frame. That is, each of the subframes (1SF, 2SF, 3SF) of the N + 1 frame is equal to each of the subframes (1SF, 2SF, 3SF) of the N frame except that the polarity of the image signal and the logic state of the common voltage are reversed. It is driven in the same way.

As described above, according to the present invention, by dividing one frame into red, green, and blue subframes and reversing the polarity of the image signal in each subframe unit, the charging characteristics of the pixel cells can be improved and power consumption can be reduced.

8 is a block diagram illustrating a driving integrated circuit according to a second exemplary embodiment of the present invention.

Referring to FIG. 8 and FIG. 1, the driving integrated circuit 130 according to the second embodiment of the present invention may include a signal relay 310, a first power generator 320, a clock generator 322, and a reference voltage. The setter 324, the second power generator 326, the signal controller 330, the control signal generator 340, the booster circuit 450, the gray voltage generator 360, and the data converter 380 It is configured to include.

The signal relay 310, the first power generator 320, the clock generator 322, the reference voltage setting unit 324, the second power generator 326, the signal controller 330, and the control signal generator Each of the 340 and the data converter 380 is the same as the first embodiment of the present invention shown in FIG. 2 and will be replaced with the above description.

As shown in FIG. 9, the booster circuit 450 includes first to i + 2 level shifters 7101 to 710i + 2 and a switching circuit 720.

The first level shifter 7101 uses the first and second driving voltages Vdd and Vss supplied from the second power generator 326 to supply the common voltage VcomH in the high state and the common voltage VcomL in the low state. ) That is, the first level shifter 7101 generates the common voltage VcomH in the high state using the first driving voltage Vdd, and the common voltage VcomL in the low state using the second driving voltage Vss. Create

The switching circuit 720 is switched according to the data polarity signal DPS supplied from the control signal generator 340 to be supplied from the first level shifter 7101. The common voltage VcomH in the high state or the common voltage in the low state is provided. VcomL is supplied to the common electrode of the liquid crystal panel 100. At this time, the switching circuit 720 outputs the common voltage VcomH in the high state when the data polarity signal DPS is in the low state, and outputs the common voltage VcomL in the low state in the high state.

The second level shifter 7102 may use the gate start signal RVst supplied from the control signal generator 340 using the gate on voltage Von and the gate off voltage Voff supplied from the second power generator 326. Level shifted to the gate driving circuit 120. That is, the second level shifter 7102 level shifts the gate start signal RVst of the high state to the gate on voltage Von, and level shifts the gate start signal RVst of the low state to the gate off voltage Voff. Let's do it. The level shifted gate start signal Vst is supplied to the selector 622 of the gate driving circuit 120 shown in FIG. 4.

Each of the third to i + 2 level shifters 7103 to 710i + 2 uses the gate-on voltage Von and the gate-off voltage Voff supplied from the second power generator 326. The voltage of the first to i th clock signals RCLK1 to RCLKi supplied from the 340 is level-shifted and supplied to the gate driving circuit 120. That is, each of the third to i + 2 level shifters 7103 to 710i + 2 level shifts the clock signal RCLK in the high state to the gate-on voltage Von and gates the clock signal RCLK in the low state. Level shift to the off voltage (Voff). The level shifted first to i th clock signals CLK1 to CLKi are supplied to the respective clock signal lines of the gate driving circuit 120 illustrated in FIG. 4.

As described above, the liquid crystal display including the driving integrated circuit according to the second exemplary embodiment of the present invention generates the common voltage Vcom and the gate driving signal GDS in the boosting circuit 450 to generate the driving integrated circuit 130. It can reduce the size and facilitate the circuit design.

10 is a view for explaining a liquid crystal display and a driving method thereof according to the second embodiment of the present invention.

10, the liquid crystal display according to the second exemplary embodiment of the present invention has the same configuration as the liquid crystal display according to the first exemplary embodiment of the present invention except for the driving integrated circuit 130.

The driving integrated circuit 130 has the configuration as shown in FIG. 2 or 8 and supplies the dummy voltage DV to each data line during the first blanking period BP1 of each subframe 1SF, 2SF, and 3SF. It includes the function to do it. At this time, since the voltage charged in each pixel cell is inverted into positive or negative polarity for each subframe, the dummy voltage DV is an arbitrary voltage level for precharging toward the polarity of the image signal to which the voltage of each data line is supplied. Has For example, the dummy voltage DV may be an intermediate gray voltage among the plurality of gray voltages.

The driving integrated circuit 130 supplies a dummy voltage DV to each data line during the first blanking period BP1 of each subframe 1SF, 2SF, and 3SF, thereby connecting each data line to the dummy voltage DV. Precharge to the corresponding voltage.

Accordingly, each data line is charged to a voltage corresponding to the dummy voltage DV during the first blanking period BP1 of each subframe 1SF, 2SF, 3SF, and then each subframe 1SF, 2SF, 3SF. Is charged with the positive or negative image signal Vdata corresponding to the data polarity signal DSP.

Therefore, the liquid crystal display according to the second exemplary embodiment of the present invention uses the first blanking period BP1 of each subframe 1SF, 2SF, or 3SF before the start of each subframe 1SF, 2SF, or 3SF. By pre-charging each data line, the charging characteristics of each pixel cell connected to the first horizontal line according to the polarity reversal in units of subframes 1SF, 2SF, and 3SF can be improved.

In the liquid crystal display according to the second exemplary embodiment of the present invention, each data line is precharged using the first blanking period BP1 of each subframe 1SF, 2SF, or 3SF, but is not limited thereto. As illustrated in FIG. 11, each data line may be precharged using the second blanking period BP2 of each subframe 1SF, 2SF, or 3SF. Of course, the method of preliminary charging using the second blanking period BP2 is the same as the embodiment shown in FIG. 10.

12 is a diagram illustrating a liquid crystal display according to a third exemplary embodiment of the present invention.

Referring to FIG. 12, the liquid crystal display according to the third exemplary embodiment of the present invention displays a plurality of pixel cells 110 to display a color image of one frame by combining monochrome images displayed on different horizontal lines during a plurality of subframes. ), A liquid crystal panel 800 formed on the liquid crystal panel 800, a driving integrated circuit 830 for inverting the polarity of the image signal in units of sub-frames, and supplying the pixel signals to the pixel cells 110 in the horizontal line. A gate driving circuit 820 formed in the liquid crystal panel 800 so as to be connected to the horizontal line of the panel 800 and attached to the liquid crystal panel 800 to drive the horizontal line under the control of the driving integrated circuit 830; It includes a flexible printed circuit 200 for connecting the integrated circuit 830 to an external drive system (not shown).

The liquid crystal panel 800 is configured to include the exemplary embodiment of FIG. 1 except for including dummy horizontal lines.

The dummy horizontal line is formed on the liquid crystal panel 800 to be driven before the first horizontal line is driven. In this case, the dummy horizontal line may be formed in the non-display area of the liquid crystal panel 800 or overlap the light blocking layer (not shown).

The dummy horizontal line includes a dummy gate line GL0 connected to the gate driving circuit 820, a dummy pixel cell formed in a region defined by the dummy gate line GL0 and the data lines DL1 to DLm. 810.

Each of the dummy pixel cells 810 includes a dummy thin film transistor 812 connected to the dummy gate line GL0 and the data lines DL1 to DLm, and a dummy pixel electrode 814 connected to the thin film transistor 812. It is composed. The dummy pixel electrode 814 has the same size or a smaller size than the pixel electrode 114 of the pixel cell 110 formed in the first horizontal line.

The driving integrated circuit 830 includes the embodiment related to FIG. 10 except for the timing of the gate start signal Vst.

The driving integrated circuit 830 generates a gate start signal Vst to correspond to the second blanking period BP2 of each subframe, and supplies the gate start signal Vst to the gate driving circuit 820 through the gate driving signal transmission line 140. In addition, as described with reference to FIG. 10, the driving integrated circuit 830 may be connected to the dummy gate line GL0 from the gate driving circuit 820 during the first blanking period BP1 of each subframe 1SF, 2SF, or 3SF. A dummy voltage is supplied to each data line to be synchronized with the gate-on voltage supplied to the data line.

As shown in FIG. 13, the gate driving circuit 820 includes a dummy stage 821, a selector 822, and n stages 6241 to 624n.

The dummy stage 821 is driven by the gate start signal Vst supplied from the driving integrated circuit 830 through the gate driving signal transmission line 140 to receive the i-th clock signal CLKi from the dummy gate line GL0 and Supply to selector 822.

The selector 822 is provided from the dummy stage 821 according to the first and second sub frame signals SFS1 and SFS2 supplied from the driving integrated circuit 830 through the gate driving signal transmission line 140. The clock signal CLKi is selectively output. That is, the selector 822 supplies the i-th clock signal CLKi to the first stage 6241 according to the first and second sub-frame signals SFS1 and SFS2 in the low state. In addition, the selector 822 supplies the i-th clock signal CLKi to the second stage 6242 according to the first sub frame signal SFS1 in the low state and the second sub frame signal SFS2 in the high state. . In addition, the selector 822 may be configured according to the first subframe signal SFS1 in the high state and the second subframe signal SFS2 in the low state or the first and second subframe signals SFS1 and SFS2 in the high state. The i-th clock signal CLKi is supplied to the third stage 6241.

Since the n stages 6241 to 624n are the same as the n stages shown in Fig. 4, the description above will be replaced.

The gate driving circuit 820 drives the dummy gate line GL0 at every first blanking period of each subframe, and then, according to the layout of each stage, as in the embodiment of FIG. 4, the first to nth gates. The line is driven in a three subframe interlaced manner.

14 is a waveform diagram illustrating a method of driving a liquid crystal display according to a third exemplary embodiment of the present invention.

A driving method of a liquid crystal display according to a third exemplary embodiment of the present invention will be described with reference to FIG. 14 as follows.

In the N frame, during the first blanking period BP1 of the first subframe 1SF, the gate driving circuit 820 receives an i-th clock signal having a level of a gate-on voltage under the control of the driving integrated circuit 830. The dummy gate line GL0 is supplied to the dummy gate line GL0, and the driving integrated circuit 830 supplies the dummy voltage DV to the data lines DL1 to DLm to be synchronized with the gate-on voltage. Accordingly, each of the dummy pixel cells connected to the dummy gate line GL0 is charged to the dummy voltage DV during the first blanking period BP1 of the first subframe 1SF. As a result, each data line is precharged to the dummy voltage DV during the first blanking period BP1 of the first subframe 1SF.

Subsequently, during the active period of the first subframe 1SF, the gate driving circuit 820 sequentially supplies the gate-on voltage to the 3k-2nd gate line GL3k-2 under the control of the driving integrated circuit 830. The driving integrated circuit 830 supplies the positive red (R +) image signal Vdata to the data lines DL1 to DLm according to the data polarity signal DPS in the high state in synchronization with each gate-on voltage. Accordingly, each pixel cell 110 connected to the 3k-2 th gate line GL3k-2 during the first subframe 1SF has a common voltage VcomL in a low state and a red (R +) image signal having a positive polarity ( A positive red image R corresponding to the difference voltage of Vdata) is displayed.

Similar to the first subframe 1SF, in the second subframe 2SF, each data line is precharged with the dummy voltage DV during the first blanking period BP1, and then the 3k−1 th gate line GL3k− is used. The negative green (G-) image signal Vdata is supplied to each of the data lines DL1 to DLm so as to be synchronized with the gate-on voltage supplied to 1). Accordingly, each pixel cell 110 connected to the 3k-1 th gate line GL3k-1 during the second subframe 2SF has a common voltage VcomH and a negative green (G-) image in a high state. A negative green image G corresponding to the difference voltage of the signal Vdata is displayed.

Like the first subframe 1SF, in the third subframe 3SF, each data line is precharged with the dummy voltage DV during the first blanking period BP1 and then supplied to the 3kth gate line GL3k. The positive blue (B +) image signal Vdata is supplied to each of the data lines DL1 to DLm so as to be synchronized with the gate-on voltage. Accordingly, each pixel cell 110 connected to the 3kth gate line GL3k during the third subframe 3SF has a difference between the common voltage VcomL in the low state and the blue (B +) image signal Vdata of the positive polarity. A blue image B of positive polarity corresponding to the voltage is displayed.

Therefore, in the N frame, a color image in which the red, green, and blue images R, G, and B in the first to third subframes 1SF, 2SF, and 3SF are combined is displayed. In other words, in the N frame, a color image is displayed by combining red, green, and blue images R, G, and B displayed in different horizontal lines during the first to third subframes 1SF, 2SF, and 3SF. .

On the other hand, in the N + 1 frame, it is driven in an inverted form to the N frame. That is, each of the subframes (1SF, 2SF, 3SF) of the N + 1 frame is equal to each of the subframes (1SF, 2SF, 3SF) of the N frame except that the polarity of the image signal and the logic state of the common voltage are reversed. same.

As described above, the liquid crystal display and the driving method thereof according to the third exemplary embodiment of the present invention provide a first horizontal line according to polarity reversal in units of subframes 1SF, 2SF, and 3SF by precharging each data line using a dummy horizontal line. The charging characteristic of each pixel cell connected to a line can be improved.

12 to 14 precharge each data line using the first blanking period BP1 of each subframe 1SF, 2SF, or 3SF, but the present invention is not limited thereto. Each data line may be precharged using each of the first and second blanking periods BP1 and BP2 of the 2SF and 3SF.

To this end, the liquid crystal display according to the fourth exemplary embodiment of the present invention includes upper and lower dummy horizontal lines formed on the liquid crystal panel 900, a driving integrated circuit 930, and a gate driving circuit as shown in FIG. 15. Except for 920, the embodiment includes the embodiment related to FIG. 12.

The upper dummy horizontal line is formed on the liquid crystal panel 900 to be driven before the first horizontal line is driven. In this case, the upper dummy horizontal line may be formed in the non-display area of the liquid crystal panel 900 or overlap the light blocking layer (not shown). The upper dummy horizontal line includes a dummy pixel formed in an area defined by the upper dummy gate line GL0 connected to the gate driving circuit 920, the upper dummy gate line GL0, and the data lines DL1 to DLm. It comprises a cell 810.

The lower dummy horizontal line is formed on the liquid crystal panel 900 to be driven after the last horizontal line is driven. In this case, the lower dummy horizontal line may be formed in the non-display area of the liquid crystal panel 900 or overlap the light blocking layer (not shown). The lower dummy horizontal line is a region defined by the lower dummy gate line GLn + 1 connected to the gate driving circuit 920, the lower dummy gate line GLn + 1, and the data lines DL1 to DLm. And a dummy pixel cell 810 formed therein.

Each of the dummy pixel cells 810 includes a dummy thin film transistor 812 connected to the lower dummy gate line GLn + 1 and the data lines DL1 to DLm, and a dummy pixel electrode 814 connected to the dummy thin film transistor 812. It is configured to include). The dummy pixel electrode 814 has the same size or a smaller size than the pixel electrode 114 of the pixel cell 110 formed on another horizontal line.

The driving integrated circuit 930 is substantially the same as the driving integrated circuit 830 illustrated in FIG. 12 except that the dummy voltage is supplied to each of the first and second blanking sections of each subframe. Has

As shown in FIG. 16, the gate driving circuit 920 includes upper and lower dummy stages 921a and 921b, a selector 922, and n stages 6241 to 624n.

The upper dummy stage 921a is driven by the gate start signal Vst supplied from the driving integrated circuit 930 through the gate driving signal transmission line 140 to transfer the i-th clock signal CLKi to the upper dummy gate line GL0. ) And the selection unit 922.

The selector 922 is provided from the upper dummy stage 921a according to the first and second sub frame signals SFS1 and SFS2 supplied from the driving integrated circuit 930 through the gate driving signal transmission line 140. The i clock signal CLKi is selectively supplied to the first to third stages 6241, 6242, and 6243.

Since the n stages 6241 to 624n are the same as the n stages shown in Fig. 4, the description above will be replaced.

The lower dummy stage 921b is driven by output signals from each of the n-th, n-th, and n-th stages 624n-2, 624n-1, and 624n to lower the first clock signal CLK1. Supply to gate line GLn + 1.

The gate driving circuit 920 drives the upper dummy gate line GL0 during the first blanking period of each subframe, and operates the first to nth gate lines in a three subframe interlace manner during the active period of each subframe. In addition, the lower dummy gate line GLn + 1 is driven in the second blanking period of each subframe.

17 is a waveform diagram illustrating a method of driving a liquid crystal display according to a fourth exemplary embodiment of the present invention.

A driving method of the liquid crystal display according to the fourth exemplary embodiment of the present invention will be described with reference to FIG. 17 as follows.

In the N frame, during the first blanking period BP1 of the first subframe 1SF, the gate driving circuit 920 receives the i-th clock signal having the level of the gate-on voltage under the control of the driving integrated circuit 930. The upper dummy gate line GL0 is supplied to the upper dummy gate line GL0, and the driving integrated circuit 930 supplies the dummy voltage DV to the data lines DL1 to DLm to be synchronized with the gate-on voltage. Accordingly, each of the dummy pixel cells 810 connected to the upper dummy gate line GL0 is charged to the dummy voltage DV during the first blanking period BP1 of the first subframe 1SF. As a result, each data line is precharged to the dummy voltage DV during the first blanking period BP1 of the first subframe 1SF.

Subsequently, during the active period of the first subframe 1SF, the gate driving circuit 920 sequentially supplies the gate-on voltage to the 3k-2nd gate line GL3k-2 under the control of the driving integrated circuit 930. The driving integrated circuit 930 supplies the positive red (R +) image signal Vdata to the data lines DL1 to DLm according to the data polarity signal DPS in the high state in synchronization with each gate-on voltage.

Subsequently, during the second blanking period BP2 of the first subframe 1SF, the gate driving circuit 920 may apply the i-th clock signal according to the gate-on voltage supplied to the n-th-th gate line GLn-2. The lower dummy gate line GLn + 1 is supplied, and the driving integrated circuit 930 supplies the dummy voltage DV to the data lines DL1 to DLm so as to be synchronized with the gate-on voltage. Therefore, each of the dummy pixel cells 810 connected to the lower dummy gate line GLn + 1 is charged to the dummy voltage DV during the second blanking period BP2. As a result, each data line is precharged to the dummy voltage DV during the second blanking period BP2 of the first subframe 1SF.

Each pixel cell 110 connected to the 3k-2 th gate line GL3k-2 during the first subframe 1SF has a common voltage VcomL in a low state and a red (R +) image signal Vdata having a positive polarity. A red image R having a positive polarity corresponding to the difference voltage of () is displayed.

Similarly to the first subframe 1SF, in the second subframe 2SF, each data line is precharged with the dummy voltage DV during the first blanking period BP1, and then the 3k−1 th gate line during the active period. The negative green (G-) image signal Vdata is supplied to each of the data lines DL1 to DLm so as to be synchronized with the gate-on voltage supplied to the GL3k-1, and each of the second blanking periods BP2 is applied. The data line is precharged to the dummy voltage DV. Each pixel cell 110 connected to the 3k-1 th gate line GL3k-1 during the second subframe 2SF has a common voltage VcomH and a negative green (G-) image signal in a high state. A negative green image G corresponding to the difference voltage of Vdata is displayed.

Like the first subframe 1SF, in the third subframe 3SF, each data line is precharged with the dummy voltage DV during the first blanking period BP1, and then the 3kth gate line GL3k during the active period. In addition, a positive blue (B +) image signal Vdata is supplied to each of the data lines DL1 to DLm so as to be synchronized with the gate-on voltage supplied thereto, and each data line is connected to a dummy voltage during the second blanking period BP2. Precharge with DV). Each pixel cell 110 connected to the 3k th gate line GL3k during the third subframe 3SF has a difference voltage between the common voltage VcomL in the low state and the blue (B +) image signal Vdata of the positive polarity. The blue image B of the positive correspondence is displayed.

Therefore, in the N frame, a color image in which the red, green, and blue images R, G, and B in the first to third subframes 1SF, 2SF, and 3SF are combined is displayed. In other words, in the N frame, a color image is displayed by combining red, green, and blue images R, G, and B displayed in different horizontal lines during the first to third subframes 1SF, 2SF, and 3SF. .

On the other hand, in the N + 1 frame, it is driven in an inverted form to the N frame. That is, each subframe (1SF, 2SF, 3SF) of the N + 1 frame is each subframe (1SF, 2SF, 3SF) of the N frame except that the polarity of the image signal and the logic state of the common voltage are reversed. Is the same as

As described above, the liquid crystal display and the driving method thereof according to the fourth exemplary embodiment of the present invention invert the polarity in units of subframes 1SF, 2SF, and 3SF by precharging each data line by using upper and lower dummy horizontal lines. The charging characteristic of each pixel cell connected to the first and last horizontal lines can be improved.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Will be apparent to those of ordinary skill in the art.

The liquid crystal display device and the driving method thereof according to the embodiment of the present invention provide the following effects.

First, by driving a liquid crystal panel with one driving integrated circuit and incorporating a driving integrated circuit into a liquid crystal panel, the unit cost can be reduced and the thickness of the liquid crystal display device can be minimized.

Second, since each pixel cell is disposed in the horizontal direction, the number of data lines can be reduced to 1/3 so that the pixel cells can be applied to not only a small liquid crystal display but also a medium liquid crystal display.

Third, by dividing one frame into red, green and blue subframes and reversing the polarity of the image signal in each subframe unit, the charging characteristics of the pixel cells can be improved and power consumption can be reduced.

Fourth, by generating the common voltage and the gate driving signal in the boosting circuit, the size of the driving integrated circuit can be reduced and the circuit design can be facilitated.

Fifth, each pixel cell connected to the first and / or horizontal lines according to the polarity inversion of each subframe by precharging each data line with a dummy voltage using the first blanking period and / or the second blanking period of each subframe. Can improve the charging characteristics.

Sixth, the charging characteristic of each pixel cell connected to the first and / or the last horizontal line according to the polarity inversion of the sub-frame unit can be improved by preliminary charging of each data line by using the upper or lower dummy horizontal line.

Claims (31)

A liquid crystal panel in which a plurality of pixel cells displaying a color image by combining monochromatic images displayed on adjacent horizontal lines during the first to third subframes of one frame are formed; A driving integrated circuit mounted on the liquid crystal panel and inverting the polarity of the image signal in units of the sub-frame to supply the pixel cells to the pixel cells; A gate driving circuit connected to a horizontal line of the liquid crystal panel to control the driving integrated circuit to drive the horizontal line; Pixel cells of the same color are repeatedly arranged in the liquid crystal panel along the direction of the gate line corresponding to the horizontal line direction, and pixel cells of three different colors are repeatedly arranged in the direction of the data line crossing the gate line. Become, And the driving integrated circuit supplies a dummy voltage to the data lines every first blanking period, the first half of the subframe, or every second blanking period, the second half of the subframe. delete delete The method of claim 1, And the liquid crystal panel further comprises a dummy horizontal line driven before the first horizontal line is driven. 5. The method of claim 4, And the driving integrated circuit supplies a dummy voltage to each pixel cell of the dummy horizontal line in each of the first blanking periods, which is the first half of the subframe. The method of claim 1, The liquid crystal panel, The upper dummy horizontal line driven before the first horizontal line is driven, And a lower dummy horizontal line driven after the last horizontal line is driven. The method according to claim 6, The drive integrated circuit comprising: A dummy voltage is supplied to each pixel cell of the upper dummy horizontal line in each of the first blanking periods, which is the first half of the subframe, And supplying a dummy voltage to each pixel cell of the lower dummy horizontal line at every second blanking period, which is a second half of the subframe. The method according to any one of claims 1, 5 and 7, The drive integrated circuit comprising: A signal relay unit for relaying the input source data signal and the synchronization signal, A first power generating unit for generating a first power source, A second power generator for generating a second power using the first power source, A common voltage generator for generating a common voltage to be supplied to the common electrode of the liquid crystal panel using the second power source, A signal controller for generating first to third subframe data by color-aligning the source data signal supplied from the signal relay unit and controlling the inside of the driving integrated circuit; A control signal generator for generating a data control signal and a gate driving signal for driving the gate driving circuit using the synchronizing signal supplied through the signal controller; A boosting circuit for boosting the voltage level of the gate driving signal using the second power supply and supplying the voltage to the gate driving circuit; A gradation voltage generator for generating a plurality of gradation voltages using the first power source, And a data converting unit converting the sub frame data into the image signal according to the data control signal using the plurality of gray voltages. 9. The method of claim 8, Wherein the control signal generator comprises: A frequency modulator for modulating the synchronization signal; A data control signal generation unit generating the data control signal using the modulated synchronization signal; And a gate control signal generator configured to generate the gate driving signal using the modulated synchronization signal. 10. The method of claim 9, Wherein the data conversion unit comprises: A shift register for generating a shift signal, A latch unit for latching the subframe data according to the shift signal; A digital-to-analog converter for converting the latched subframe data into positive and negative image signals using the plurality of gray voltages; A buffer unit for buffering the positive and negative image signals; And a selector for selecting the positive or negative image signal and supplying the positive or negative image signal to the data lines according to the data polarity signal inverted in the sub-frame unit. 10. The method of claim 9, And the gate driving circuit sequentially drives only gate lines connected to pixel cells of the same color during each subframe according to the gate driving signal. The method of claim 11, The gate control signal generator generates i (where i is two or more natural numbers) clock signals having a gate start signal and a sequential phase by using the modulated synchronization signal, and modulates the vertical synchronization among the modulated synchronization signals And counting the signals to generate a plurality of subframe signals corresponding to the subframes. 13. The method of claim 12, The gate driving circuit, A selector for selectively outputting the gate start signal according to the plurality of subframe signals; And n stages for sequentially driving only gate lines connected to pixel cells of the same color during each subframe according to the gate start signal and the clock signal output from the selector. Display. 14. The method of claim 13, 3k-2 (where k is a natural number of 1 to n / 3) th stages are sequentially driven during the first subframe, 3k-1th stages are driven sequentially during the second subframe, And 3kth stages are sequentially driven during the third subframe. 10. The method of claim 9, And the booster circuit generates the common voltage according to a data polarity signal inverted in units of subframes so as to control the polarity of the image signal among the data control signals by integrating the common voltage generator. 16. The method of claim 15, The boost circuit, A first level shifter for generating a common voltage in a high state and a common voltage in a low state by using the second power supply; A switching circuit for outputting the common voltage in the high state or the common voltage in the low state according to the data polarity signal; And second to i + 2 level shifters for boosting the voltage level of the gate driving signal by using the second power supply. 10. The method of claim 9, The gate driving circuit drives the dummy gate line of the dummy horizontal line in the first blanking period of each subframe according to the gate driving signal, and then sequentially drives only gate lines connected to pixel cells of the same color. Liquid crystal display device characterized in that. 18. The method of claim 17, The gate control signal generator generates i (where i is two or more natural numbers) clock signals having a gate start signal and a sequential phase by using the modulated synchronization signal, and modulates the vertical synchronization among the modulated synchronization signals And counting the signals to generate a plurality of subframe signals corresponding to the subframes. 19. The method of claim 18, The gate driving circuit, A dummy stage driven according to the gate start signal to supply the clock signal to the dummy gate line; A selection unit for selectively outputting an output signal from the dummy stage according to the plurality of subframe signals; And n stages for sequentially driving only gate lines connected to pixel cells of the same color during each subframe according to the output signal from the selector and the clock signal. 20. The method of claim 19, 3k-2 (where k is a natural number of 1 to n / 3) th stages are sequentially driven during the first subframe, 3k-1th stages are driven sequentially during the second subframe, And 3kth stages are sequentially driven during the third subframe. 10. The method of claim 9, The gate driving circuit drives the upper dummy gate line of the upper dummy horizontal line in the first blanking period of each subframe according to the gate driving signal, and then sequentially only gate lines connected to pixel cells of the same color. And driving a lower dummy gate line of the lower dummy horizontal line in a second blanking period of each subframe. 22. The method of claim 21, The gate control signal generator generates i (where i is two or more natural numbers) clock signals having a gate start signal and a sequential phase by using the modulated synchronization signal, and modulates the vertical synchronization among the modulated synchronization signals And counting the signals to generate a plurality of subframe signals corresponding to the subframes. 23. The method of claim 22, The gate driving circuit, An upper dummy stage supplying the clock signal to the upper dummy gate line according to the gate start signal; A selection unit for selectively outputting an output signal from the dummy stage according to the plurality of subframe signals; N stages for sequentially driving only gate lines connected to pixel cells of the same color during each subframe according to the output signal from the selector and the clock signal; And a lower dummy stage configured to supply the clock signal to the lower dummy gate line in accordance with an output signal from each of the n-th, n-th, and n-th stages. . 24. The method of claim 23, 3k-2 (where k is a natural number of 1 to n / 3) th stages are sequentially driven during the first subframe, 3k-1th stages are driven sequentially during the second subframe, And 3kth stages are sequentially driven during the third subframe. A liquid crystal panel in which pixel cells of the same color are repeatedly arranged along a direction of a gate line corresponding to a horizontal line direction, and three pixel cells of different colors are repeatedly arranged along a direction of a data line crossing the gate line. Include, And dividing one frame into first to third subframes by using one driving integrated circuit mounted on the liquid crystal panel, and displaying a color image by displaying different monochrome images on each subframe. , Monochrome images of adjacent subframes have different polarities, The display of the monochrome image A first step of sequentially driving only gate lines connected to pixel cells of the same color for each subframe by using a gate driving circuit formed in the liquid crystal panel and controlled by the driving integrated circuit; A second step of supplying a monochromatic image signal to the data lines so as to be synchronized with the driving of the gate line from the driving integrated circuit; And the second step further comprises supplying dummy voltages to the data lines before the first horizontal line is driven or after the last horizontal line is driven. delete delete 26. The method of claim 25, And the first step further comprises driving a dummy gate line of the dummy horizontal line formed before the first horizontal line before the first horizontal line is driven. 29. The method of claim 28, And the second step further comprises supplying a dummy voltage to each pixel cell connected to the dummy gate line so as to be synchronized with the driving of the dummy gate line. 26. The method of claim 25, In the first step, Driving the upper dummy gate line of the upper dummy horizontal line formed before the first horizontal line before the first horizontal line is driven; And driving the lower dummy gate line of the lower dummy horizontal line formed after the last horizontal line after the last horizontal line is driven. 31. The method of claim 30, The second step, Supplying a dummy voltage to each pixel cell connected to the upper dummy gate line in synchronization with driving of the upper dummy gate line; And supplying a dummy voltage to each pixel cell connected to the lower dummy gate line so as to be synchronized with driving of the lower dummy gate line.

Images