KR101373500B1 - Liquid crystal panel with a preventing function of static electricity - Google Patents

Abstract

Accordingly, it is an object of the present invention to provide a liquid crystal panel having an antistatic function suitable for efficiently removing static electricity.

An antistatic liquid crystal panel includes: a lower substrate having a pixel array in which a thin film transistor, a pixel electrode, and a common electrode are formed for each pixel; At least one ground pad formed on the lower substrate; An upper substrate having a conductive black matrix having a matrix portion corresponding to the pixel array and an extension portion around the matrix portion; A liquid crystal material filled between the matrix portion and the pixel array; And a conductive contact electrically connecting the at least one ground pad and the extension of the black matrix.

Static electricity, ground wiring, dot contact, board, yield, image quality, liquid crystal, transverse electric field.

Description

Liquid crystal panel with a preventing function of static electricity}

The present invention relates to a liquid crystal panel used as an image display screen, and more particularly to a liquid crystal panel having an antistatic function.

A typical liquid crystal panel (LCD) displays an image corresponding to video information by adjusting the light transmittance of the liquid crystal according to an electric field (that is, the voltage of the pixel driving signal). The liquid crystal panel has a thin thickness and light weight, but can enlarge the screen size beyond the limit. In view of this, the liquid crystal panel is used as a display device of a computer, a display device of a television receiver, a display device of a portable terminal, etc. in place of a cathode ray tube.

Such liquid crystal panels are classified into a longitudinal electric field system and a transverse electric field system according to a method of applying an electric field to the liquid crystal. Conventional liquid crystal panels include liquid crystal panels such as a vertical field alignment mode and a twisted mode. On the other hand, the transverse electric field method includes a liquid crystal panel in an in-plane switch mode.

The liquid crystal panel of the in-plane switch mode has a liquid crystal material layer 30 injected between the lower substrate 10 and the upper substrate 20, as in FIG. 1. The liquid crystal material layer 30 is sealed by a sealant 32 formed between the lower and upper substrates 10 and 20. The lower substrate 10 surface corresponding to the inside of the sealant 32 and the central portions of the lower surface of the upper substrate 20 are used as display areas, while the lower substrate 10 and upper portion corresponding to the outer side of the sealant 32 are used. Edges of the substrate 20 are used as non-display areas.

The display area of the lower substrate 10 is divided into pixel areas by gate lines and data lines (not shown). Each of the pixel regions of the lower substrate 10 includes a thin film transistor 12 for switching a pixel driving signal from a corresponding data line; And a pixel electrode 14 and a common electrode 16 for applying the voltage of the pixel driving signal from the thin film transistor 12 to the liquid crystal material layer 30. Electrostatic mute cells 18 are formed in the non-display area of the lower substrate 10 to prevent static electricity. The electrostatic mute cell 18 bypasses electrostatic charges that can be input to the surface of the lower substrate 10 under electromagnetic influence. For this purpose, the electrostatic mute cell 18 is connected between a data line or a gate line and a ground line.

The upper substrate 20 includes a black matrix 22 that divides the display area of the lower surface into pixel areas in a matrix form. In each of the pixel areas divided by the black matrix 22, a color filter layer 24 including any one of red, green, and blue filters may be formed. In addition, an overcoat layer 26 may be formed on the surfaces of the black matrix 22 and the color filter layer 24.

As such, in order to remove the static charges existing between the lower substrate 10 and the upper substrate 20, the transverse electric field type liquid crystal panel uses the electrostatic mute cell 18 on the lower substrate 10. The electrostatic mute cell 18 on the lower substrate 10 may effectively remove static electricity charged on the surface of the lower substrate 10, but may not remove static electricity charged on the surface of the upper substrate 20. Static electricity charged on the surface of the upper substrate 20 acts as a noise electric field on the liquid crystal material layer 30 to allow a greater or lesser amount of light to be transmitted than an amount corresponding to the voltage of the pixel driving signal. For this reason, the quality of the image displayed on the transverse electric field liquid crystal panel was inevitably deteriorated. In addition, the static electricity charged on the surface of the upper substrate 20 may damage a portion of the thin film transistors 12 on the lower substrate 10 and may cause a failure of the liquid crystal panel. The defect of the liquid crystal panel acts as a factor of lowering the yield of the liquid crystal panel.

Accordingly, it is an object of the present invention to provide a liquid crystal panel having an antistatic function suitable for efficiently removing static electricity.

It is another object of the present invention to provide a liquid crystal panel having an antistatic function suitable for displaying a good quality image.

It is another object of the present invention to provide a liquid crystal panel having an antistatic function suitable for improving production yield.

According to an aspect of an exemplary embodiment, there is provided a liquid crystal panel having an antistatic function, including: a lower substrate having a thin film transistor, a pixel electrode, and a pixel array in which a common electrode is formed for each pixel; At least one ground pad formed on the lower substrate; An upper substrate having a conductive black matrix having a matrix portion corresponding to the pixel array and an extension portion around the matrix portion; A liquid crystal material filled between the matrix portion and the pixel array; And a conductive contact electrically connecting the at least one ground pad and the extension of the black matrix.

Preferably, the conductive contact portion has at least one silver (Ag) dot contact.

The conductive contact portion may be formed in a frame shape on the lower substrate to surround the pixel array.

The antistatic liquid crystal panel includes: a ground wiring formed on the lower substrate to wrap around the pixel array and to be electrically connected to the ground pad; And electrostatic mute cells electrically connected to each of the plurality of gate lines and the plurality of data lines extending from the pixel array and commonly connected to the ground line.

By the above-described configuration, the antistatic function liquid crystal panel according to the present invention can effectively discharge not only static electricity charged on the surface of the lower substrate but also static electricity charged on the surface of the upper substrate. Accordingly, damage to the liquid crystal panel due to static electricity is prevented in the bonding process as well as in the subsequent manufacturing process, and the yield of the liquid crystal panel is increased. In addition, the distortion of the pixel driving signal due to static electricity may be removed to improve the quality of the image displayed on the liquid crystal panel.

In addition to the object of the present invention as described above, other objects, other advantages and other features of the present invention will become apparent from the detailed description of the preferred embodiment with reference to the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the accompanying drawings, components having the same operation and function will be referred to by the same name and the same reference numerals in other drawings.

2 is a cross-sectional view illustrating a cross section of a liquid crystal panel according to an exemplary embodiment of the present invention. Referring to FIG. 2, the liquid crystal panel includes a liquid crystal material layer 300 filled between the lower substrate 100 and the upper substrate 200. The liquid crystal material layer 300 is sealed by a sealing material 310 surrounding the array area AR between the lower substrate 100 and the upper substrate 200. At an outer portion (ie, a peripheral circuit region) of the sealing material 310, at least one dot contact 130 that electrically connects the upper substrate 200 and the lower substrate is disposed. The at least one dot contact 130 is formed of a conductive metal material having a low resistivity in order to increase conductive properties between the upper substrate 200 and the lower substrate 100. Preferably, the dot contact 130 is formed of silver (Ag).

The array area AR of the lower substrate 100 is divided into pixel areas by a gate line (not shown) and a data line (not shown). Each of these pixel regions includes a thin film transistor 110, a pixel electrode 112, and a common electrode 114. The thin film transistor 110 includes a gate insulating layer formed on an entire surface of the lower substrate 100 including a gate electrode, a gate line, and a gate electrode protruding from the gate line. In addition, the thin film transistor 110 may include an active layer formed on the gate insulating layer above the gate electrode, a source electrode derived from the data line and overlapping with a portion of the active layer, and overlapping with another portion of the active layer spaced apart from the source electrode. A drain electrode is provided. In addition, the thin film transistor 110 may further include an ohmic contact layer formed between the active layer, the source electrode, and the drain electrode. The pixel electrode 112 is formed on the passivation layer to be in electrical contact with the drain electrode of the thin film transistor 110. The common electrode 114 is formed on the passivation layer to be electrically connected to the common electrodes on the adjacent pixel region. The pixel electrode 112 and the common electrode 114 may be formed of a transparent conductive metal having excellent light transmittance, such as indium-tin-oxide (hereinafter, referred to as "ITO"). The pixel electrode 112 and the common electrode 114 are arranged on the protective layer alternately with each other. The common electrode 114 may be formed on the same layer as the source electrode, the drain electrode, and the data line (ie, on the gate insulating layer) or on the same layer as the gate line and the gate electrode (ie, below the gate insulating layer). It may be. When formed on the same layer as the data line or the gate line, the common electrode 114 is formed of the same conductive material as the data line or the gate line.

The lower substrate 100 includes a ground line CML and an electrostatic mute cell 120 formed in the peripheral circuit region PCR. The electrostatic mute cell 120 is electrically connected to the gate line or data line and the ground line CML extending from the array area AR to discharge static electricity on the gate line or the data line toward the ground line CML. The ground line CML is also formed to be electrically connected to the ground pad PDM on the pad area PDR of the lower substrate 100 so that the static electricity from the electrostatic mute cell 120 is directed toward an external ground source (not shown). To be discharged. The ground line CML D is formed in the form of a closed loop to surround the array area AR. A part of the ground line CML is formed simultaneously with the gate line and the gate electrode, and the rest of the ground line CML is formed simultaneously with the data line and the source and drain electrodes. The electrostatic mute cell 120 is formed simultaneously with the thin film transistor.

The pads on the pad region PDR of the lower substrate 100 may also include some pads formed simultaneously with the gate line and the gate electrode and remaining pads formed simultaneously with the data line, source, and drain electrodes. Some pads include ground pads and gate pads, and others include ground pads and data pads.

At least one conductive dot contact 130 is formed in the lower substrate 100 to be in electrical contact with at least one edge of the ground line CML. The at least one dot contact 130 is electrically connected to the ground pad PDM via the ground line CML. Instead of the at least one conductive dot contact 130, a conductive contact having a frame shape along the ground line CML may be formed on the lower substrate 100. The conductive contact is also electrically connected to the ground pads PDM1 to PDM4 via the ground wiring CML.

The upper substrate 200 has a black matrix formed in all regions including the array region AR and the peripheral circuit region PCR. The black matrix has a matrix portion 210A positioned on the array region AR and an extension portion 210B positioned in the peripheral circuit region PCR. The matrix unit 210A divides the array region AR of the upper substrate 200 into unit regions (ie, pixel regions). The expansion unit 210B may include a ground line CML on the peripheral circuit region PCR of the lower substrate 100 through at least one dot contact 130 positioned between the upper substrate 200 and the lower substrate 100. Is electrically connected to the The black matrix is a static electricity that can be generated between the upper substrate 200 and the liquid crystal material layer 300, including the contact contact 130, the ground wiring (CML) and the ground pad (PDM) on the lower substrate 100 Discharge through to the external ground source. To this end, the black matrix 210 is formed of a metal material such as chromium (Cr).

In addition, the lower substrate 200 may further include a color filter 220 corresponding to unit regions (pixel regions) separated by the matrix portion 210A of the black matrix 210. This color filter allows only light of a unique color to be transmitted. In addition to this inherent function, the color filter 220 may have static electricity generated between the upper substrate 200 and the liquid crystal material layer 300 by itself and the black matrix 210, the dot contact 130, and the lower substrate ( It may be efficiently discharged toward the external ground source via the ground wiring (CML) and the ground pad (PDM) on the 100. To this end, the color filter 220 will be formed of a conductive material capable of transmitting light. In addition, the upper substrate 200 may further include an overcoat layer 230 formed on the matrix portion 210A of the black matrix 210 and the color filter 220. The overcoat layer 230 removes a step between the matrix portion 210A of the black matrix 210 and the color filter 220 so that the upper substrate 200 has a flat surface. The overcoat layer 230 is a ground wire on the self and the black matrix 210, the dot contact 130, and the lower substrate 100, which may be generated between the upper substrate 200 and the liquid crystal material layer 300. It can also be efficiently discharged to an external ground source via the CML and ground pad (PDM). To this end, the overcoat layer 230 may be formed of a conductive material capable of transmitting light.

The sealing material 310 is formed on the upper substrate 200 or the lower substrate 100 to have a rim shape along the boundary between the array region AR and the peripheral circuit region PCR. In other words, the sealing material 310 in the form of a frame is positioned inward of the at least one dot contact 130. After the lower substrate 100 and the upper substrate 200 are bonded together, the liquid crystal material 300 is injected into the inner space of the high water material 310.

3 is a plan view illustrating the layout of the liquid crystal panel of FIG. 2 in detail, and FIG. 4 is a plan view illustrating the layout of the upper substrate 200 of the liquid crystal panel of FIG. 2 in detail. 3 and 4, the antistatic liquid crystal panel includes a lower substrate 100 and an upper substrate 200 facing each other. The central portions of the lower substrate 100 and the upper substrate 200 are allocated to the array region AR used for displaying an image, and the periphery of the array region AR (that is, the edge of the upper substrate 200) is a peripheral circuit. It is assigned to the area PCR. In addition, the lower substrate 100 has a pad region PDR extending outward and to the left of the upper substrate 200.

The array area AR on the lower substrate 100 is divided into a plurality of pixel areas by a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm. The thin film transistor 110, the pixel electrodes 1112, and the common electrodes 114 are formed in each pixel area of the lower substrate 100. The pixel electrodes 112 are all electrically connected to the drain electrode of the thin film transistor 110. The source electrode of the thin film transistor 110 is connected to the corresponding data line DL and the gate electrode of the thin film transistor 110 is connected to the corresponding gate line GL.

The ground line CML and the electrostatic mute cells 120 are formed in the peripheral circuit region PCR of the lower substrate 100. Among the static mute cells 120, some of the static mute cells 120 connected between the corresponding gate line GL and the ground line CML are connected to the ground lines CML on the corresponding gate lines GL1 to GLn. ) And the remaining electrostatic mute cells 120 connected between the corresponding data line DL and the ground line CML discharge the static electricity on the corresponding data line DL toward the ground line CML. To this end, one terminal of the electrostatic mute cells 120 is connected to either one of both ends of each of the gate lines GL1 to GLn and both ends of each of the data lines DL1 to DLm, and the electrostatic mute cells 120 The other terminals are all commonly connected to the ground wiring CML. The ground line CML is formed in the form of a closed loop surrounding the array area AR of the lower substrate 100. Some of the ground wiring CML (a ground wiring portion crossing the data line) is formed of the same material as the gate wiring GL, and the remaining portion of the ground wiring CML (the ground wiring portion crossing the gate lines) is formed. It is formed of the same material as the data line DL. Accordingly, a portion of the ground line CML crossing the gate lines GL is formed at the same time as the data lines DL, while the remaining portion of the ground line CML crossing the data lines DL is formed. It is formed simultaneously with the gate lines GL. In addition, the ground line on the peripheral circuit region PCR of the lower substrate 100 is electrically connected to at least two ground pads PDM1 to PDM4 on the adjacent pad region PAR. Further, the ground wiring CML on the peripheral circuit region PCR of the lower substrate 100 may extend through the dot contact 130 to the black matrix 210 on the upper substrate 200, in particular, the black matrix 210. It is also electrically connected to the part 210A.

Gate pads PDG1 to PDGn, data pads PDD1 to PDDm, and at least one ground pads PDM1 to PDM4 are arranged in the pad region PDR of the lower substrate 100. The gate pads PDG1 to PDGn are electrically connected to the gate lines GL1 to GLn on the array region AR, and the data pads PDD1 to PDDm are also data lines on the array region AR. It is electrically connected corresponding to (DL1 ~ DLm). At least one ground pad PDM1-PDM4 is electrically common-connected to the ground wiring CML on the peripheral circuit region PCR. In addition to the gate pads PDG1 to PDGn, the data pads PDD1 to PDDm, and at least one or more ground pads PDM1 to PDM4, the pad region PDR of the lower substrate 100 may be provided with a supply voltage, a reference voltage, and a timing signal. Pads (not shown) for delivery are provided. At least one ground pad PDM1 to PDM4 is connected to a ground voltage source installed outside of the liquid crystal panel to form a discharge path of static electricity from the ground wiring CML on the peripheral circuit region PCR to an external ground voltage source. Let's do it.

The black matrix 210 is formed on the upper substrate 200. The black matrix 210 includes a matrix portion 210A positioned on the array region AR and an extension portion 210B formed on the peripheral circuit region PCR. The matrix portion 210A of the black matrix 210 divides the array region AR of the upper substrate 200 into pixel regions. The extension 210B of the black matrix 210 is formed on the front surface of the peripheral circuit region PCR. This black matrix 210 prevents optical interference between the pixels. In addition, the black matrix 210 has a function of discharging static electricity that may be generated between the upper substrate 200 and the liquid crystal material layer 300. To this end, the black matrix 210 including the matrix portion 210A and the extension portion 210B is formed of a conductive material such as chromium (Cr) and at least one dot contact 130 to form the lower substrate 100. It is also electrically connected to the ground wiring CML on the peripheral circuit region PCR of the. The at least one dot contact 130 allows the extension 210A of the black matrix 210 to be electrically connected to the ground line CML on the peripheral circuit region PCR of the lower substrate 100.

The at least one dot contact 130 is formed such that at least one edge of the ground line CML and one side (that is, the bottom) are in electrical contact with each other. The other side (top) of the at least one dot contact 130 is in electrical contact with at least one edge of the extension 210B of the black matrix 210 when the lower substrate 100 and the upper substrate 200 are bonded together. . In other words, the at least one dot contact 130 electrically connects the extension 210B of the black matrix 210 to the ground pad PDM. By the at least one dot contact 130, the static electricity charged on the surface of the upper substrate 200 is transferred to the matrix portion 210A and the extension portion 210B of the black matrix 210, the dot contact 130, and the ground wiring. It is discharged to the ground source via the CML and the ground pads PDM1 to PDM4. In other words, the liquid crystal panel having the antistatic function may discharge static electricity charged on the surface of the lower substrate 100 as well as static electricity charged on the surface of the upper substrate 200. Accordingly, damage to the liquid crystal panel due to static electricity is prevented in the bonding process as well as in the subsequent manufacturing process, and the yield of the liquid crystal panel is increased. In addition, the distortion of the pixel driving signal due to static electricity may be removed to improve the quality of the image displayed on the liquid crystal panel.

5 is a plan view illustrating a layout of a liquid crystal panel having an antistatic function according to another exemplary embodiment of the present invention. The liquid crystal panel of FIG. 5 has the same configuration as the liquid crystal panel of FIG. 3 except that at least one dot contact 130 is replaced by the conductive contact portion 130A. Components of FIG. 5 having the same functions, operations, and names as those shown in FIG. 3 will be referred to by the same reference numerals as in FIG. 3. Also, the detailed description of the components of FIG. 5 that are identical to those of FIG. 3 will be omitted, as is already apparent from FIG. 3.

The conductive contact portion 130A is formed on the lower substrate 100 to have the shape of a frame along the ground line CML. The conductive contact portion 130A having such a frame shape is directly contacted with the ground wire CML to be electrically connected to the at least one ground pad PDM1 to PDM4 via the ground wire CML. In addition, when the lower substrate 100 and the upper substrate 200 are bonded to each other, the conductive contact portion 130A may be in direct contact with the extension 210A of the black matrix 210 on the upper substrate 200 so as to contact the black matrix 210. Is electrically connected to a ground pad (PDM). By the conductive contact 130A, the static electricity charged on the surface of the upper substrate 200 is transferred to the matrix portion 210A and the extension portion 210B of the black matrix 210, the conductive contact portion 130A, and the ground wiring (CML). And discharge to the ground source via the ground pads PDM1 to PDM4. In other words, the liquid crystal panel having the antistatic function may discharge static electricity charged on the surface of the lower substrate 100 as well as static electricity charged on the surface of the upper substrate 200. Accordingly, damage to the liquid crystal panel due to static electricity is prevented in the bonding process as well as in the subsequent manufacturing process, and the yield of the liquid crystal panel is increased. In addition, the distortion of the pixel driving signal due to static electricity may be removed to improve the quality of the image displayed on the liquid crystal panel.

As described above, the present invention has been limited to the embodiments shown in the accompanying drawings, but these are merely exemplary, and those skilled in the art to which the present invention pertains may have the technical idea and It will be apparent that various modifications, changes and equivalent other embodiments are possible without departing from the scope.

For example, the liquid crystal panel of FIGS. 3 and 5 is common to the common electrode 114 in addition to the electrostatic mute cell 120 connected between the gate line GL or the data line DL and the ground wiring CML. At least one antistatic cell connected between the common voltage line extending from the array region AR and the ground line CML may be further provided to supply a voltage Vcom. The electrostatic mute cell connected to the common voltage line discharges the static electricity charged on the common voltage line to an external ground source via the ground line CML and the ground pad PDM.

In addition, the liquid crystal panel of FIGS. 3 and 5 may include a storage capacitor (not shown) having one terminal connected to the thin film transistor 110 together with the pixel electrode 112. In this case, the liquid crystal panel of FIGS. 3 and 5 is disposed between the storage wiring (not shown) and the ground wiring CML extending from the array region AR in order to connect the other terminal of the storage capacitor to a power source having a constant potential. It will also have at least one electrostatic mute cell connected. The at least one electrostatic mute cell may discharge static electricity charged on the storage wiring to an external ground source via the ground wiring CML and the ground pad PDM.

Therefore, the spirit and scope of the present invention to be protected will be defined by the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS For a better understanding of the drawings used in the detailed description of the present invention, a brief description of each drawing is provided.

1 is a cross-sectional view illustrating the structure of a conventional sulfur field type liquid crystal panel.

2 is a cross-sectional view illustrating a structure of a liquid crystal panel having an antistatic function according to an exemplary embodiment of the present invention.

3 is a plan view illustrating a layout of the liquid crystal panel illustrated in FIG. 2.

4 is a plan view illustrating a layout of an upper substrate of the liquid crystal panel of FIG. 3.

5 is a plan view illustrating a layout of a liquid crystal panel having an antistatic function according to another exemplary embodiment of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS to the main parts of the drawings "

10,100: lower substrate 12,110: thin film transistor

14,112: pixel electrode 16,114: common electrode

18,120: electrostatic mute cell 20,200: upper substrate

22,210: Black Matrix 24,220: Color Filter

26,240: overcoat layer 30,300: liquid crystal material layer

32,310: sealing material 130: dot contact

130A: conductive contact portion 210A: matrix portion

210B: Extension

Claims (9)

A lower substrate having a pixel array in which a thin film transistor, a pixel electrode, and a common electrode are formed for each pixel; At least one ground pad formed on the lower substrate; An upper substrate having a conductive black matrix having a matrix portion corresponding to the pixel array and an extension portion around the matrix portion; A liquid crystal material filled between the matrix portion and the pixel array; A conductive contact electrically connecting the at least one ground pad to an extension of the black matrix; A ground line formed on the lower substrate to wrap around the pixel array and to be electrically connected to the ground pad; And And at least one first electrostatic mute cell electrically connected to each of the plurality of gate lines and the plurality of data lines extending from the pixel array and commonly connected to the ground line. panel. The method of claim 1, And the conductive contact portion comprises at least one silver dot contact. The method of claim 1, And an electroconductive contact portion formed in a rim on the lower substrate to surround the pixel array. delete The method of claim 1, And a color filter formed in each of the regions separated by the matrix portion of the black matrix. 6. The method of claim 5, And the color filter is formed of a conductive material. 6. The method of claim 5, And an overcoat layer formed to cover the color filters and the matrix portion. The method of claim 7, wherein And the overcoat layer is formed of a conductive material capable of transmitting light. The method of claim 1, The pixel array further includes a plurality of common voltage wirings and storage wirings, And at least one second electrostatic mute cell connected to at least one of the common voltage line and the storage line extending from the pixel array and connected to the ground line.

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