KR101366024B1 - Circuit for common votage of LCD and driving method - Google Patents

Abstract

The present invention relates to a liquid crystal display device, and more particularly, to a common voltage circuit of a liquid crystal display device and a method of driving the same, which improves a defect caused by a change in an optimum common voltage initially set using a programmable IC after a predetermined time elapses. will be.

According to the present invention, in determining the optimum common voltage, offset data, which is an amount of change in the optimum common voltage that changes with time, is stored in the common voltage circuit, and in actual driving, the offset data is added to the optimum common voltage. The common voltage is generated in consideration of the change of the optimum common voltage.

Accordingly, the process time required to adjust the offset data can be reduced during the process, thereby preventing the occurrence of defects.

Common Voltage (Vcom), Flicker, Programmable IC

Description

Common voltage circuit of LCD and its driving method {Circuit for common votage of LCD and driving method}

1 is a block diagram schematically illustrating a configuration of a general liquid crystal display device.

2 is a block diagram showing the structure of a conventional common voltage circuit.

3 is a graph schematically illustrating a change in the optimum common voltage over time.

4 is a block diagram schematically illustrating a structure of a common voltage circuit of a liquid crystal display according to an exemplary embodiment of the present invention.

5 is a flowchart illustrating a method of driving a common voltage circuit of a liquid crystal display according to an exemplary embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

171: n-bit register section 172: control section

173: n-bit memory unit 174: offset control unit

175: adder 177: decoder unit

178: switching unit SDA: data

SCL: clock offset_s: offset active signal

R1 to Rm: resistance elements VH, VL: first and second voltages

The present invention relates to a liquid crystal display device, and more particularly, to a common voltage circuit of a liquid crystal display device and a method of driving the same, which improves a defect caused by a change in an optimum common voltage initially set using a programmable IC after a predetermined time elapses. will be.

Liquid crystal displays have low power consumption and are capable of thinning and realizing large screens. Therefore, LCDs are in the spotlight as next-generation advanced display devices with high added value as display devices such as notebook computers and large screen TVs.

In the field of liquid crystal display devices, active matrix liquid crystal displays (AMLCDs) are mainstream. In this AMLCD, one thin film transistor (TFT) corresponds to one pixel, and one TFT controls the voltage level of the pixel as a switching element to change the light transmittance of the pixel to display an image.

FIG. 1 is a block diagram schematically illustrating a configuration of a general liquid crystal display, and a thin film transistor T is provided in a matrix form at a point where a plurality of gate lines GL and data lines DL intersect to display an image. A liquid crystal panel 10, a gate driver 30 for supplying a gate signal to the liquid crystal panel 10, a data driver 50 for supplying a data signal, and a control signal and a data signal from an external source. A gamma circuit configured to control the gate driver 30 and the data driver 50 in response to the signals, and to supply a gamma voltage that is a reference voltage to the data driver 50 ( 60 and a common voltage circuit 70 for supplying a common voltage Vcom to the liquid crystal panel 10.

In particular, the liquid crystal panel 10 of the TN mode has a form in which the first and second substrates are bonded to each other with a liquid crystal layer interposed therebetween, and according to the magnitude of the electric field formed by the voltage difference between the two substrates, It is a structure for displaying an image by controlling, and in detail, a gray voltage corresponding to an image signal is applied to one of the two substrates, and a common voltage Vcom is applied to the other substrate to form an electric field by the voltage difference between the two signals. The light transmittance of the liquid crystal is controlled.

In addition, even in the case of the liquid crystal panel 100 of the IPS mode in which both the image signal and the common voltage Vcom are applied to one substrate, the driving principle is the same.

Hereinafter, driving of a general liquid crystal display device will be described.

First, when a control signal is supplied from the outside to the timing controller 20, the timing controller 20 corresponds to a gate control signal for driving the gate driver 30 and data control for driving the data driver 50. A signal is generated and supplied to each driving circuit, and a data signal is supplied from the outside to rearrange the data signal and supply the data signal to the data driver 50.

The gate driver 30 supplied with the gate control signal sequentially supplies a gate driving signal to the liquid crystal panel 10 one horizontal line for one frame through each gate line GL.

The data driver 50 supplied with the data control signal converts the digital data signal into an analog video signal corresponding to the gamma voltage, and converts the video signal of one horizontal line through all the data lines DL. At the same time, the liquid crystal panel 10 is supplied.

In addition, the common voltage circuit 70 generates a common voltage Vcom and supplies it to the common electrode of the liquid crystal panel 1.

Accordingly, the liquid crystal panel 10 displays the image gray level by the voltage difference between the image signal supplied from the data driver 50 and the common voltage Vcom. Therefore, the image quality is greatly influenced by the common voltage Vcom value.

2 is a block diagram illustrating a structure of a conventional common voltage circuit. As illustrated, the conventional common voltage circuit 70 includes an n-bit register unit for receiving data SDA and a clock SCL from the outside. 71, an n-bit memory unit 73 for storing the input data, a control unit 72 for controlling the n-bit memory unit 73, and two inputs from the n-bit register unit 71 A decoder 77 for converting the true data into one selection signal, a switching unit 78 for outputting one of m-level voltages to the common voltage Vcom according to the selection of the decoder 77; The plurality of resistors R1 to Rm divide the input first and second voltages VH and VL.

The setter supplies a predetermined test image signal to the liquid crystal panel to display a predetermined image, and then inputs an appropriate temporary common voltage to the common voltage circuit 70 to inspect the image, thereby minimizing flicker. Find the optimum common voltage (FVcom).

However, the optimum common voltage FVcom, which is initially set through this process, has a characteristic that its value changes when the liquid crystal panel passes a predetermined time. That is, the liquid crystal panel during the initial driving is in an unstable state, and some time is required to be stabilized.

3 is a graph schematically illustrating a change in the optimum common voltage over time.

As shown, the optimum common voltage (FVcom) during the initial operation is about 6.75V, but gradually decreases with time, and after 10 minutes or more, the optimum common voltage (FVcom) decreases to about 6.52V. . The difference between the optimum common voltage FVcom during the initial driving and the optimum common voltage FVcom decreased after a predetermined time is called an offset k. Referring to the drawings, the offset k becomes approximately 0.23V.

Such a difference is a voltage difference corresponding to 10 or more gradations in the liquid crystal display device expressing 128 gradations, which may cause a defect of the liquid crystal panel due to the accumulation of DC voltage.

Accordingly, conventionally, thermistors are used to control the common voltage Vcom to be lowered, or to adjust the optimum common voltage FVcom in the process and then lower the voltage to an arbitrary voltage level. However, this method has a problem that causes a failure due to process time extension and adjustment error.

The present invention has been made to solve the above problems, the present invention provides a common voltage circuit of the liquid crystal display device that solves the problems caused by the phenomenon that the voltage level is lowered as the optimum common voltage over a predetermined time. Its purpose is to.

In order to realize the above object, the common voltage circuit of the liquid crystal display device according to the embodiment of the present invention is a common voltage circuit for supplying a common voltage to the liquid crystal display device. A bit memory section; A control unit controlling data input / output of the n-bit memory unit; An offset control unit for storing offset data; An adder that adds the data and the offset data and transfers the result to the n-bit register; An n-bit register unit for temporarily storing the calculated data; A decoder for decoding the temporarily stored data and outputting a selection signal; A resistance element receiving the first and second voltages and dividing the voltage into a plurality of voltage levels; And a switching unit for selecting one of the plurality of voltage levels in response to the selection signal.

The n-bit is 7-bit, and the liquid crystal display is characterized in that it implements 128 gradations.

The offset data is characterized in that the signal having a voltage level of 0 to 31 steps.

The offset control unit is characterized in that the built-in 5-bit memory.

The n-bit register unit, the control unit, and the offset control unit may be connected to the outside in an I 2 C scheme.

The offset control unit receives an offset activation signal from the outside, and outputs the offset data to the adder when the offset activation signal is at a low level, and when the offset activation signal is at a high level, The offset data is not output to the adder.

In order to achieve the above object, a method of driving a common voltage circuit of a liquid crystal display device according to an embodiment of the present invention is a common voltage circuit for supplying a common voltage to a liquid crystal display device, the n-bit memory unit and the n- A control unit for controlling data input / output of the bit memory unit, an offset control unit for storing offset data, an adder, an n-bit register unit for temporarily storing data, a decoder unit, and a plurality of first and second voltages A common voltage circuit for supplying a common voltage to a liquid crystal display device, comprising: a resistance element for dividing at a voltage level of? And a switching unit, the method comprising: determining an optimum common voltage and the offset data; Storing and outputting the offset data to the offset control unit; Storing the optimum common voltage in the n-bit memory unit; Adding the optimum common voltage and the offset data; And outputting the optimum common voltage.

The storing and outputting of the offset data to the offset control unit may include: applying a high level offset activation signal to the offset control unit; Storing the offset data in the offset control unit; Applying a low level offset activation signal to the offset control unit; And outputting the offset data to the offset control unit.

The adding of the optimum common voltage and the offset data may include: inputting an optimum common voltage stored in the memory unit into the adder; And inputting the offset data stored in the offset control unit to the adder.

The outputting of the optimum common voltage may include transferring data temporarily stored in the n-bit register to the decoder; And outputting, by the decoder, a voltage divided by the resistance element through the switching element in response to the temporarily stored data.

The n-bit is 7-bit, and the liquid crystal display is characterized in that it implements 128 gradations.

The offset data is characterized in that the signal having a voltage level of 0 to 31 steps.

The offset control unit is characterized in that the built-in 5-bit memory.

The n-bit register unit, the control unit, and the offset control unit may be connected to the outside in an I 2 C scheme.

Hereinafter, a common voltage circuit of a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

In the following description, only a common voltage circuit for generating and optimizing a common voltage, which is an important feature of the present invention, will be described for convenience. The other driving circuits have the same configuration as the driving circuits of the general liquid crystal display device and perform the same operation.

4 is a block diagram schematically illustrating a structure of a common voltage circuit of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown, the common voltage circuit 170 of the liquid crystal display according to the embodiment of the present invention receives data and a clock through two signal lines, SCL (Serial Clock) and SDA (Serial Data) from the outside. an n-bit register section 171, an n-bit memory section 173 for storing the input data, a control section 172 for controlling the n-bit memory section 173, and the data, clock and offset activity An offset control unit 174 for receiving and temporarily storing a signal offset_s, an adder 175 for adding and calculating the offset active signal offset_s and data stored in the n-bit memory unit 172, and n A decoder 177 for converting binary data input from the bit register unit 171 into a single selection signal and one of m-level voltages according to the selection of the decoder 177 is selected as a common voltage. Vcom) and the switching unit 178 and the input first and second voltages (VH, VL) It includes a plurality of resistance elements (R1 to Rm) to be divided.

In addition, the SCL signal line SCL and the SDA signal line SDA which transfer the data and the clock are connected to the n-bit register unit 171, the control unit 172, and the offset control unit 174. .

More specifically, the n-bit register unit 171 temporarily stores the data input in the n-bit serial form until the transfer to the decoder unit 177 is completed.

The controller 172 stores data input in the form of n bits in the n-bit memory unit 173 and controls data input / output of the n-bit memory unit 173.

The n-bit memory unit 173 updates or transmits the stored data to the n-bit register unit 171 under the control of the controller 172.

The offset control unit 174 stores the offset data offset_d in the range set by the setter, and transmits the offset data offset_d through the adder 175 in response to the offset activation signal offset_s to the n-bit memory unit 173. And adds the result to the n-bit register unit 171.

Here, the offset data offset_d is a common voltage compensation signal in a predetermined range arbitrarily set by the setter, that is, the initial optimum common voltage FVcom determined by the experimental value and the common voltage Vcom value in the stabilized liquid crystal panel. The signal corresponding to the difference.

The size of the offset data offset_d is preferably a signal having a voltage level of 32 steps in a liquid crystal display device expressing 128 gray levels. Accordingly, the offset control unit 174 preferably includes a 5-bit memory. .

In addition, the offset activation signal offset_s is a signal for determining whether the offset data and the data stored in the n-bit memory unit 173 are added or not, and the offset control unit 174 may include an offset activation signal offset_s. In the low level, the prestored offset data is output to the adder 175. In the low level, the prestored offset data is not output to the adder 175.

The adder 175 performs a calculation operation on the data stored in the n-bit memory unit 173 and the offset data.

The decoder 177 receives the data temporarily stored in the n-bit register 171 and controls the switching unit 178 correspondingly.

Although not shown, the switching unit 178 includes a plurality of switching elements (not shown) corresponding to the output of the decoder unit 177 one-to-one, and are controlled by the decoder unit 177 and include resistors R1 to Rm. The voltage divided by is output as a common voltage Vcom.

 In this operation, since the data transmitted from the n-bit register unit 171 is a digital signal, it is decoded to turn on one of the switching elements (not shown) of the switching unit 178 and connected thereto. The voltage divided by the resistors R1 to Rm is output as a common voltage Vcom.

The resistors R1 to Rm divide the first and second voltages VH and VL supplied from the outside to a plurality of levels by m + 1.

The common voltage circuit 170 according to the embodiment of the present invention having such a structure is connected to an external data input means (not shown) in an I 2 C manner. In this case, the I2C method is a serial interface method that transmits information between devices by two signal lines SCL and SDA. The I2C method can change a function by software without changing hardware, and supports many-to-many communication function instead of one-to-one communication.

The reason for connecting the common voltage circuit 170 and the external data input means (not shown) by the above-described I2C method is that it is strong in noise, has high reliability, low power consumption, operates well in various temperature environments, and various voltages. This is because there is an advantage in supporting the level.

Here, the number of bits n of the n-bit register unit 171 and the n-bit memory unit 173 is the number of bits when generating the common voltage Vcom having a voltage level of 0 to 127. n) becomes 7 (n = 7).

In the following description, a method of setting the optimum common voltage using the common voltage circuit of the liquid crystal display according to the exemplary embodiment of the present invention as an example in which the number of bits n is 7 will be described with reference to FIG. 5.

5 is a flowchart illustrating a method of driving a common voltage circuit of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown, in step S1, the setter inputs an arbitrary voltage level to be tested through the data signal line SDA and the clock signal line SCL to determine the optimum common voltage FVcom and the offset data offset_d. Step.

In step S2, the offset activation signal offset_s is applied at a high level, and the offset control unit 174 is applied to the offset data offset_d determined by a test through the SCL signal line SCL and the SDA signal line SDA. ) Step.

In step S3, the optimum common voltage FVcom is input through the SCL signal line SCL and the SDA signal line SDA. At this time, since the offset activation signal Offset_s is high, the offset data Offset_d stored in the offset control unit 174 is not transmitted to the adder 173, thereby affecting the optimum common voltage FVcom. Do not.

In step S4, after the process of setting the optimum common voltage FVcom is completed, the offset activation signal offset_s is maintained at a low level. Accordingly, the offset data offset_d stored in the offset controller 174 is input to the adder 173 and added to the initial optimum common voltage FVcom.

In step S5, the offset data offset_d is added to the optimum common voltage FVcom and finally output as the common voltage Vcom.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It can be understood that

Therefore, the common voltage circuit of the liquid crystal display device and the driving method thereof according to the embodiment of the present invention store offset data which is a change amount of the optimum common voltage which changes with time in the common voltage circuit when the optimum common voltage is determined. In actual driving, the offset data is added to the optimum common voltage to generate a common voltage in consideration of the change of the optimum common voltage.

Accordingly, the process time required to adjust the offset data can be reduced during the process, thereby preventing the occurrence of defects.

Claims (14)

In a common voltage circuit for supplying a common voltage to a liquid crystal display device, an n-bit memory unit for storing data input in an n-bit serial form; A control unit controlling data input / output of the n-bit memory unit; An offset control unit for storing offset data; An adder that adds the data and the offset data and transfers the result to the n-bit register; An n-bit register unit for temporarily storing the calculated data; A decoder for decoding the temporarily stored data and outputting a selection signal; A resistance element receiving the first and second voltages and dividing the voltage into a plurality of voltage levels; A switching unit for selecting one of the plurality of voltage levels in response to the selection signal Common voltage circuit of the liquid crystal display device comprising a. The method of claim 1, Wherein the n-bit is 7-bit, and the liquid crystal display implements 128 gradations. The method of claim 2, And the offset data is a signal having a voltage level of 0 to 31 steps. The method of claim 3, wherein The offset control unit is a common voltage circuit of the liquid crystal display, characterized in that the built-in 5-bit memory. The method of claim 1, And the n-bit register unit, the control unit, and the offset control unit are connected to an external device in an I2C manner. The method of claim 1, The offset control unit receives an offset activation signal from the outside, and outputs the offset data to the adder when the offset activation signal is at a low level, and when the offset activation signal is at a high level, And the offset data is not output to the adder. A common voltage circuit for supplying a common voltage to a liquid crystal display device, comprising: an n-bit memory unit, a control unit for controlling data input / output of the n-bit memory unit, an offset control unit for storing offset data, an adder, and data And a n-bit register section for temporarily storing the data, a decoder section, a resistor element for receiving the first and second voltages and dividing the voltage into a plurality of voltage levels, and a switching section. In a method of driving a common voltage circuit for supplying a liquid crystal display device, Determining an optimum common voltage and the offset data; Storing and outputting the offset data to the offset control unit; Storing the optimum common voltage in the n-bit memory unit; Adding the optimum common voltage and the offset data; Outputting the optimum common voltage Method of driving a common voltage circuit of a liquid crystal display device comprising a. The method of claim 7, wherein Storing and outputting the offset data to the offset control unit; Applying a high level offset activation signal to the offset control unit; Storing the offset data in the offset control unit; Applying a low level offset activation signal to the offset control unit; Outputting the offset data to the offset control unit. Method of driving a common voltage circuit of a liquid crystal display device comprising a. The method of claim 7, wherein The adding of the optimum common voltage and the offset data, Inputting an optimum common voltage stored in the memory unit into the adder; Inputting the offset data stored in the offset control unit to the adder Method of driving a common voltage circuit of a liquid crystal display device comprising a. The method of claim 7, wherein The step of outputting the optimum common voltage, Passing data temporarily stored in the n-bit register to the decoder; Outputting, by the decoder, a voltage divided from the resistor through the switching device of the switching unit in response to the temporarily stored data; Method of driving a common voltage circuit of a liquid crystal display device comprising a. Claim 11 was abandoned when the registration fee was paid. The method of claim 7, wherein And the n-bit is 7-bit, and the liquid crystal display implements 128 gray levels. Claim 12 is abandoned in setting registration fee. The method of claim 7, wherein And the offset data is a signal having a voltage level of 0 to 31 steps. Claim 13 has been abandoned due to the set registration fee. The method of claim 7, wherein And the offset control unit includes a 5-bit memory. Claim 14 has been abandoned due to the setting registration fee. And the n-bit register unit, the control unit, and the offset control unit are connected to an external device in an I2C manner.

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