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KR101363992B1 - Stacked semiconductor package and fabrication method of the same - Google Patents

Stacked semiconductor package and fabrication method of the same Download PDF

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KR101363992B1
KR101363992B1 KR1020120049640A KR20120049640A KR101363992B1 KR 101363992 B1 KR101363992 B1 KR 101363992B1 KR 1020120049640 A KR1020120049640 A KR 1020120049640A KR 20120049640 A KR20120049640 A KR 20120049640A KR 101363992 B1 KR101363992 B1 KR 101363992B1
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semiconductor package
solder ball
groove
substrate
mold part
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KR20130125965A (en
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김동규
김윤식
하상옥
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(주)윈팩
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

적층 반도체 패키지 및 그 제조방법이 개시되어 있다. 개시된 적층 반도체 패키지는 상면에 제1 볼랜드가 형성된 제1 기판, 상기 제1 볼랜드 상에 장착된 제1 솔더볼 및 상기 제1 기판의 상면을 밀봉하고 상기 제1 솔더볼을 노출하는 홈을 구비하는 제1 몰드부를 포함하는 하부 반도체 패키지;및 하단부에 제2 솔더볼을 구비하며, 상기 제2 솔더볼이 상기 홈에 결합되고 상기 홈 하부의 상기 제1 솔더볼과 접합되도록 상기 하부 반도체 패키지 상에 적층된 상부 반도체 패키지를 포함한다. A multilayer semiconductor package and a method of manufacturing the same are disclosed. The disclosed stacked semiconductor package includes a first substrate having a first borland formed thereon, a first solder ball mounted on the first borland, and a groove sealing an upper surface of the first substrate and exposing the first solder ball. An upper semiconductor package including a lower semiconductor package including a mold part, and a second solder ball at a lower end thereof, wherein the second solder ball is coupled to the groove and bonded to the first solder ball under the groove; It includes.

Description

적층 반도체 패키지 및 그 제조방법{STACKED SEMICONDUCTOR PACKAGE AND FABRICATION METHOD OF THE SAME}Multilayer semiconductor package and its manufacturing method {STACKED SEMICONDUCTOR PACKAGE AND FABRICATION METHOD OF THE SAME}

본 발명은 POP(Package On Package) 타입의 적층 반도체 패키지 및 그 제조방법에 관한 것이다.The present invention relates to a laminated semiconductor package of the POP (Package On Package) type and a method of manufacturing the same.

반도체 패키지는 용량 및 기능을 확장하기 위하여 웨이퍼 상태에서 집적도가 점차 증가하고 있으며, 두 개 이상의 반도체 칩 혹은 반도체 패키지를 하나로 통합하여 사용하는 적층 반도체 패키지도 일반화되고 있다. In order to expand the capacity and the function of the semiconductor package, the degree of integration is gradually increasing in the state of the wafer, and a multilayer semiconductor package in which two or more semiconductor chips or semiconductor packages are integrated into one is used.

웨이퍼 상태에서 반도체 소자의 기능을 확장하는 것은 많은 설비 투자가 필요하고 많은 비용이 소요되며 공정에서 발생할 수 있는 여러 가지 문제점들의 해결이 선결되어야 한다. 그러나, 반도체 칩을 만든 후 반도체 패키지로 조립(assembly)하는 과정에서 두 개 이상의 반도체 칩 혹은 두 개 이상의 반도체 패키지를 하나로 통합하는 것은 위에서 설명된 선결과제의 해결 없이도 달성이 가능하다. 또한, 웨이퍼 상태에서 용량 및 기능을 확장하는 방식과 비교하여 적은 설비투자와 비용으로 달성 가능하기 때문에 반도체 소자 제조업체에서는 SIP(System In Package), MCP(Multi Chip Package) 및 POP(Package On Package)와 같은 적층 반도체 패키지에 대한 연구 개발에 박차를 가하고 있다.Expanding the functionality of semiconductor devices in the wafer state requires a lot of equipment investment, is expensive, and must solve many problems that may occur in the process. However, in the process of fabricating a semiconductor chip and then assembling it into a semiconductor package, integrating two or more semiconductor chips or two or more semiconductor packages into one can be achieved without solving the above-described priorities. In addition, semiconductor device manufacturers can achieve system in package (SIP), multi chip package (MCP), and package on package (POP) because they can be achieved with less equipment investment and cost compared to the method of expanding capacity and function in wafer state. It is spurring research and development on the same stacked semiconductor package.

이러한 적층 반도체 패키지 중에서 POP 타입의 적층 반도체 패키지는 조립이 완료된 두 개의 반도체 패키지를 하나로 적층하는 방식을 채택하고 있다. 따라서, 각각의 반도체 패키지에 대한 최종 전기적 검사 단계를 통하여 양품의 반도체 패키지만을 선택하여 조립 가능한 장점이 있다.Among the stacked semiconductor packages, the POP type stacked semiconductor package adopts a method of stacking two assembled semiconductor packages into one. Therefore, there is an advantage that only the semiconductor packages of good quality can be selected and assembled through the final electrical inspection step for each semiconductor package.

도 1은 종래 기술에 따른 POP 타입의 적층 반도체 패키지를 도시한 단면도이다. 1 is a cross-sectional view showing a laminated semiconductor package of the POP type according to the prior art.

도 1을 참조하면, 하부 반도체 패키지(10) 및 상부 반도체 패키지(20)가 수직 방향으로 적층(stack)되어 있다. Referring to FIG. 1, the lower semiconductor package 10 and the upper semiconductor package 20 are stacked in a vertical direction.

하부 반도체 패키지(10)는 제1 기판(11), 제1 기판(11) 상에 범프(13)를 매개로 플립칩 본딩된 제1 반도체 칩(12), 제1 반도체 칩(12)을 포함한 제1 기판(11)의 중심부를 밀봉하는 제1 몰드부(14)를 포함한다. The lower semiconductor package 10 includes a first substrate 11, a first semiconductor chip 12 and a first semiconductor chip 12 flip-chip bonded to each other via a bump 13 on the first substrate 11. The first mold part 14 which seals the central part of the first substrate 11 is included.

그리고, 상부 반도체 패키지(20)는 제2 기판(21), 제2 기판(21) 상에 부착된 제2 반도체 칩(22), 제2 반도체 칩(22)과 제2 기판(21)을 전기적으로 연결하는 본딩 와이어(23), 제2 반도체 칩(22)을 포함한 제2 기판(21)의 상부면을 밀봉하는 제2 몰드부(24) 및 제2 기판(21) 하부면의 제2 볼랜드(25)에 장착된 솔더볼(30)을 구비한다. The upper semiconductor package 20 electrically connects the second substrate 21, the second semiconductor chip 22, the second semiconductor chip 22, and the second substrate 21 attached to the second substrate 21. Bonding wires 23 connected to each other, the second mold part 24 sealing the upper surface of the second substrate 21 including the second semiconductor chip 22 and the second borland on the lower surface of the second substrate 21. The solder ball 30 attached to the 25 is provided.

그리고, 상기 솔더볼(30)은 하부 반도체 패키지(10)의 제1 몰드부(41) 바깥쪽 제1 기판(11)의 상부면에 마련된 제1 볼랜드(15)과 접합되게 되며, 이에 따라 하부 반도체 패키지(10)와 상부 반도체 패키지(20)가 하나로 통합되어 동작하게 된다. In addition, the solder ball 30 is bonded to the first ball land 15 provided on the upper surface of the first substrate 11 outside the first mold part 41 of the lower semiconductor package 10. The package 10 and the upper semiconductor package 20 are integrated into one operation.

반도체 장치의 다기능화, 고집적화됨에 따라서 반도체 장치에서 요구되는 입출력(Input/Output) 개수가 점차 증가되고 있다. 전술한 POP 타입의 적층 반도체 패키지에서 입출력 개수를 늘리기 위해서는 솔더볼(30)의 피치(pitch, H1)를 감소시켜야 한다. 그러나, 하부 반도체 패키지(10)와 상부 반도체 패키지(20)간 연결을 위해서는 솔더볼(30)의 피치(H1)가 하부 반도체 패키지(10)의 제1 몰드부(14)의 두께(H2)보다 커야 하는 조건을 충족해야만 하기 때문에, 입출력 개수를 늘리기 어려운 실정이다. As the semiconductor devices become more versatile and highly integrated, the number of input / outputs required by the semiconductor devices is gradually increasing. In order to increase the number of input and output in the POP type stacked semiconductor package, the pitch (H1) of the solder ball 30 should be reduced. However, in order to connect the lower semiconductor package 10 and the upper semiconductor package 20, the pitch H1 of the solder ball 30 must be greater than the thickness H2 of the first mold part 14 of the lower semiconductor package 10. It is difficult to increase the number of input and output because the conditions must be satisfied.

제1반도체 칩(12)의 두께를 줄이거나, 범프(13)의 높이를 낮추면 제1 몰드부(14) 높이(H2)를 줄일 수 있어 솔더볼(30)의 피치(H1) 감소가 가능하지만, 제1 반도체 칩(12)의 두께를 줄이면 장시간 동작시 제1 반도체 칩(12)에 기능 에러(function error)가 발생되고, 범프(13)의 높이를 낮추면 제1 반도체 칩(12)과 제1 기판(11)간 간격이 감소되어 제1 반도체 칩(12)과 제1 기판(11) 사이에 제1 몰드부(14)가 제대로 충진되지 않아 보이드(void)가 발생되게 된다. If the thickness of the first semiconductor chip 12 is reduced or the height of the bump 13 is reduced, the height H2 of the first mold part 14 may be reduced, so that the pitch H1 of the solder ball 30 may be reduced. When the thickness of the first semiconductor chip 12 is reduced, a function error occurs in the first semiconductor chip 12 during a long time operation. When the height of the bump 13 is lowered, the first semiconductor chip 12 and the first semiconductor chip 12 are reduced. Since the gap between the substrates 11 is reduced, the voids are generated because the first mold part 14 is not properly filled between the first semiconductor chip 12 and the first substrate 11.

한편, 패키지 조립 도중 또는 조립 이후에 열팽창률 및 강율(rate of rigidity) 차이로 인하여 반도체 패키지들(10,20)이 이동되고, 이로 인해 솔더볼(30)에 전단 응력이 가해져 솔더볼(30)에 크랙이 발생되는 등 제품의 신뢰성 및 전기적인 특성이 저하되는 문제점이 있었다. Meanwhile, the semiconductor packages 10 and 20 are moved due to a difference in thermal expansion rate and rate of rigidity during or after package assembly, and a shear stress is applied to the solder ball 30 to crack the solder ball 30. There was a problem in that the reliability and electrical properties of the product is lowered.

본 발명은 종래 기술의 문제점을 해결하기 위하여 안출한 것으로, 입출력 개수를 늘릴 수 있고 제품의 신뢰성 및 전기적 특성을 향상시키기에 적합한 적층 반도체 패키지를 제공하는데, 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and it is an object of the present invention to provide a multilayer semiconductor package suitable for increasing the number of input and output and improving the reliability and electrical characteristics of a product.

본 발명의 다른 목적은, 상기 적층 반도체 패키지의 제조방법을 제공하는데, 있다.Another object of the present invention is to provide a method for manufacturing the laminated semiconductor package.

본 발명의 일 견지에 따른 적층 반도체 패키지는, 상면에 제1 볼랜드가 형성된 제1 기판, 상기 제1 볼랜드 상에 장착된 제1 솔더볼 및 상기 제1 기판의 상면을 밀봉하고 상기 제1 솔더볼을 노출하는 홈을 구비하는 제1 몰드부를 포함하는 하부 반도체 패키지;및 하단부에 제2 솔더볼을 구비하며, 상기 제2 솔더볼이 상기 홈에 결합되고 상기 홈 하부의 상기 제1 솔더볼과 접합되도록 상기 하부 반도체 패키지 상에 적층된 상부 반도체 패키지를 포함한다. According to an aspect of the present disclosure, a multilayer semiconductor package may include a first substrate having a first borland formed on an upper surface thereof, a first solder ball mounted on the first borland, and an upper surface of the first substrate and exposing the first solder ball. A lower semiconductor package including a first mold portion having a groove; and a second solder ball at a lower end thereof, wherein the second solder ball is coupled to the groove and bonded to the first solder ball under the groove; And an upper semiconductor package stacked thereon.

상기 하부 반도체 패키지는 상기 제1 볼랜드 안쪽 상기 제1 기판의 상면에 실장된 제1 반도체 칩을 더 포함할 수 있다. The lower semiconductor package may further include a first semiconductor chip mounted on an upper surface of the first substrate in the first borland.

그리고, 상기 상부 반도체 패키지는 하면에 상기 제2 솔더볼이 장착된 제2 기판; 상기 제2 기판의 상면에 실장된 제2 반도체 칩;및 상기 제2 반도체 칩을 포함한 상기 제2 기판의 상면을 밀봉하는 제2 몰드부를 더 포함할 수 있다. The upper semiconductor package may further include: a second substrate on which the second solder balls are mounted; The semiconductor device may further include a second semiconductor chip mounted on an upper surface of the second substrate; and a second mold part sealing an upper surface of the second substrate including the second semiconductor chip.

상기 제1 기판은 상기 제1 볼랜드를 복수개 구비하며, 상기 홈은 상기 제1 볼랜드들 상에 장착된 제1 솔더볼들을 동시에 노출하는 라인 형태로 형성될 수도 있다. 이와 달리, 상기 홈은 상기 제1 볼랜드들 상에 장착된 제1 솔더볼들을 개별적으로 노출하도록 형성될 수도 있다. The first substrate may include a plurality of first ball lands, and the groove may be formed in a line shape simultaneously exposing the first solder balls mounted on the first ball lands. Alternatively, the groove may be formed to individually expose the first solder balls mounted on the first borland.

상기 제1 솔더볼은 상부 표면에 상기 홈과 연결된 트렌치를 구비할 수 있다. 상기 트렌치의 측벽은 사선형 슬로프를 가질 수 있다. 이와 달리, 상기 트렌치의 측벽은 곡선형 슬로프를 가질 수도 있다. The first solder ball may have a trench connected to the groove on an upper surface thereof. The sidewalls of the trench may have an oblique slope. Alternatively, the sidewalls of the trench may have a curved slope.

본 발명의 다른 견지에 따른 적층 반도체 패키지의 제조방법은, 하부 반도체 패키지의 제1 기판의 상면에 마련된 제1 볼랜드 상에 제1 솔더볼을 장착하는 단계; 상기 제1 솔더볼을 포함한 상기 제1 기판의 상면을 밀봉하는 제1 몰드부를 형성하는 단계; 상기 제1 몰드부에 상기 제1 솔더볼을 노출하는 홈을 형성하는 단계;및 상부 반도체 패키지의 하단부에 마련된 제2 솔더볼을 상기 홈에 삽입한 후 상기 제2 솔더볼과 상기 제1 솔더볼을 접합시키는 단계를 포함한다. According to another aspect of the present invention, a method of manufacturing a multilayer semiconductor package includes mounting a first solder ball on a first borland provided on an upper surface of a first substrate of a lower semiconductor package; Forming a first mold part to seal an upper surface of the first substrate including the first solder ball; Forming a groove exposing the first solder ball in the first mold part; and inserting a second solder ball provided in the lower end of the upper semiconductor package into the groove, and then joining the second solder ball and the first solder ball to each other. It includes.

상기 홈을 형성하는 단계는 블레이드를 이용하여 상기 제1 몰드부를 절단하는 방식으로 수행될 수 있다. 이와 달리, 상기 홈을 형성하는 단계는 레이저를 이용하여 상기 제1 몰드부를 절단하는 방식으로 수행될 수도 있고, 상기 제1 몰드부 상에 상기 제1 몰드부의 일부분을 노출하는 마스크 패턴을 형성하고 몰드 수지 에천트를 이용하여 상기 마스크 패턴에 의해 노출된 제1 몰드부를 제거하는 방식으로 수행될 수도 있다. The forming of the groove may be performed by cutting the first mold part using a blade. Alternatively, the forming of the groove may be performed by cutting the first mold part using a laser, and forming a mask pattern exposing a portion of the first mold part on the first mold part and forming a mold. The resin mold may be used to remove the first mold part exposed by the mask pattern.

상기 홈을 형성하는 단계에서 상기 홈 하부의 제1 솔더볼을 일부 제거하여 상기 제1 솔더볼의 상부 표면에 트렌치를 더 형성할 수도 있다. In the forming of the groove, the trench may be further formed on the upper surface of the first solder ball by partially removing the first solder ball under the groove.

본 발명에 따르면, 상부 반도체 패키지와 하부 반도체 패키지를 연결하는 솔더볼의 피치가 종래에 비해 감소되므로 솔더볼의 피치가 큼으로 인하여 제안되었던 입출력 개수를 늘릴 수 있다. 또한, 상부 반도체 패키지의 솔더볼이 하부 반도체 패키지의 몰드부에 형성된 홈과 결합되어 상, 하부 반도체 패키지들간 결속력이 향상되므로 열팽률 및 강율 차이로 인한 반도체 패키지들의 이동이 감소되므로 상, 하부 반도체 패키지들을 연결하는 솔더볼에 크랙이 발생되지 않아 제품의 전기적 특성 및 신뢰성이 향상된다. According to the present invention, the pitch of the solder ball connecting the upper semiconductor package and the lower semiconductor package is reduced compared to the conventional, it is possible to increase the number of input and output proposed due to the large pitch of the solder ball. In addition, the solder balls of the upper semiconductor package are combined with the grooves formed in the mold of the lower semiconductor package, thereby improving the binding force between the upper and lower semiconductor packages, thereby reducing the movement of the semiconductor packages due to thermal expansion and the difference in strength. Cracks do not occur in the solder balls, which improves the electrical characteristics and reliability of the product.

도 1은 종래 기술에 따른 POP 타입의 적층 반도체 패키지를 도시한 단면도이다.
도 2는 본 발명의 실시예에 따른 적층 반도체 패키지를 도시한 단면도이다.
도 3은 도 2의 분해도이다.
도 4는 도 2에 도시된 하부 반도체 패키지를 상부측에서 바라본 평면도이다.
도 5는 제1 솔더볼의 다른 실시 형태를 나타낸 도면들이다.
도 7a 내지 도 7d는 본 발명의 실시예에 따른 적층 반도체 패키지의 제조 방법을 설명하기 위한 단면도들이다.1 is a cross-sectional view showing a laminated semiconductor package of the POP type according to the prior art.
2 is a cross-sectional view illustrating a multilayer semiconductor package according to an embodiment of the present invention.
3 is an exploded view of Fig.
FIG. 4 is a plan view of the lower semiconductor package illustrated in FIG. 2 as viewed from the upper side.
5 is a view showing another embodiment of the first solder ball.
7A to 7D are cross-sectional views illustrating a method of manufacturing a multilayer semiconductor package according to an embodiment of the present invention.

이하, 첨부된 도면들을 참조하여 본 발명의 바람직한 실시예들을 상세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명의 실시예에 따른 적층 반도체 패키지를 도시한 단면도이고, 도 3은 도 2의 분해도이고, 도 4는 도 2에 도시된 하부 반도체 패키지를 상부측에서 바라본 평면도이고, 도 5는 제1 솔더볼의 다른 실시 형태를 설명하기 위한 도면들이다. 2 is a cross-sectional view illustrating a multilayer semiconductor package according to an exemplary embodiment of the present invention, FIG. 3 is an exploded view of FIG. 2, FIG. 4 is a plan view of the lower semiconductor package shown in FIG. It is a figure for demonstrating another embodiment of a 1st solder ball.

도 2 및 도 3을 참조하면, 본 발명의 실시예에 따른 적층 반도체 패키지는 하부 반도체 패키지(100) 및 상부 반도체 패키지(200)를 포함한다.2 and 3, a multilayer semiconductor package according to an embodiment of the present invention includes a lower semiconductor package 100 and an upper semiconductor package 200.

하부 반도체 패키지(100)는 제1 기판(110), 제1 반도체 칩(120), 제1 솔더볼(130) 및 제1 몰드부(140)을 포함한다. The lower semiconductor package 100 includes a first substrate 110, a first semiconductor chip 120, a first solder ball 130, and a first mold part 140.

제1 기판(110)은 상면(110A) 및 상면(110A)과 대향하는 하면(110B)을 가지며, 상면(110A) 중심부에 형성된 제1 접속 패드(111), 상면(110A) 가장자리에 형성된 제1 볼랜드(112) 및 하면(110B)에 형성된 제2 볼랜드(113)를 포함한다. The first substrate 110 has an upper surface 110A and a lower surface 110B facing the upper surface 110A, and the first connection pad 111 formed at the center of the upper surface 110A and the first surface formed at the edge of the upper surface 110A. And a second borland 113 formed on the borland 112 and the lower surface 110B.

제1 반도체 칩(120)은 제1 본딩 패드(121) 및 제1 본딩 패드(121) 상에 형성된 범프(122)를 구비하며, 제1 반도체 칩(120)은 범프(122)를 매개로 제1 기판(110)의 제1 접속 패드(111) 상에 플립칩 본딩(flip chip bonding)되어 있다. The first semiconductor chip 120 includes a first bonding pad 121 and a bump 122 formed on the first bonding pad 121, and the first semiconductor chip 120 is formed through the bump 122. 1 is flip chip bonding on the first connection pad 111 of the substrate 110.

비록, 본 실시예에서는 하나의 제1 반도체 칩(120)이 제1 기판(110)에 플립칩 본딩 방식으로 연결된 경우를 도시 및 설명하였으나, 본 발명은 이에 한정되지 않는다. 예컨데, 제1 반도체 칩(120)은 제1 기판(110)과 와이어 본딩 방식으로 연결될 수도 있고, 복수개의 제1 반도체 칩(120)이 제1 기판(110) 상에 수평 실장되거나, 수직하게 적층될 수도 있다. Although the first semiconductor chip 120 is connected to the first substrate 110 by the flip chip bonding method in the present embodiment, the present invention is not limited thereto. For example, the first semiconductor chip 120 may be connected to the first substrate 110 by wire bonding, and the plurality of first semiconductor chips 120 may be horizontally mounted on the first substrate 110 or vertically stacked. May be

상기 제1 솔더볼(130)은 제1 기판(110) 상면(110A)의 제1 볼랜드(112) 상에장착된다. 제1 몰드부(140)는 제1 반도체 칩(120)을 포함한 제1 기판(110) 상면(110A)을 밀봉하며 제1 솔더볼(130)을 노출하는 홈(141)을 갖는다.The first solder ball 130 is mounted on the first ball land 112 of the upper surface 110A of the first substrate 110. The first mold part 140 has a groove 141 that seals the upper surface 110A of the first substrate 110 including the first semiconductor chip 120 and exposes the first solder balls 130.

도 4를 참조하면, 홈(141)은 다수개의 제1 솔더볼(130)들을 동시에 노출하는 라인(line) 형태로 형성될 수 있다. 이와 달리, 도면으로 나타내지 않았지만 홈(141)은 제1 솔더볼(130)들을 개별적으로 노출하도록 형성될 수도 있다. Referring to FIG. 4, the groove 141 may be formed in a line shape to simultaneously expose the plurality of first solder balls 130. Alternatively, although not illustrated, the groove 141 may be formed to individually expose the first solder balls 130.

도 2 및 도 3을 다시 참조하면, 제1 솔더볼(130)과 상부 반도체 패키지(200)의 제2 솔더볼(240)간의 접합 면적을 확보하기 위하여, 제1 솔더볼(130)의 상부 표면에는 홈(141)과 연결된 트렌치(131)가 형성되어 있다. 트렌치(131)의 측벽은 사선형의 슬로프를 가질 수 있다. Referring to FIGS. 2 and 3 again, in order to secure a junction area between the first solder ball 130 and the second solder ball 240 of the upper semiconductor package 200, grooves (not shown) may be formed in the upper surface of the first solder ball 130. A trench 131 connected to the 141 is formed. The sidewalls of the trench 131 may have diagonal slopes.

이와 달리, 도 5에 나타낸 바와 같이 트렌치(131)의 측벽은 곡선형 슬로프를 가질 수도 있다. Alternatively, as shown in FIG. 5, the sidewalls of the trench 131 may have curved slopes.

도 2 및 도 3을 다시 참조하면, 상부 반도체 패키지(200)는 제2 기판(210), 제2 반도체 칩(220), 제2 몰드부(230) 및 제2 솔더볼(240)을 포함한다. Referring to FIGS. 2 and 3 again, the upper semiconductor package 200 includes a second substrate 210, a second semiconductor chip 220, a second mold part 230, and a second solder ball 240.

제2 기판(210)은 상면(210A)에 제2 접속 패드(211)를 구비하고, 하면(210B)에 제3 볼랜드(212)를 구비한다. The second substrate 210 includes a second connection pad 211 on the top surface 210A, and a third ball land 212 on the bottom surface 210B.

제2 반도체 칩(220)은 제2 접속 패드(211) 안쪽 제2 기판(210) 상면(210A) 상에 접착 부재(250)를 매개로 부착된다. 제2 반도체 칩(220)은 제2 기판(210)에 부착된 일면(220A) 및 일면(220A)과 대향하는 타면(220B)을 가지며, 제2 반도체 칩(220)의 타면(220B)에는 제2 본딩 패드(221)가 형성되어 있다. 그리고, 제2 기판(210)의 제2 접속 패드(211)와 제2 반도체 칩(220)의 제2 본딩 패드(221)는 본딩 와이어(260)를 매개로 전기적으로 연결되어 있다. The second semiconductor chip 220 is attached to the upper surface 210A of the second substrate 210 inside the second connection pad 211 via the adhesive member 250. The second semiconductor chip 220 has one surface 220A attached to the second substrate 210 and the other surface 220B facing the one surface 220A, and the second semiconductor chip 220 has a second surface 220B on the other surface 220B of the second semiconductor chip 220. 2 bonding pads 221 are formed. In addition, the second connection pad 211 of the second substrate 210 and the second bonding pad 221 of the second semiconductor chip 220 are electrically connected to each other via the bonding wire 260.

비록, 본 실시예에서는 하나의 제2 반도체 칩(220)이 제2 기판(10)에 와이어 본딩 방식으로 연결된 경우를 도시 및 설명하였으나, 본 발명은 이에 한정되지 않는다. 예컨데, 제2 반도체 칩(220)은 제2 기판(210)과 플립칩 본딩 방식으로 연결될 수도 있고, 복수개의 제2 반도체 칩(220)이 제2 기판(210) 상에 수평 실장되거나, 수직하게 적층될 수도 있다. Although the present embodiment illustrates and describes a case in which one second semiconductor chip 220 is connected to the second substrate 10 by wire bonding, the present invention is not limited thereto. For example, the second semiconductor chip 220 may be connected to the second substrate 210 by flip chip bonding, and the plurality of second semiconductor chips 220 may be horizontally mounted on the second substrate 210 or vertically. It may be stacked.

상기 제2 몰드부(230)는 제2 반도체 칩(220)을 포함한 제2 기판(210) 상면(210A)을 밀봉하고, 상기 제2 솔더볼(240)은 제2 기판(210)의 제3 볼랜드(212) 상에 장착된다. The second mold part 230 seals the upper surface 210A of the second substrate 210 including the second semiconductor chip 220, and the second solder ball 240 is the third borland of the second substrate 210. 212 is mounted on.

그리고, 상부 반도체 패키지(200)는 제2 솔더볼(240)이 하부 반도체 패키지(100)의 제1 몰드부(140)에 형성된 홈(141)과 결합되고 홈(141) 하부의 제1 솔더볼(130)과 접합되도록 하부 반도체 패키지(100) 상에 적층된다. In the upper semiconductor package 200, the second solder balls 240 are coupled to the grooves 141 formed in the first mold part 140 of the lower semiconductor package 100 and the first solder balls 130 under the grooves 141. ) Is stacked on the lower semiconductor package 100 to be bonded.

상부 반도체 패키지(200)의 구조는 전술한 실시예에 한정되지 않으며 다양한 변형이 가능하다. 예컨데, 상부 반도체 패키지(200)는 기판 없이 웨이퍼 레벨(wafer level)로 제작된 웨이퍼 레벨 패키지 일 수도 있다. The structure of the upper semiconductor package 200 is not limited to the above-described embodiment and various modifications are possible. For example, the upper semiconductor package 200 may be a wafer level package manufactured at a wafer level without a substrate.

미설명된 도면부호 150은 제1 기판(110) 하면(110B)의 제2 볼랜드(113) 상에 장착된 제3 솔더볼을 나타낸다. Unexplained reference numeral 150 denotes a third solder ball mounted on the second ball land 113 of the bottom surface 110B of the first substrate 110.

전술한 적층 반도체 패키지의 제조방법은 다음과 같다.The manufacturing method of the above-mentioned laminated semiconductor package is as follows.

도 7a 내지 도 7d는 본 발명의 실시예에 따른 적층 반도체 패키지의 제조 방법을 설명하기 위한 단면도들이다.7A to 7D are cross-sectional views illustrating a method of manufacturing a multilayer semiconductor package according to an embodiment of the present invention.

먼저, 도 7a를 참조하면 하부 반도체 패키지(100)의 제1 기판(110)의 상면(110A)에 마련된 제1 접속 패드(111) 상에 범프(122)를 매개로 제1 반도체 칩(120)을 플립칩 본딩하고, 제1 기판(110) 상면(110A)에 마련된 제1 볼랜드(112) 상에 제1 솔더볼(130)을 장착한다.First, referring to FIG. 7A, the first semiconductor chip 120 may be formed on the first connection pad 111 provided on the top surface 110A of the first substrate 110 of the lower semiconductor package 100 through the bumps 122. Is flip-chip bonded, and the first solder balls 130 are mounted on the first ball lands 112 provided on the top surface 110A of the first substrate 110.

그 다음, 도 7b를 참조하면 제1 반도체 칩(120) 및 제1 솔더볼(130)을 포함한 제1 기판(110)의 상면(110A)을 밀봉하는 제1 몰드부(140)를 형성하고, 제1 기판(110) 하면(110B)에 마련된 제2 볼랜드(113) 상에 솔더볼(150)을 장착한다.Next, referring to FIG. 7B, a first mold part 140 is formed to seal the top surface 110A of the first substrate 110 including the first semiconductor chip 120 and the first solder ball 130. 1 The solder ball 150 is mounted on the second ball land 113 provided on the bottom surface 110B of the substrate 110.

도 7c를 참조하면, 제1 몰드부(140)에 제1 솔더볼(130)을 노출하는 홈(141)을 형성한다.Referring to FIG. 7C, a groove 141 exposing the first solder ball 130 may be formed in the first mold part 140.

홈(141)을 형성하는 방법으로는 블레이드(blade)를 이용하여 제1 몰드부(140)를 절단하는 방법, 레이저(laser)를 이용하여 제1 몰드부(140)를 절단하는 방법, 제1 몰드부(140) 상에 제1 몰드부(140)를 선택적으로 노출하는 마스크 패턴을 형성하고 몰드 수지 에천트를 이용하여 노출된 제1 몰드부(140)를 제거하는 방법 등이 사용할 수도 있다.As a method of forming the groove 141, a method of cutting the first mold part 140 using a blade, a method of cutting the first mold part 140 using a laser, and a first method A method of forming a mask pattern for selectively exposing the first mold part 140 on the mold part 140 and removing the exposed first mold part 140 using a mold resin etchant may be used.

상기 홈(141)을 형성하는 과정에서, 제1 솔더볼(130)이 일부 식각되게 되며, 이에 따라서 제1 솔더볼(130)의 상부 표면에는 홈(141)과 연결된 트렌치(131)가 형성되게 된다. In the process of forming the groove 141, the first solder ball 130 is partially etched, and thus the trench 131 connected to the groove 141 is formed on the upper surface of the first solder ball 130.

그 다음, 도 7d를 참조하면, 상부 반도체 패키지(200)의 하단부에 마련된 제2 솔더볼(240)을 하부 반도체 패키지(100)의 제1 몰드부(140)의 홈(141)에 삽입하고, 리플로우 공정을 실시하여 상부 반도체 패키지(200)의 제2 솔더볼(240)과 하부 반도체 패키지(100)의 제1 솔더볼(130) 간을 접합시키어, 본 발명에 따른 적층 반도체 패키지를 완성한다. Next, referring to FIG. 7D, the second solder ball 240 provided at the lower end of the upper semiconductor package 200 is inserted into the groove 141 of the first mold part 140 of the lower semiconductor package 100, and then rippled. The row process is performed to bond the second solder balls 240 of the upper semiconductor package 200 and the first solder balls 130 of the lower semiconductor package 100 to complete the laminated semiconductor package according to the present invention.

이상에서 상세하게 설명한 바에 의하면, 상부 반도체 패키지와 하부 반도체 패키지를 연결하는 솔더볼의 피치가 종래에 비해 감소되므로 솔더볼의 피치가 큼으로 인하여 제안되었던 입출력 개수를 늘릴 수 있다. 또한, 상부 반도체 패키지의 솔더볼이 하부 반도체 패키지의 몰드부에 형성된 홈과 결합되어 상, 하부 반도체 패키지들간 결속력이 향상되므로 열팽률 및 강율 차이로 인한 반도체 패키지들의 이동이 감소되므로 상, 하부 반도체 패키지들을 연결하는 솔더볼에 크랙이 발생되지 않아 제품의 전기적 특성 및 신뢰성이 향상된다. As described in detail above, since the pitch of the solder balls connecting the upper semiconductor package and the lower semiconductor package is reduced as compared with the related art, the number of input and output proposed due to the large pitch of the solder balls can be increased. In addition, the solder balls of the upper semiconductor package are combined with the grooves formed in the mold of the lower semiconductor package, thereby improving the binding force between the upper and lower semiconductor packages, thereby reducing the movement of the semiconductor packages due to thermal expansion and the difference in strength. Cracks do not occur in the solder balls, which improves the electrical characteristics and reliability of the product.

앞서 설명한 본 발명의 상세한 설명에서는 본 발명의 실시예들을 참조하여 설명하였지만, 해당 기술분야의 숙련된 당업자 또는 해당 기술분야에 통상의 지식을 갖는 자라면 후술 될 특허청구범위에 기재된 본 발명의 사상 및 기술 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention can be variously modified and changed without departing from the technical scope thereof.

100: 하부 반도체 패키지
110 : 제1 기판
130 : 제1 솔더볼
140 : 제1 몰드부
141: 홈
200 : 상부 반도체 패키지
240 : 제2 솔더볼100: lower semiconductor package
110: first substrate
130: first solder ball
140: first mold part
141: home
200: upper semiconductor package
240: second solder ball

Claims (14)

상면에 제1 볼랜드가 형성된 제1 기판, 상기 제1 볼랜드 상에 장착된 제1 솔더볼 및 상기 제1 기판의 상면을 밀봉하고 상기 제1 솔더볼을 노출하는 홈을 구비하는 제1 몰드부를 포함하는 하부 반도체 패키지;및
하단부에 제2 솔더볼을 구비하며, 상기 제2 솔더볼이 상기 홈과 결합되고 상기 홈 하부의 상기 제1 솔더볼과 접합되도록 상기 하부 반도체 패키지 상에 적층된 상부 반도체 패키지를 포함하며,
상기 제1 솔더볼은 상부 표면에 상기 홈과 연결된 트렌치를 구비하는 것을 특징으로 하는 적층 반도체 패키지.A lower portion including a first substrate having a first ball land formed on an upper surface thereof, a first solder ball mounted on the first ball land, and a groove for sealing an upper surface of the first substrate and exposing the first solder ball; Semiconductor package; and
A lower semiconductor package having a second solder ball at a lower end thereof, the upper semiconductor package stacked on the lower semiconductor package such that the second solder ball is coupled to the groove and bonded to the first solder ball below the groove;
And the first solder ball has a trench connected to the groove on an upper surface thereof. 제 1항에 있어서, 상기 하부 반도체 패키지는 상기 제1 볼랜드 안쪽 상기 제1 기판의 상면에 실장된 제1 반도체 칩을 더 포함하는 것을 특징으로 하는 적층 반도체 패키지.The multilayer semiconductor package of claim 1, wherein the lower semiconductor package further comprises a first semiconductor chip mounted on an upper surface of the first substrate inside the first borland. 제 1항에 있어서, 상기 상부 반도체 패키지는 하면에 상기 제2 솔더볼이 장착된 제2 기판;
상기 제2 기판의 상면에 실장된 제2 반도체 칩;및
상기 제2 반도체 칩을 포함한 상기 제2 기판의 상면을 밀봉하는 제2 몰드부를 더 포함하는 것을 특징으로 하는 적층 반도체 패키지.The semiconductor package of claim 1, wherein the upper semiconductor package comprises: a second substrate on which a second solder ball is mounted;
A second semiconductor chip mounted on an upper surface of the second substrate; and
And a second mold part for sealing an upper surface of the second substrate including the second semiconductor chip. 제 1항에 있어서, 상기 제1 기판은 상기 제1 볼랜드를 복수개 구비하며,
상기 홈은 상기 제1 볼랜드들 상에 장착된 제1 솔더볼들을 동시에 노출하는 라인 형태로 형성된 것을 특징으로 하는 적층 반도체 패키지.The method of claim 1, wherein the first substrate is provided with a plurality of the first borland,
And the groove is formed in a line shape simultaneously exposing the first solder balls mounted on the first borlands. 제 1항에 있어서, 상기 제1 기판은 상기 제1 볼랜드를 복수개 구비하며,
상기 홈은 상기 제1 볼랜드들 상에 장착된 제1 솔더볼들을 개별적으로 노출하도록 형성된 것을 특징으로 하는 적층 반도체 패키지.The method of claim 1, wherein the first substrate is provided with a plurality of the first borland,
And the groove is formed to individually expose first solder balls mounted on the first borlands. 삭제delete 제 1항에 있어서, 상기 트렌치의 측벽은 사선형 슬로프를 갖는 것을 특징으로 하는 적층 반도체 패키지.The laminated semiconductor package of claim 1, wherein the sidewalls of the trench have diagonal slopes. 제 1항에 있어서, 상기 트렌치의 측벽은 곡선형 슬로프를 갖는 것을 특징으로 하는 적층 반도체 패키지.The laminated semiconductor package of claim 1, wherein the sidewalls of the trench have curved slopes. 삭제delete 하부 반도체 패키지의 제1 기판의 상면에 마련된 제1 볼랜드 상에 제1 솔더볼을 장착하는 단계;
상기 제1 솔더볼을 포함한 상기 제1 기판의 상면을 밀봉하는 제1 몰드부를 형성하는 단계;
상기 제1 몰드부에 상기 제1 솔더볼을 노출하는 홈을 형성하는 단계;및
상부 반도체 패키지의 하단부에 마련된 제2 솔더볼을 상기 홈에 삽입한 후 상기 제2 솔더볼과 상기 제1 솔더볼을 접합시키는 단계를 포함하며,
상기 홈을 형성하는 단계에서 상기 홈 하부의 제1 솔더볼을 일부 제거하여 상기 제1 솔더볼의 상부 표면에 트렌치를 형성하는 것을 특징으로 하는 적층 반도체 패키지의 제조방법.Mounting a first solder ball on a first ball land provided on an upper surface of the first substrate of the lower semiconductor package;
Forming a first mold part to seal an upper surface of the first substrate including the first solder ball;
Forming a groove exposing the first solder ball in the first mold part; and
Inserting a second solder ball provided in the lower end of the upper semiconductor package into the groove, and then bonding the second solder ball to the first solder ball,
And forming a trench on an upper surface of the first solder ball by partially removing the first solder ball under the groove in the forming of the groove. 제 10항에 있어서, 상기 홈을 형성하는 단계는 블레이드를 이용하여 상기 제1 몰드부를 절단하는 방식으로 수행되는 것을 특징으로 하는 적층 반도체 패키지의 제조방법.The method of claim 10, wherein the forming of the groove is performed by cutting the first mold part using a blade. 제 10항에 있어서, 상기 홈을 형성하는 단계는 레이저를 이용하여 상기 제1 몰드부를 절단하는 방식으로 수행되는 것을 특징으로 하는 적층 반도체 패키지의 제조방법.The method of claim 10, wherein the forming of the groove is performed by cutting the first mold part using a laser. 제 10항에 있어서, 상기 홈을 형성하는 단계는 상기 제1 몰드부 상에 상기 제1 몰드부의 일부분을 노출하는 마스크 패턴을 형성하고 몰드 수지 에천트를 이용하여 상기 마스크 패턴에 의해 노출된 제1 몰드부를 제거하는 방식으로 수행되는 것을 특징으로 하는 적층 반도체 패키지의 제조방법.The method of claim 10, wherein the forming of the groove comprises forming a mask pattern exposing a portion of the first mold part on the first mold part and exposing the first pattern part by the mask pattern using a mold resin etchant. Method of manufacturing a laminated semiconductor package, characterized in that carried out in a way to remove the mold portion. 삭제delete
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