KR101352362B1 - Thermoelectric device and method of forming the same, temperature sensing sensor, and heat-source image sensor using the same - Google Patents

Abstract

A thermoelectric element, a method of forming the same, a temperature sensing sensor, and a heat source image sensor using the same are provided. The thermoelectric device includes a first nanowire and a second nanowire disposed on a substrate, spaced apart from each other, a first silicon thin film connected to one end of the first nanowire, a second silicon thin film connected to one end of the second nanowire, and a first one. And a third silicon thin film connected to the other end of the nanowire and the other end of the second nanowire, wherein the first nanowire and the second nanowire extend in a horizontal direction with respect to the upper surface of the substrate.

Description

Thermoelectric element and its formation method, temperature sensing sensor and heat source image sensor using the same {THERMOELECTRIC DEVICE AND METHOD OF FORMING THE SAME, TEMPERATURE SENSING SENSOR, AND HEAT-SOURCE IMAGE SENSOR USING THE SAME}

The present invention relates to a thermoelectric element, a method of forming the same, a temperature sensing sensor, and a heat source image sensor, and more particularly, to a thermoelectric element, a temperature sensing sensor, and a heat source image sensor using nanowires.

Thermoelectric devices are devices that convert thermal energy into electrical energy and are one of the representative technical fields that can satisfy energy and eco-friendly policies at the same time. The heat source of the thermoelectric element can use all the heat existing on the earth as the energy source such as solar heat, automobile waste heat, geothermal heat, body heat and radioactive heat.

The thermoelectric effect was first discovered by Thomas Seebeck in the 1800s. Seebeck connects bismuth with copper and places a compass in it. The hot heating of one side of bismuth induces a current due to the temperature difference, and the magnetic field generated by this induced current affects the compass, demonstrating the thermoelectric effect for the first time.

The figure of merit (ZT) is used as an indicator of thermoelectric efficiency. The ZT value is proportional to the square of the Seebeck coefficient and the electrical conductivity and inversely proportional to the thermal conductivity. These are highly dependent on the intrinsic properties of the material. In the case of metal, the Seebeck coefficient value is very low, such as a few kW / K, and according to the Wiedemann-Franz law, there is a proportional relationship between electrical conductivity and thermal conductivity. On the other hand, through constant research by scientists on semiconductor materials, thermoelectric devices whose body heat and radiation heat are the heat sources are brought to the market. However, the market size is still small. As commercialized thermoelectric materials, Bi ₂ Te ₃ is used around room temperature and medium temperature, and SiGe is used at high temperature. The ZT value of Bi ₂ Te ₃ has a maximum value of 0.9 at room temperature of 0.7 and 120 ° C. The ZT value of SiGe has a maximum value of 0.9 at about 0.1 and 900 ° C at room temperature.

Research based on silicon, the basic material of the semiconductor industry, is also receiving attention. Since silicon has a very high thermal conductivity of 150 W / m · K and a ZT value of 0.01, it has been recognized that it is difficult to be used as a thermoelectric element. However, recently, in the case of silicon nanowires grown by chemical vapor deposition, the thermal conductivity can be reduced to 0.01 times or less, and thus the ZT value is reported to be close to 1.

However, integration and commercialization of silicon nanowire-based thermoelectric devices using existing technologies face great difficulties. One of the biggest reasons is the absence of a method for manufacturing nanowires that can be mass-produced. Most of the production methods use a catalyst or non-catalyst method to grow individually in a furnace. However, such an individual growth method has two disadvantages. First, nanowires do not grow consistently in only one direction, and some nanowires grow in undesired directions and interfere with the growth of other nanowires, which places great constraints on obtaining high-quality nanowires. Second, the nanowires grown in the furnace must be moved to the device and then attached to the device. In other words, the integrated production of nanowires and the device is not made, mass production is impossible, and the cost increases because the process takes a lot of time.

It is an object of the present invention to provide a thermoelectric element and a method of forming the same, a temperature sensor and a heat source image sensor using the same.

According to an embodiment of the present invention, a thermoelectric device includes a first nanowire and a second nanowire disposed on a substrate and spaced apart from each other, a first silicon thin film connected to one end of the first nanowire, and one end of the second nanowire. And a second silicon thin film connected to the second silicon thin film and a third silicon thin film connected to the other end of the first nanowire and the second end of the second nanowire, wherein the first nanowire and the second nanowire are formed on an upper portion of the substrate. It extends in a direction horizontal to the plane.

The silicon thin films and the nanowires according to the exemplary embodiment of the present invention may be provided on the same plane.

The silicon thin films and the nanowires according to the exemplary embodiment of the present invention may have the same thickness.

The thermoelectric device according to the embodiment of the present invention may further include first, second and third metal thin films electrically connected to the silicon thin films, and an absorber electrically connected to the third metal thin film.

The absorber according to the embodiment of the present invention may absorb heat and transfer the heat to the third silicon thin film through the third metal thin film.

The first and second nanowires according to the embodiment of the present invention may include silicon.

The first nanowire according to an embodiment of the present invention may include an N-type dopant, and the second nanowire may include an etched dopant.

According to an embodiment of the present invention, the thermoelectric device may further include a doped region in each of the first silicon thin film, the second silicon thin film, and the third silicon thin film, wherein the doped regions may be connected to the metal thin films. Ohmic contacts can be formed.

The metal thin films according to the embodiment of the present invention may include the same material.

The metal thin films according to the embodiment of the present invention may include at least one of copper (Cu), aluminum (Al), titanium (Ti), cobalt (Co), titanium nitride (TiN), or tungsten (W). .

The thermoelectric device according to the embodiment of the present invention may further include an insulating film provided on the substrate, and the first, second, third silicon thin films and the first and second nanowires may be disposed on the insulating film. .

Temperature sensor according to an embodiment of the present invention is a thermoelectric element for converting the thermal energy of the heat source into electrical energy, a central processing unit for comparing the electrical energy with the temperature value of the heat source, and stores the data calculated in the central processing unit It may include a data storage for exchanging data with the central processing unit.

A heat source image sensor according to an exemplary embodiment of the present invention may include a plurality of unit pixels each including an AND logic circuit, a switching element turned on by the AND logic circuit, and a thermoelectric element electrically connected to the switching element, A row multiplexer and a column multiplexer, wherein the plurality of unit pixels are selected and electrically connected to the AND logic circuit, current amplifiers amplifying electrical energy of the thermoelectric element through the turned-on switching element, and by the current amplifiers And a display for receiving an amplified signal and outputting an image.

In the method of forming a thermoelectric element according to an exemplary embodiment of the present invention, an insulating film and a silicon layer are sequentially formed on a substrate, a photoresist pattern having a first line width is formed on the silicon layer, and an ashing process is performed on the photoresist pattern. Proceeding to form a photoresist fine pattern having a second line width narrower than the first line width, and performing an etching process on the silicon layer using the photoresist fine pattern as a mask to form first and second nanowires. It includes forming a.

Forming the first and second nanowires according to an embodiment of the present invention forms a first silicon thin film connected to one end of the first nanowire, and second silicon connected to one end of the second nanowire. The method may include forming a thin film, and forming a third silicon thin film connected to the other end of the first nanowire and the other end of the second nanowire.

The method of forming a thermoelectric device according to an exemplary embodiment of the present invention may include doping an en-type dopant on the first nanowire and doping a dopant on the second nanowire.

According to an embodiment of the invention, the nanowires extend in a horizontal direction with respect to the substrate. This is because nanowires are formed by a semiconductor process (CMOS process). Instead of being formed separately in the furnace, it is formed using a photolithography process and an ashing process, so that the process time for forming the nanowires is reduced and mass production may be possible. In addition, the uniformity of the nanowires is secured, and thus the performance of the thermoelectric device may be improved.

1 is a schematic diagram illustrating a thermoelectric device according to an exemplary embodiment of the present invention.
2 to 3b are views for explaining a thermoelectric device according to an embodiment of the present invention in detail. 3A is a cross-sectional view taken along the line II ′ of FIG. 2, and FIG. 3B is a cross-sectional view taken along the line II-II ′ of FIG. 2.
4 is a conceptual diagram illustrating a temperature sensor according to an embodiment of the present invention.
5 is a circuit diagram illustrating a basic operation principle of a heat source image sensor according to an exemplary embodiment of the present invention.
6A to 7C are diagrams for describing a method of forming a thermoelectric device according to an exemplary embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, and advantages of the present invention will become more readily apparent from the following description of preferred embodiments with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In this specification, when an element is referred to as being on another element, it may be directly formed on another element, or a third element may be interposed therebetween. Further, in the drawings, the thickness of the components is exaggerated for an effective description of the technical content. The same reference numerals denote the same elements throughout the specification.

Embodiments described herein will be described with reference to cross-sectional views and / or plan views that are ideal illustrations of the present invention. In the drawings, the thicknesses of films and regions are exaggerated for effective explanation of technical content. Thus, the shape of the illustrations may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in the shapes that are generated according to the manufacturing process. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention. Although terms such as first, second, third, and the like are used to describe various components in various embodiments of the present specification, these components should not be limited by such terms. These terms have only been used to distinguish one component from another. The embodiments described and exemplified herein also include their complementary embodiments.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. The terms "comprises" and / or "comprising" used in the specification do not exclude the presence or addition of one or more other elements.

1 is a schematic diagram illustrating a thermoelectric device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, an insulating film 110 is disposed on a substrate 100. The substrate 100 may be a silicon substrate or a silicon on insulator (SOI) substrate. The insulating layer 110 may be a silicon oxide layer provided on the substrate 100. Alternatively, the insulating layer 110 may be a buried oxide of a silicon on insulator (SOI) substrate. The first nanowire 132 and the second nanowire 134 are disposed on the insulating layer 110 to be spaced apart from each other. The first nanowire 132 and the second nanowire 134 extend in a horizontal direction with respect to the upper surface of the insulating film 110.

A first silicon thin film 122 connected to one end of the first nanowire 132 is disposed, and a second silicon thin film 124 connected to one end of the second nano wire 134 is disposed. The third silicon thin film 126 is connected to the other ends of the first and second nanowires 132 and 134. The first nanowire 132 may include an n-type dopant, and the second nanowire 134 may include a doped dopant.

The first silicon thin film 122 may include an N-type dopant, and the second silicon thin film 124 may include a doped dopant. The third silicon thin films 126 may include a p-type or en-type dopant. Specifically, the third silicon thin film 126 adjacent to the first nanowire 132 may include an N-type dopant, and the third silicon thin film 126 adjacent to the second nanowire 134 may have a doped dopant. It may include.

The third silicon thin film 126 is exposed to a heat source to increase the temperature, and thus, between the third silicon thin film 126 and the first silicon thin film 122 and between the third silicon thin film 126 and the second silicon thin film ( The current can be induced by the temperature difference between 124). That is, due to the temperature difference, electrons e move from the third silicon thin film 126 toward the first silicon thin film 122 through the first nanowire 132, and the hole h is the second nano. A clockwise current flow may be formed by moving from the third silicon thin film 126 toward the first silicon thin film 122 through the wire 134.

2 to 3b are views for explaining a thermoelectric device according to an embodiment of the present invention in detail. 3A is a cross-sectional view taken along the line II ′ of FIG. 2, and FIG. 3B is a cross-sectional view taken along the line II-II ′ of FIG. 2.

2 to 3B, an insulating film 110 is provided on the substrate 100 including n and p regions. The substrate 100 may be a semiconductor substrate or a SOI substrate. The insulating layer 110 may include a silicon oxide layer. The insulating layer 110 may be a buried oxide of a SOI substrate. The first nanowire 132 is disposed on the insulating layer 110 in the n region. The second nanowire 134 spaced apart from the first nanowire 132 is disposed on the insulating layer 110 in the p region.

A first silicon thin film 122 connected to one end of the first nanowire 132 is disposed on the insulating layer 110. A second silicon thin film 124 connected to one end of the second nanowire 134 is disposed on the insulating layer 110. A third silicon thin film 126 connected to the other ends of the first and second nano wires 132 and 134 is disposed on the insulating layer 110. The first and second nanowires 132 and 134 extend in a horizontal direction with respect to the upper surface of the substrate 100 or the insulating film 110.

The first and second nanowires 132 and 134 may include silicon. The first nanowire 132 may include an N-type dopant, and the second nanowire 134 may include an etched dopant. The silicon thin films 122, 124, and 126 and the nanowires 132 and 134 may be provided in the same plane. In addition, the silicon thin films 122, 124, and 126 and the nanowires 132 and 134 may have the same thickness.

The first silicon thin film 122 includes a first doped region 123, the second silicon thin film 124 includes a second doped region 125, and the third silicon thin film 126 is formed of a first doped region 123. Three doped regions 127. Each of the first, second and third doped regions 123, 125, and 127 may include a dopant. The first doped region 123 may have the same conductivity type as the first silicon thin film 122, and the second doped region 125 may have the same conductivity type as the second silicon thin film 124. The first silicon thin film 122 and the first doped region 123 may have an N-type dopant. The second silicon thin film 124 and the second doped region 125 may have a doped dopant. The third doped region may include an n-type doped region 127n provided in the n region and a typed doped region 127p provided in the p region. The third silicon thin film 126 disposed in the n region may have an N-type dopant, and the third silicon thin film 126 disposed in the p region may have a doped dopant.

The first interlayer insulating layer 140 covering the silicon thin films 122, 124, and 126 and the nanowires 132 and 134 is disposed. The first interlayer insulating layer 140 may include a silicon oxide layer. First, second and third metal contacts 142, 144, and 146 connected to the first interlayer insulating layer 140 and the first, second and third silicon thin films 122, 124, and 126, respectively. ) Is placed. Unlike the illustrated in FIG. 2, the third metal contact 146 may be separated into an N-type metal contact provided in the n-region and a to-be-shaped metal contact provided in the p-region.

A second interlayer insulating layer 150 is disposed on the first interlayer insulating layer 140. The second interlayer insulating layer 150 may include the same material as the first interlayer insulating layer 140. The first metal thin film 152, the second metal thin film 154, and the third metal thin film 156 electrically connected to the first, second and third metal contacts 142, 144, and 146, respectively, The second interlayer insulating layer 150 is disposed. The first, second and third metal thin films 152, 154 and 156 may include the same material. The first, second and third metal thin films 152, 154, and 156 may include copper (Cu), aluminum (Al), titanium (Ti), cobalt (Co), titanium nitride (TiN), or tungsten (W). It may include at least one of. The first, second and third metal thin films 152, 154, and 156 may include the same material as the first, second and third metal contacts 142, 144, and 146.

A third interlayer insulating layer 160 is disposed on the second interlayer insulating layer 150 and the metal thin films 152, 154, and 156. The third interlayer insulating layer 160 may include the same material as the second interlayer insulating layer 150. A contact 162 in contact with the third metal thin film 156 is disposed on the third interlayer insulating layer 160. An absorber 170 connected to the contact 162 is disposed on the third interlayer insulating layer 160. The absorber 170 may serve to absorb external heat. The absorber 170 may include a titanium oxide film. The contact 162 may include the same material as the absorber 170. The absorber 170 transfers heat to the third silicon thin film 126, thereby between the third silicon thin film 126 and the first silicon thin film 122 and between the third silicon thin film 126 and the second silicon. A temperature difference may be formed between the thin films 124.

4 is a conceptual diagram illustrating a temperature sensor according to an embodiment of the present invention.

Referring to FIG. 4, the temperature sensor 200 includes a thermoelectric element 220 that absorbs thermal energy of the heat source 210 and converts the thermal energy into electrical energy. The thermoelectric element 220 includes the components described with reference to FIGS. 2 to 3b. The central processing unit 230 calculates the electric energy value converted by the heat source 210 and the thermoelectric element 220. The central processor 230 stores the relationship between the temperature of the heat source 210 and the electric energy value in the data storage 240. The temperature sensor 200 may include a display unit 250 that displays a temperature according to the temperature of the heat source 210. According to an embodiment of the present invention, the temperature sensor 200 may detect the temperature of the heat source 210 using the silicon nanowires.

5 is a circuit diagram illustrating a basic operation principle of a heat source image sensor according to an exemplary embodiment of the present invention.

Referring to FIG. 5, the heat source image sensor 300 may include unit pixels including the thermoelectric element 310, the AND logic circuit 320, and the switching element 330 described with reference to FIGS. 2 to 3B. Include. The switching element 330 may be turned on by the AND logic circuit 320. A row multiplexer 340 and a column multiplexer 350 are selected to select the plurality of unit pixels and are electrically connected to the AND logic circuit 320. Thermal energy corresponding to the position of the thermoelectric element 310 is converted into electrical energy by the thermoelectric element 310 of the selected unit pixels. When the switching element 330 of the selected unit pixels is turned on, the electric energy converted by the thermoelectric element 310 is output. The output electrical energy is amplified by a low noise current amplifier 360 and then converted into a voltage value. The converted voltage value may be implemented as an image by the display 370.

6A to 7C are diagrams for describing a method of forming a thermoelectric device according to an exemplary embodiment of the present invention. 6A to 6F are diagrams for describing a method of forming nanowires, and show a pair of nanowires for convenience of illustration.

Referring to FIG. 6A, an insulating film 410 is formed on the substrate 400. It may be formed of the insulating film 410. The silicon layer 430 is formed on the insulating layer 410. Alternatively, the substrate 400, the insulating layer 410, and the silicon layer 430 may be prepared by a silicon on insulator (SOI) substrate. The silicon layer 430 has a thickness of several tens of nm, for example, 40 nm. Thinning the silicon layer 430 may include repeating a thermal oxidation process and an oxide film removing process. The oxide film removing process may include a wet etching process.

Referring to FIG. 6B, a photoresist pattern 420 is formed on the silicon layer 430. The first minimum line width W1 of the photoresist pattern 420 may be 180 nm. The photoresist pattern 420 may be formed by a stepper using a KrF excimer laser. The photoresist pattern 420 is etched using a mask to form a first preliminary silicon thin film 422a, a second preliminary silicon thin film 424a, a third preliminary silicon thin film 426a, and a first preliminary nanowire 432a. ) And the second preliminary nanowire 434a may be formed.

Referring to FIG. 6C, an ashing process is performed on the photoresist pattern 420 so that the photoresist fine pattern 425 having a second minimum line width W2 that is narrower than the first minimum line width W1. Is formed. The second minimum line width W2 may be formed to about 30 nm. The ashing process may be an oxygen plasma ashing process.

Referring to FIG. 6D, the first preliminary silicon thin film 422a, the second preliminary silicon thin film 424a, the third preliminary silicon thin film 426a, and the first preliminary nanowire using the photoresist fine pattern 425 as a mask. An etching process is performed on the 432a and the second preliminary nanowires 434a to form the first silicon thin film 422, the second silicon thin film 424, the third silicon thin film 426, and the first nano wire 432. And a second nanowire 434 is formed. The first nanowire 432 and the second nanowire 434 may have a line width of about 30 nm. The first and second nanowires 432 and 434 extend in a horizontal direction with respect to the upper surface of the substrate 400.

The silicon thin films 422, 424, and 426 and the nanowires 432 and 434 may be formed on substantially the same plane. This is because they are simultaneously formed by one photoresist fine pattern 425. In addition, the silicon thin films 422, 424, and 426 and the nanowires 432 and 434 may have the same thickness.

6E and 6F show Scanning Electron Microscope (SEM) photographs of the first and second nanowires 432 and 434 before and after the ashing process, respectively. In FIG. 6E, the line width of the nanowires is 160.9 nm, whereas in FIG. 6F after the ashing process, the line widths of the nanowires are 31.1 nm.

7A to 7C are diagrams illustrating a process after the first and second nanowires 432 and 434 are formed, and each of the first and second nanowires 432 and 434 is shown in plural.

Referring to FIG. 7A, an N-type dopant is doped into the first nanowire 432. By doping the N-type dopant, the substrate 400 may include n regions. A portion of the third silicon thin film 426 adjacent to the first silicon thin film 422 and the first nanowire 432 may be provided in the n region. The doped dopant is doped in the second nanowire 434. By doping the dopant, the substrate 400 may include a p region. In the p region, a portion of the third silicon thin film 426 adjacent to the second silicon thin film 424 and the second nanowire 434 may be provided.

Referring to FIG. 7B, a first doped region 423 is formed in the first silicon thin film 422 for ohmic contact, and a second doping is formed in the second silicon thin film 424 for ohmic contact. Region 425 is formed. The first doped region 423 includes an n-type dopant and the second doped region 425 includes an doped dopant. A third doped region 427n for ohmic contact is formed in the N-type region of the third silicon thin film 426, and a fourth doped region 427p for ohmic contact is formed in the to-be-shaped region of the third silicon thin film 426. Is formed. The third doped region 427n includes an N-type dopant, and the fourth doped region 427p includes an doped dopant. Here, ohmic contact refers to reducing resistance between the silicon thin film and the metal contact or metal thin film to be described below.

Referring to FIG. 7C, a first interlayer insulating layer 440 is formed to cover the silicon thin films 422, 424, and 426 and the nanowires 432 and 434. The first interlayer insulating film 440 may be formed of a silicon oxide film. In the first interlayer insulating layer 440, a first metal contact 442 is formed to contact the first doped region 423, and a second metal contact 444 is in contact with the second doped region 425. Is formed, and a third metal contact 446 is formed in contact with the third doped region 427n and the fourth doped region 427p. Unlike the example illustrated in FIG. 7C, the third metal contact 446 may be divided into a metal contact in contact with the third doped region 427n and a metal contact in contact with the fourth doped region 427p. have.

A second interlayer insulating layer 450 is formed on the first interlayer insulating layer 440. The second interlayer insulating film 450 may be formed of the same material as the first interlayer insulating film 440, for example, a silicon oxide film. A first metal thin film 452 in contact with the first metal contact 442, a second metal thin film 454 in contact with the second metal contact 444, and the second interlayer insulating layer 450. A third metal thin film 456 is formed in contact with the three metal contacts 446. The first, second and third metal thin films 452, 454, and 456 may be formed of the same material. The first, second and third metal thin films 452, 454, and 456 may be formed of the same material as the first, second and third metal contacts 442, 444, and 446. The first, second and third metal thin films 452, 454, and 456 may be formed of, for example, copper (Cu), aluminum (Al), titanium (Ti), cobalt (Co), titanium nitride (TiN), or It may be formed of at least one of tungsten (W).

A third interlayer insulating layer 460 is formed on the second interlayer insulating layer 450. The third interlayer insulating film 460 may be formed of, for example, a silicon oxide film. A contact 462 in contact with the third metal thin film 456 is formed on the third interlayer insulating layer 460. An absorber 470 connected to the contact 462 is formed on the third interlayer insulating layer 460. The absorber 470 may be formed of a titanium oxide film. The contact 462 may be formed of the same material as the absorber 470.

According to an embodiment of the present invention, the first nanowire 432 and the second nanowire 434 are formed by a photolithography process and an ashing process. That is, the first nanowire 432 and the second nanowire 434 are not formed separately in the furnace but are formed using a semiconductor process (CMOS process). Thus, the process time for forming the nanowires is reduced, and mass production may be possible. In addition, the uniformity of the nanowires is secured, and thus the performance of the thermoelectric device may be improved. The central processing unit 230, the data storage unit 240, the AND logic circuit 320, the switching element 330, the low multiplexer 340, the column multiplexer 350, and the low noise current amplifier 360 described in FIG. 4 are CMOS. Device, and may be formed by the above-described CMOS process.

132: first nanowire 134: second nanowire
122: first silicon thin film 124: second silicon thin film
126: third silicon thin film 152: first metal thin film
154: second metal thin film 156: third metal thin film
170: absorber

Claims (16)

First and second nanowires spaced apart from each other on the substrate;
A first silicon thin film connected to one end of the first nanowire;
A second silicon thin film connected to one end of the second nanowire; And
A third silicon thin film connected to the other end of the first nanowire and the other end of the second nanowire,
The first nanowire and the second nanowire extend in a horizontal direction with respect to an upper surface of the substrate;
And the silicon thin films and the nanowires are provided in the same plane. delete The method according to claim 1,
And the silicon thin films and the nanowires have the same thickness. The method according to claim 1,
First, second and third metal thin films electrically connected to the silicon thin films, respectively; And
The thermoelectric device further comprises an absorber electrically connected to the third metal thin film. The method of claim 4,
The absorber absorbs heat and transfers the heat to the third silicon thin film through the third metal thin film. The method of claim 4,
The first and second nanowires comprise silicon. The method of claim 6,
Wherein the first nanowire comprises an N-type dopant, and the second nanowire comprises a doped dopant. The method of claim 4,
Each of the first silicon thin film, the second silicon thin film, and the third silicon thin film may further include a doped region, wherein the doped region may form an ohmic contact with contacts connected to the first, second and third metal thin films. Forming a thermoelectric element. The method of claim 4,
And the first, second and third metal thin films comprise the same material. The method of claim 9,
The first, second and third metal thin films may include at least one of copper (Cu), aluminum (Al), titanium (Ti), cobalt (Co), titanium nitride (TiN), or tungsten (W). device. The method according to claim 1,
Further comprising an insulating film provided on the substrate,
And the silicon thin films and the nano wires are disposed on the insulating layer. A thermoelectric element of claim 1 for converting thermal energy of a heat source into electrical energy;
A central processing unit for comparing the electrical energy with a temperature value of the heat source; And
And a data storage unit for storing data calculated by the central processing unit and exchanging data with the central processing unit. A plurality of unit pixels each including an AND logic circuit, a switching element turned on by the AND logic circuit, and a thermoelectric element of claim 1 electrically connected to the switching element;
A row multiplexer and a column multiplexer for selecting the plurality of unit pixels and electrically connected to the AND logic circuit;
Current amplifiers for amplifying electrical energy of the thermoelectric element through the turned-on switching element; And
And a display configured to receive a signal amplified by the current amplifiers and to output an image. Sequentially forming an insulating film and a silicon layer on the substrate;
Forming a photoresist pattern having a first line width on the silicon layer;
Performing an ashing process on the photoresist pattern to form a photoresist fine pattern having a second line width narrower than the first line width; And
And etching the silicon layer using the photoresist fine pattern as a mask to form first and second nanowires. The method according to claim 14,
Forming the first and second nanowires is:
Forming a first silicon thin film connected to one end of the first nanowire, forming a second silicon thin film connected to one end of the second nanowire, and forming another second thin film of the first nanowire and a second end of the second nanowire. A method of forming a thermoelectric element comprising forming a third silicon thin film connected to the other end. 16. The method of claim 15,
Doping an N-type dopant to the first nanowire; And
And forming a dopant to the second nanowire.

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