KR101351377B1 - A shift register - Google Patents

Abstract

The present invention relates to a shift register capable of preventing deterioration of a multi-output and a switching element, comprising a plurality of stages for sequentially outputting scan pulses through an output terminal; Each stage includes: a node controller for controlling charge and discharge states of the set node and the reset node; A pull-up switching element controlled by a signal supplied to the set node and connected to the scan clock transmission line for transmitting a scan clock pulse and the output terminal; A pull-down switching element controlled by a control signal from the outside and connected between a discharge power supply line for transmitting the discharge voltage source and the output terminal; And periodically reset and discharge the reset node during the non-output period of the stage, and before the reset node is supplied with an active scan clock pulse to the pull-up switching element during the non-output period. And a coupling remover for filling.

LCD, shift register, coupling phenomenon, multi output

Description

A shift register

1 shows one stage in a conventional shift register.

2 is a view illustrating a shift register according to an embodiment of the present invention.

FIG. 3 is a timing chart of various signals supplied to or output from each stage of FIG. 2; FIG.

4 is a diagram illustrating a circuit configuration of a first stage of FIG. 2.

FIG. 5 shows another circuit configuration of the first stage shown in FIG.

FIG. 6 is a view showing another circuit configuration of the first stage shown in FIG.

FIG. 7 illustrates another circuit configuration of the first stage shown in FIG. 2.

FIG. 8 shows another circuit configuration of the first stage shown in FIG.

FIG. 9 illustrates another circuit configuration of the first stage shown in FIG. 2.

* Explanation of symbols on the main parts of the drawings

Vout: Scan pulse VDD: Voltage source for charging

VSS: Voltage source for discharge Vst: Start pulse

Trpu: Pull-up Switching Device Trpd: Pull-down Switching Device

ST: Stage CLK: Clock Pulse

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register of a liquid crystal display, and more particularly, to a shift register capable of preventing multiple outputs due to coupling phenomenon and preventing deterioration of a switching element.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, a liquid crystal display device includes a liquid crystal panel in which pixel regions are arranged in a matrix form, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged in an intersecting manner, and a pixel region is located in an area defined by vertically intersecting the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed on the liquid crystal panel.

Here, the gate lines are sequentially driven by a scan pulse, which is generated by a shift register.

1 is a diagram illustrating one stage in a conventional shift register.

The conventional stage includes a node control unit 101 for controlling the charging and discharging states of the set node Q and the reset node QB, and a scan pulse Vout in accordance with the signal state of the set node Q. ) And a pull-down switching device Trpd for outputting a discharge voltage source VSS in accordance with the signal state of the reset node QB.

Here, the set node Q and the reset node QB are alternately charged and discharged. Specifically, when the set node Q is in a charged state, the reset node QB is charged. Is maintained in a discharged state, and when the reset node QB is in a charged state, the set node Q is maintained in a discharged state.

At this time, when the set node Q is in a charged state, a scan pulse Vout is output from the pull-up switching device Trpu, and when the reset node QB is in a charged state, pull-down switching of the output unit is performed. The discharge voltage source VSS is output from the element Trpd.

The scan pulse Vout output from the pull-up switching device Trpu and the discharge voltage source VSS output from the pull-down switching device Trpd are supplied to the corresponding gate line.

Here, the gate terminal of the pull-up switching element Trpu is connected to the set node Q, the drain terminal is connected to the clock transmission line to which the clock pulse CLK is applied, and the source terminal is connected to the gate line. do. The clock pulse CLK has a high state and a low state periodically and is supplied to the drain terminal of the pull-up switching device Trpu. In this case, the pull-up switching device Trpu outputs any one of the clock pulses CLK in the high state input every cycle. The clock pulse CLK output at this particular time point is the scan pulse Vout for driving the gate line.

This specific time point means a time point after the set node Q is charged. That is, the pull-up switching device Trpu is at the specific time point (that is, the time point when the set node Q is charged) among the clock pulses CLK which are continuously input to its drain terminal periodically. The input high clock pulse CLK is output as a scan pulse Vout. After the output of the scan pulse Vout, the set node Q is maintained in the discharge state until the next frame period starts, so that the pull-up switching device Trpu has one scan pulse Vout per frame. ) Will be printed. However, since the clock pulse CLK is output several times in one frame period, the clock pulse even when the pull-up switching device Trpu is turned off, that is, even when the set node Q is discharged. CLK is continuously input to the drain terminal of the pull-up switching element Trpu.

In other words, the pull-up switching device Trpu is turned on only once for one frame, and outputs the clock pulse CLK input to its drain terminal as a scan pulse Vout during this turn-on period. .

Thereafter, the pull-up switching device Trpu is turned off until the start of the next frame period, so that the pull-up switching device Trpu is clock pulse CLK at its drain terminal no matter how long it is turned off. Is input, it cannot be output as a scan pulse (Vout). However, as the clock pulse CLK is periodically applied to the drain terminal of the pull-up switching device Trpu, the set node Q and the pull-up connected to the gate terminal of the pull-up switching device Trpu are connected. Coupling occurs between the drain terminals of the switching element Trpu. Due to such a coupling phenomenon, the set node Q is continuously charged with a predetermined voltage corresponding to the clock pulse CLK.

Then, the set node Q may be kept in a charged state at any moment. That is, the set node Q may be kept in a charged state at an unwanted timing. In this case, the set node Q may be maintained in the charging state more than once in one frame period, whereby the pull-up switching device Trpu may be turned on more than once in one frame period. As a result, a multi-output phenomenon in which one stage outputs two or more scan pulses Vout in one frame period may occur due to the coupling phenomenon as described above.

As such, when one stage outputs two or more scan pulses Vout during one frame period, the quality of an image displayed on the liquid crystal panel is degraded.

The present invention has been made to solve the above problems, and to provide a shift register that can prevent the deterioration of the switching element by periodically charging and discharging the reset node, and prevents multiple outputs. There is this.

The shift register according to the present invention for achieving the above object includes a plurality of stages for sequentially outputting the scan pulse through the output terminal; Each stage includes: a node controller for controlling charge and discharge states of the set node and the reset node; A pull-up switching element controlled by a signal supplied to the set node and connected to the scan clock transmission line for transmitting a scan clock pulse and the output terminal; A pull-down switching element controlled by a control signal from the outside and connected between a discharge power supply line for transmitting the discharge voltage source and the output terminal; And periodically charging and discharging the reset node during the non-output period of the stage, and before the reset node is supplied with an active scan clock pulse to the pull-up switching device during the non-output period. And a coupling remover for filling.

Hereinafter, a shift register according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a diagram illustrating a shift register according to an embodiment of the present invention, and FIG. 3 is a timing chart of various signals supplied to or outputted from each stage of FIG.

The shift register according to the embodiment of the present invention includes n stages ST1 to STn and one dummy stage STn + 1 as shown in FIG. 2. Here, each of the stages ST1 to STn outputs one scan pulse Vout1 to Voutn + 1 for one frame period, in which case the scan pulses are sequentially sequentially from the first stage ST1 to the dummy stage STn + 1. Outputs

Here, the scan pulses Vout1 to Voutn output from the stages ST1 to STn except for the dummy stage STn + 1 are sequentially supplied to the gate lines of the liquid crystal panel (not shown) The gate lines are sequentially scanned.

That is, first, the first stage ST1 outputs the first scan pulse Vout1, the second stage ST2 outputs the second scan pulse Vout2, and then the third stage ST3, The third scan pulse Vout3 is output, and finally the nth scan stage STn outputs the nth scan pulse Voutn.

Meanwhile, after the n-th stage STn outputs the n-th scan pulse Voutn, the dummy stage STn + 1 outputs the n + 1-th scan pulse Voutn + 1, wherein the dummy stage The nth + 1th scan pulse Voutn + 1 output from (STn + 1) is not supplied to the gate line but is supplied only to the nth stage STn.

Such a shift register is built in the liquid crystal panel. That is, the liquid crystal panel has a display portion for displaying an image and a non-display portion surrounding the display portion. The shift register is embedded in the non-display portion.

The entire stages ST1 to STn + 1 of the shift register configured as described above are charged voltage sources VDD, discharge voltage sources VSS, and the first and second clock pulses CLK1 and CLK2 circulating with sequential phase differences. ) Is authorized.

The charging voltage source VDD and the discharging voltage source VSS are all DC voltage sources, the charging voltage source VDD is positive and the discharging voltage source VSS is negative. Meanwhile, the discharging voltage source VSS may be a ground voltage.

As shown in FIG. 3, the first and second clock pulses CLK1 and CLK2 are output with phase differences from each other. That is, the second clock pulse CLK2 is phase-delayed by one pulse width than the first clock pulse CLK1 and output. Here, the first clock pulse CLK1 and the second clock pulse CLK2 are phase-inverted with respect to each other. Accordingly, the second clock pulse CLK2 indicates a low state when the first clock pulse CLK1 is high and the second clock pulse CLK2 when the first clock pulse CLK1 is low. Indicates a high state.

The first and second clock pulses CLK1 and CLK2 are sequentially output, and are also output while being circulated. That is, the signals are sequentially output from the first clock pulse CLK1 to the second clock pulse CLK2, and sequentially output from the first clock pulse CLK1 to the second clock pulse CLK2.

As shown in FIG. 3, the length of the active period of the first clock pulse CLK1 and the length of the active period of the second clock pulse CLK2 are the same. The length of the inactive period of the first clock pulse CLK1 and the length of the inactive period of the second clock pulse CLK2 are the same. The inactive period of the first clock pulse CLK1 is longer than the active period, and the inactive period of the second clock pulse CLK2 is longer than the active period. The first clock pulse CLK1 is kept in an active state within the inactive period of the second clock pulse CLK2. The second clock pulse CLK2 is maintained in an active state within the inactive period of the first clock pulse CLK1.

According to the circuit configuration of the stage, the number of clock pulses supplied to one stage may vary.

The first stage ST1 located at the uppermost one of the stages ST1 to STn + 1 is connected to the charging voltage source VDD, the discharging voltage source VSS, and the first and second clock pulses CLK1 , And CLK2, as well as a start pulse Vst.

Each of the clock pulses CLK1 and CLK2 is outputted several times during one frame period, but the start pulse Vst is outputted only once during one frame period.

In other words, each clock pulse CLK1 and CLK2 periodically shows several active states (high states) during one frame period, but the start pulse Vst shows only one active state during one frame period.

In this case, the second clock pulse CLK2 and the start pulse Vst may be output in synchronization with each other. At this time, the second clock pulse CLK2 of the first and second clock pulses CLK1 and CLK2 is output first.

In order for each of the stages ST1 to STn + 1 to output the scan pulse, the enable operation of each stage ST1 to STn + 1 must be preceded. The fact that the stage is enabled means that the stage is set in a state in which it can output, that is, a state in which a clock pulse supplied thereto can be outputted as a scan pulse. To this end, each stage ST1 to STn + 1 is enabled by receiving a scan pulse from the stage located at the previous stage from the stage ST1 to STn + 1.

For example, the k < th > stage is enabled in response to a scan pulse from the (k-1) th stage.

Since the stage does not exist in front of the first stage ST1 positioned at the uppermost side, the first stage ST1 is enabled in response to the start pulse Vst from the timing controller.

In addition, each stage ST1 to STn + 1 is disabled in response to a scan pulse from the next stage. Disabling the stage means that the stage is reset to a state in which output is not possible, i.e., a state in which a clock pulse supplied to the stage can not be outputted as a scan pulse.

For example, the kth stage is disabled in response to the scan pulse from the k + 1th stage.

The odd-numbered stages of each stage, that is, the 2k-1 stage, use the first clock pulse CLK1 as a scan pulse and control the second clock pulse CLK2 for its reset node QB. use. In other words, the first clock pulse CLK1 supplied to the odd stages is a scan clock pulse, and the second clock pulse CLK2 is a control clock pulse.

The even-most stages of each stage, that is, the second k stage, use the second clock pulse CLK2 as a scan pulse, and use the first clock pulse CLK1 to control its reset node QB. . In other words, the second clock pulse CLK2 supplied to the even-numbered stages is a scan clock pulse, and the first clock pulse CLK1 is a control clock pulse.

The structure of each stage ST1 to STn + 2 in the shift register constructed as described above will be described in more detail as follows.

Since the configurations of the stages ST1 to STn + 2 are the same, only the first stage ST1 will be described as an example.

4 is a diagram illustrating a circuit configuration of the first stage of FIG. 2.

Each stage ST1 to STn + 1 includes a set node Q, a reset node QB, a pull-up switching element Trpu, and a pull-down switching element Trpd, as shown in FIG. And a coupling remover CR including the first to third switching elements Tr1 to Tr3, and a node controller including the fourth to seventh switching elements Tr4 to Tr7.

The pull-up switching element Trpui is controlled by a signal supplied to the set node Q, and is connected to a scan clock transmission line for transmitting scan clock pulses and an output terminal of the stage. The output terminal of each stage ST1 to STn + 1 is connected to the corresponding gate line.

The pull-down switching element Trpd is controlled by a signal supplied to the reset node QB, and is connected between the discharge power line for transmitting the discharge voltage source VSS and the output terminal.

The coupling remover CR periodically charges and discharges the reset node QB during the non-output period of the stage, and scans the active state to the pull-up switching device Trpu during the non-output period. The reset node QB is charged before the clock pulse is supplied.

Each stage ST1 to STn + 1 has a set period, an output period, and a non-output period. Each stage ST1 to STn + 1 is enabled in the set period, and then outputs the scan clock pulse supplied to it in the output period as a scan pulse, and then does not output the scan pulse in the non-output period. That is, each stage ST1 to STn + 1 outputs a discharge voltage source in this non-output period.

Each stage ST1 to STn + 1 maintains its set node Q in a charged state during the set period and the output period, and maintains the reset node QB in a discharged state. The set node Q is kept in a discharged state during the non-output period, and the reset node QB is periodically changed to a charged and discharged state.

In the non-output period, a scan pulse is supplied to the pull-up switching elements Trpu of each of the stages ST1 to STn + 1, and the coupling removing unit CR provided to each of the stages ST1 to STn + 1 is provided. During the non-output period, the stage outputs a scan pulse in the non-output period by charging the reset node QB before the pull-up switching element Trpu is supplied with an active scan clock pulse. prevent.

In the first stage ST1 illustrated in FIG. 4, first and second clock pulses CLK1 and CLK2 are supplied, wherein the first clock pulse CLK1 is the aforementioned clock pulse for scanning and the second clock. The pulse CLK2 is the control clock pulse described above.

The first switching element Tr1 is controlled by a signal supplied to the set node Q, and is connected between the discharge power supply line and the common node N. That is, the gate terminal of the first switching element is connected to the set node Q, the drain terminal is connected to the common node N, and the source terminal is connected to the discharge power supply line.

The second switching element Tr2 is controlled by the charging voltage source VDD from the charging power line, and is connected between the charging power line and the common node N. That is, the gate terminal and the drain terminal of the second switching element Tr2 are connected to the set node Q, and the source terminal is connected to the common node N. As such, since the charging voltage source VDD, which is a constant voltage source, is supplied to the gate terminal and the drain terminal of the second switching element Tr2, the second switching element Tr2 is always turned on.

The third switching element Tr3 is controlled by the first clock pulse CLK1 from the first clock transmission line and is connected between the common node N and the discharge power supply line. That is, the gate terminal of the third switching element Tr3 is connected to the first clock transmission line, the drain terminal is connected to the common node N, and the source terminal is connected to the discharge power supply line.

The fourth switching element Tr4 is controlled by the start pulse Vst or the scan pulse from the front stage, and is connected between the charging power supply line and the set node Q. That is, the gate terminal of the fourth switching device Tr4 is connected to the start transmission line for transmitting the start pulse Vst or the output terminal of the front stage. The drain terminal of the fourth switching element Tr4 is connected to the charging power supply line, and the source terminal is connected to the set node Q.

For example, the fourth switching device Tr4 provided in the first stage ST1 is controlled by the start pulse Vst, and the fourth switching device Tr4 provided in the second stage ST2 is the first switching device Tr4. It is controlled by the first scan pulse Vout1 from one stage ST1.

The fifth switching element Tr5 is controlled by a signal supplied to the reset node Q and is connected between the set node Q and the discharge power line. That is, the gate terminal of the fifth switching element Tr5 is connected to the reset node Q, the drain terminal is connected to the discharge power line, and the source terminal is connected to the set node Q. do.

The sixth switching element Tr6 is controlled by the scan pulse from the next stage and is connected between the set node Q and the discharge power line. That is, the gate terminal of the sixth switching element Tr6 is connected to the output terminal of the next stage stage, the drain terminal is connected to the set node Q, and the source terminal is connected to the discharge power supply line. .

The seventh switching element Tr7 is controlled by the start pulse Vst or the scan pulse from the preceding stage, and is connected between the reset node Q and the discharge power line. That is, the gate terminal of the seventh switching element Tr7 is connected to the start transmission line for transmitting the start pulse Vst or the output terminal of the preceding stage. The drain terminal of the seventh switching element Tr7 is connected to the common node N, and the source terminal is connected to the power supply line for discharge.

For example, the seventh switching device Tr7 provided in the first stage ST1 is controlled by the start pulse Vst, and the seventh switching device Tr7 provided in the second stage ST2 is the second switching element Tr7. It is controlled by the first scan pulse Vout1 from one stage ST1.

The common node N and the reset node Q are connected to each other via a connection line 444.

The operation of the shift register constructed as described above will be described in detail as follows.

During the initial period TO, as shown in FIG. 3, only the start pulse Vst and the second clock pulse CLK2 are kept high, and the first clock pulse CLK1 is kept low.

The start pulse Vst and the second clock pulse CLK2 are input to the first stage ST1. Specifically, the start pulse Vst is supplied to the gate terminals of the fourth and seventh switching elements Tr4 and Tr7 provided in the first stage ST1, and the second clock pulse CLK2 is applied to the first terminal ST1. The gate terminal of the third switching device Tr3 provided in the first stage ST1 is supplied.

Then, the fourth, seventh and third switching elements Tr4, Tr7 and Tr3 of the first stage ST1 are turned on.

Accordingly, the charging voltage source VDD is supplied to the set node Q of the first stage ST1 through the turned-on fourth switching device Tr4, and the turned-on seventh switching device ( The discharge voltage source VSS is supplied to the common node N and the reset node QB through Tr7, and the discharge voltage source VSS is supplied through the turned-on third switching element Tr3. The common node N and the reset node QB of the first stage ST1 are supplied. In addition, the common node N is also supplied with the charging voltage source VDD via the second switching element Tr2 which is always turned on.

Then, the set node Q of the first stage ST1 is in a charged state, the reset node QB is in a discharged state, and the common node N is in a discharged state.

Here, as the set node Q is charged, the first switching element Tr1 and the pull-up switching element Trpu, whose gate terminals are connected to the set node Q, are turned on. In addition, as the reset node QB is discharged, the fifth switching element Tr5 and the pull-down switching element Trpd having the gate terminal connected to the reset node QB are turned off.

In addition, since there is no second scan pulse Vout2 from the second stage ST2 in this initial period T0, the sixth switching element Tr6 provided in the first stage ST1 is turned off. .

The common node N is supplied with a discharge voltage source VSS and a charging voltage source VDD, and the channel areas of the respective switching elements Tr1, Tr3, and Tr7 for discharging the common node N are the same. Since it is larger than the channel area of the switching element Tr2 which charges the node N, the common node N is kept in the discharge state in this initial period T0.

The operation during the first period T1 will now be described.

During the first period T1, as shown in FIG. 3, only the first clock pulse CLK1 is kept high, and the start pulse Vst and the second clock pulse CLK2 are kept low. .

Therefore, the fourth and seventh switching elements Tr4 and Tr7 of the first stage ST1 are turned off in response to the start pulse Vst in the low state.

At this time, as the fourth switching device Tr4 is turned off, the set node Q of the first stage ST1 is maintained in a floating state.

Therefore, the set node Q of the first stage ST1 is kept in the charged state by the charging voltage source VDD which has been applied during the initial period T0.

Accordingly, the pull-up switching device Trpu of the first stage ST1 having the gate terminal connected to the set node Q is maintained in the turn-on state.

In this case, the first clock pulse CLK1 is supplied to the drain terminal of the turned-on pull-up switching device Trpu. Then, the charging voltage source VDD charged in the set node Q of the first stage ST1 is amplified (bootstrapping phenomenon bootstrapping).

Therefore, the first clock pulse CLK1 supplied to the drain terminal of the pull-up switching device Trpu provided in the first stage ST1 is the source terminal of the pull-up switching device Trpu (that is, the first stage ST1). It is output stably through the output terminal of). The first clock pulse CLK1 output from the pull-up switching device Trpu is a first scan pulse Vout1.

The output first scan pulse Vout1 is supplied to the first gate line GL1 and serves as a scan pulse for driving the first gate line GL1.

In addition, the first scan pulse Vout1 output from the pull-up switching device Trpu of the first stage ST1 is supplied to the second stage ST2 to supply the node n of the second stage ST2. It acts as a start pulse Vst for charging.

That is, the first scan pulse Vout1 output from the first stage ST1 in the first period T1 is applied to the fourth and seventh switching elements Tr4 and Tr7 included in the second stage ST2. It is supplied to the gate terminal.

In addition, the first clock pulse CLK1 is also supplied to the second stage ST2. That is, the first clock pulse CLK1 is used as a control clock pulse in the second stage ST2. The first clock pulse CLK1 is a third switching device provided in the first stage ST2. It is supplied to the gate terminal of (Tr3).

Accordingly, as the first stage ST1 is enabled in the initial period T0, the second stage ST2 is enabled in the first period T1.

Thereafter, in the second period T2, the second stage ST2 outputs the second clock pulse CLK2 as the second scan pulse Vout2, and the second gate line, the third stage ST3, and It supplies to the 1st stage ST1.

Accordingly, the third stage ST3 is enabled in the second period T2, and the first stage ST1 is disabled.

The disable operation of the first stage ST1 will be described below.

The second scan pulse Vout2 output from the second stage ST2 in the second period T2 is supplied to the gate terminal of the sixth switching element Tr6 provided in the first stage ST1.

Then, the sixth switching device Tr6 is turned on, and at this time, the discharge voltage source VSS is set for the set node Q of the first stage ST1 through the turned-on sixth switching device Tr6. Is supplied. Then, the set node Q is discharged, and the pull-up switching device Trpu and the first switching device Tr1 having the gate terminal connected to the discharged set node Q are turned off.

In the second period T2, the second clock pulse maintains a high state. While the second clock pulse CLK2 maintains a high state, the third switching element of the first stage ST1 ( Tr3) remains on. However, as the second clock pulse CLK2 transitions from a high state to a low state at the end of the second period T2, the falling edge of the second clock pulse CLK2 corresponds to a falling edge. At this point in time, the third switching device Tr3 is turned off.

Accordingly, switching elements for discharging the common node N of the first stage ST1 in the period between the second period T2 and the third period T3, that is, the first, third, and first 7 The switching elements T1, T3, and T7 are all maintained in the turn-off state. Accordingly, the charging voltage source VDD may be supplied to the reset node QB of the first stage ST1 through the second switching element Tr2.

The charging time of the reset node QB is as follows.

That is, in the non-output period, the reset node QB of the first stage is charged at a first time corresponding to a polling time when the two clock pulses CLK2 transition from a high state to a low state. The charging state is maintained from the first time point to a second time point corresponding to a rising time at which the second clock pulse CLK2 transitions from a low state to a high state.

As the reset node QB is charged as described above, the fifth switching element Tr5 having the gate terminal connected to the charged reset node QB is turned on. The discharge voltage source VSS is supplied to the set node Q through the turned-on fifth switching element Tr5. Therefore, the set node Q of the first stage ST1 is discharged.

Thereafter, the first clock pulse CLK1 is supplied to the pull-up switching device Trpu of the first stage ST1 in the third period T3, but before this third period T3 (that is, the second period T2). ) And the set node Q of the first stage ST1 has already been discharged in the period between the step 3) and the third period T3), thereby reducing the coupling phenomenon.

The set node Q is already discharged in a non-output period, but the set node Q is prevented from causing a coupling phenomenon by the first clock pulse CLK1 supplied to the third period T3. By discharging Q) once again, the coupling phenomenon prevention effect can be enhanced. Also, in the non-output period, the timing at which the discharge voltage source VSS is supplied to the set node Q is earlier than the timing at which the first clock pulse CLK1 is supplied to the pull-up switching element Trpu. The coupling phenomenon prevention effect can be further maximized.

On the other hand, whenever the control clock pulse in the high state, that is, the second clock pulse CLK2 in the high state is supplied to the first stage ST1 in the non-output period, the third switching element Tr3 of the first stage ST1 is supplied. ) Is turned on. Accordingly, the discharge voltage source VSS is supplied to the common node N of the first stage ST1 through the turned-on third switching element Tr3. Here, since the common node N is connected to the reset node QB through the connection line 444, the discharge voltage source VSS supplied to the common node N is the reset node QB. Is also supplied.

Therefore, the reset node QB of the first stage ST1 is discharged whenever the second clock pulse CLK2 is supplied to the first stage ST1 in the non-output period.

As described above, the first stage ST1 uses the first clock pulse CLK1 as the control clock pulse to periodically charge and discharge the reset node QB in the non-output period so as to reset the reset stage QB. It is possible to prevent deterioration of the switching elements having the gate terminal connected to the dragon node QB.

In this manner, the 2k-1 stages including the third stage ST3 prevent the coupling phenomenon and the deterioration by performing the operation as described above using the second clock pulse CLK2.

In contrast, the second k stages including the second stage ST2 prevent the coupling phenomenon and the deterioration by performing the above-described operation using the first clock pulse CLK1.

FIG. 5 is a diagram illustrating another circuit configuration of the first stage shown in FIG. 2.

The circuit configuration of the stage shown in FIG. 5 is the same as that shown in FIG. 4, and only differs as follows in the connection relationship of the pull-down switching element Trpd.

That is, as shown in FIG. 5, the pull-down switching device Trpd is controlled by the second clock pulse CLK2, which is a control clock pulse.

FIG. 6 is a diagram illustrating another circuit configuration of the first stage shown in FIG. 2.

The coupling remover CR included in the first stage ST1 of FIG. 6 includes first to fifth switching elements Tr1 to Tr5.

The first to third switching elements Tr1 to Tr3 in FIG. 6 are the same as the first to third switching elements Tr1 to Tr3 shown in FIG. 4.

The fourth switching element Tr4 of FIG. 6 is controlled by the start pulse Vst or the scan pulse from the front stage, and is connected between the common node N and the power supply line for discharge. That is, the gate terminal of the fourth switching device Tr4 is connected to the start transmission line for transmitting the start pulse Vst or the output terminal of the front stage. The drain terminal of the fourth switching element Tr4 is connected to the common node N, and the source terminal is connected to the power supply line for discharge.

For example, the fourth switching device Tr4 provided in the first stage ST1 is controlled by the start pulse Vst, and the fourth switching device Tr4 provided in the second stage is the first stage ( It is controlled by the first scan pulse Vout1 from ST1).

The fifth switching element Tr5 is controlled by the signal supplied to the common node N, and is connected between the charging power supply line and the reset node QB. That is, the gate terminal of the fifth switching device Tr5 is connected to the common node N, the drain terminal is connected to the charging power supply line, and the source terminal is connected to the reset node QB.

The node controller of FIG. 6 includes sixth to eleventh switching elements Tr6 to Tr11.

The sixth switching device Tr6 of FIG. 6 is the same as the fourth switching device Tr4 of FIG. 4, and the seventh switching device Tr7 of FIG. 6 is the same as the fifth switching device Tr5 of FIG. 4. The eighth switching device Tr8 of FIG. 6 is the same as the sixth switching device Tr6 of FIG. 4, and the ninth switching device of FIG. 6 is the same as the seventh switching device Tr7 of FIG. 4.

The tenth switching element Tr10 of FIG. 6 is controlled by the second clock pulse CLK2 from the second clock transmission line CLK2 and is connected between the reset node QB and the discharge power line. . That is, the gate terminal of the tenth switching element Tr10 is connected to the second clock transmission line CLK2, the drain terminal is connected to the reset node QB, and the source terminal is connected to the discharge power line. Connected.

The eleventh switching element Tr11 is controlled by a signal supplied to the set node Q, and is connected between the reset node QB and the discharge power line. That is, the gate terminal of the eleventh switching element Tr11 is connected to the set node Q, the drain terminal is connected to the reset node QB, and the source terminal is connected to the discharge power supply line.

Referring to the operation of the shift register having a stage as shown in Figure 6 in detail as follows.

During the initial period TO, as shown in FIG. 3, only the start pulse Vst and the second clock pulse CLK2 are kept high, and the first clock pulse CLK1 is kept low.

The start pulse Vst and the second clock pulse CLK2 are input to the first stage ST1. Specifically, the start pulse Vst is supplied to the gate terminals of the sixth, ninth, and fourth switching elements Tr6, Tr9, and Tr4 provided in the first stage ST1, and the second clock pulse. CLK2 is supplied to the gate terminals of the third and tenth switching elements Tr3 and Tr10 provided in the first stage ST1.

Then, the sixth, ninth, fourth, third, and tenth switching elements Tr6, Tr9, Tr4, Tr3, and Tr10 of the first stage ST1 are turned on.

Accordingly, the charging voltage source VDD is supplied to the set node Q of the first stage ST1 through the turned-on sixth switching element Tr6, and the turned-on ninth switching element ( The discharge voltage source VSS is supplied to the reset node QB of the first stage ST1 through Tr9, and the discharge voltage source VSS is provided through the turned-on fourth switching element Tr4. The common node N is supplied to the common node N, and the discharge voltage source VSS is supplied to the common node N of the first stage ST1 through the turned-on third switching element Tr3. The discharge voltage source VSS is supplied to the reset node QB of the first stage ST1 through the turned-on tenth switching element Tr10. In addition, the common node N is also supplied with the charging voltage source VDD via the second switching element Tr2 which is always turned on.

Then, the set node Q of the first stage ST1 is in a charged state, the reset node QB is in a discharged state, and the common node N is in a discharged state.

Here, as the set node Q is charged, the first switching element Tr1, the eleventh switching element Tr11, and the pull-up switching element Trpu, whose gate terminals are connected to the set node Q, are charged. Is turned on. In addition, as the reset node QB is discharged, the seventh switching element Tr7 and the pull-down switching element Trpd having the gate terminal connected to the reset node QB are turned off. In addition, as the common node N is discharged, the fifth switching element Tr5 having the gate terminal connected to the common node N is turned off.

In addition, since there is no second scan pulse Vout2 from the second stage ST2 in this initial period T0, the eighth switching element Tr8 provided in the first stage ST1 is turned off. .

The common node N is supplied with a discharge voltage source VSS and a charge voltage source VDD, and the channel areas of the respective switching elements Tr1, Tr3, and Tr4 for discharging the common node N are the same. Since the channel area of the switching element Tr2 that charges the node N is larger than that, the common node N is kept in a discharged state during this initial period T0.

The operation during the first period T1 will now be described.

During the first period T1, as shown in FIG. 3, only the first clock pulse CLK1 is kept high, and the start pulse Vst and the second clock pulse CLK2 are kept low. .

Therefore, the sixth, ninth, and fourth switching elements Tr6, Tr9, and Tr4 of the first stage ST1 are turned off in response to the start pulse Vst in the low state.

At this time, as the sixth switching element Tr6 is turned off, the set node Q of the first stage ST1 is maintained in a floating state.

Therefore, the set node Q of the first stage ST1 is kept in the charged state by the charging voltage source VDD which has been applied during the initial period T0.

Accordingly, the pull-up switching device Trpu of the first stage ST1 having the gate terminal connected to the set node Q is maintained in the turn-on state.

In this case, the first clock pulse CLK1 is supplied to the drain terminal of the turned-on pull-up switching device Trpu. Then, the charging voltage source VDD charged in the set node Q of the first stage ST1 is amplified (bootstrapping phenomenon bootstrapping).

Therefore, the first clock pulse CLK1 supplied to the drain terminal of the pull-up switching device Trpu provided in the first stage ST1 is the source terminal of the pull-up switching device Trpu (that is, the first stage ST1). It is output stably through the output terminal of). The first clock pulse CLK1 output from the pull-up switching device Trpu is a first scan pulse Vout1.

The output first scan pulse Vout1 is supplied to the first gate line GL1 and serves as a scan pulse for driving the first gate line GL1.

In addition, the first scan pulse Vout1 output from the pull-up switching device Trpu of the first stage ST1 is supplied to the second stage ST2 to supply the node n of the second stage ST2. It acts as a start pulse Vst for charging.

That is, the first scan pulse Vout1 output from the first stage ST1 in the first period T1 is the sixth, ninth, and fourth switching elements Tr6 included in the second stage ST2. And Tr9 and Tr4).

In addition, the first clock pulse CLK1 is also supplied to the second stage ST2. That is, the first clock pulse CLK1 is used as a control clock pulse in the second stage ST2. The first clock pulse CLK1 is a third switching device provided in the second stage ST2. It is supplied to the gate terminal of (Tr3).

Accordingly, as the first stage ST1 is enabled in the initial period T0, the second stage ST2 is enabled in the first period T1.

Thereafter, in the second period T2, the second stage ST2 outputs the second clock pulse CLK2 as the second scan pulse Vout2, and the second gate line, the third stage ST3, and It supplies to the 1st stage ST1.

Accordingly, the third stage ST3 is enabled in the second period T2, and the first stage ST1 is disabled.

The disable operation of the first stage ST1 will be described below.

The second scan pulse Vout2 output from the second stage ST2 in the second period T2 is supplied to the gate terminal of the eighth switching device Tr8 provided in the first stage ST1.

Then, the eighth switching device Tr8 is turned on, and at this time, the discharge voltage source VSS is set for the set node Q of the first stage ST1 through the turned-on eighth switching device Tr8. Is supplied. Then, the set node Q is discharged, and the pull-up switching device Trpu and the first switching device Tr1 having the gate terminal connected to the discharged set node Q are turned off.

The second clock pulse CLK2 is maintained at a high state during this second period T2. The third stage of the first stage ST1 is maintained while the second clock pulse CLK2 is at a high state. The switching element Tr3 maintains the turn-on state. However, as the second clock pulse CLK2 transitions from a high state to a low state at the end of the second period T2, the falling edge of the second clock pulse CLK2 corresponds to a falling edge. At this point in time, the third switching device Tr3 is turned off.

Accordingly, switching elements for discharging the common node N of the first stage ST1 in the period between the second period T2 and the third period T3, that is, the first, third, and first 7 The switching elements Tr1, Tr3, and Tr4 are all kept in a turn-off state. Accordingly, the charging voltage source VDD may be supplied to the reset node QB of the first stage ST1 through the second switching element Tr2.

As the reset node QB is charged as described above, the seventh switching element Tr7 having the gate terminal connected to the charged reset node QB is turned on. The discharge voltage source VSS is supplied to the set node Q through the turned-on seventh switching element Tr7. Therefore, the set node Q of the first stage ST1 is discharged.

Thereafter, the first clock pulse CLK1 is supplied to the pull-up switching device Trpu of the first stage ST1 in the third period T3, and before this third period (that is, in the second period and the third period), Since the set node Q of the first stage ST1 has already been discharged during the period, the coupling phenomenon can be reduced.

On the other hand, whenever the control clock pulse in the high state, that is, the second clock pulse in the high state, is supplied to the first stage in the non-output period, the third switching element of the first stage is turned on. Accordingly, the discharge voltage source is supplied to the reset node QB of the first stage ST1 through the turned-on third switching element Tr3.

Therefore, the reset node QB of the first stage ST1 is discharged whenever the second clock pulse CLK2 is supplied to the first stage ST1 in the non-output period.

As described above, the first stage ST1 uses the first clock pulse CLK1 as the control clock pulse to periodically charge and discharge the reset node QB in the non-output period so as to reset the reset stage QB. It is possible to prevent deterioration of the switching elements having the gate terminal connected to the dragon node QB.

In this manner, the 2k-1 stages including the third stage ST3 prevent the coupling phenomenon and the deterioration by performing the operation as described above using the second clock pulse CLK2.

In contrast, the second k stages including the second stage ST2 prevent the coupling phenomenon and the deterioration by performing the above-described operation using the first clock pulse CLK1.

FIG. 7 is a diagram illustrating still another circuit configuration of the first stage shown in FIG. 2.

The circuit configuration of the stage shown in FIG. 7 is the same as that shown in FIG. 6, and only differs as follows in the connection relationship of the pull-down switching element Trpd.

That is, as shown in FIG. 7, the pull-down switching device Trpd is controlled by the second clock pulse CLK2, which is a control clock pulse.

FIG. 8 is a diagram illustrating still another circuit configuration of the first stage shown in FIG. 2.

The coupling remover CR included in the first stage ST1 of FIG. 8 includes first to third switching devices Tr1 to Tr3.

The first switching element Tr1 shown in FIG. 8 is controlled by the signal supplied to the set node Q, and is connected between the discharge power supply line and the reset node QB. That is, the gate terminal of the first switching element Tr1 is connected to the set node Q, the drain terminal is connected to the discharge power supply line, and the source terminal is connected to the reset node QB.

The second switching element Tr2 is controlled by the charging voltage source VDD from the charging power supply line and is connected between the charging power supply line and the reset node QB. That is, the gate terminal and the drain terminal of the second switching element Tr2 are connected to the power supply line for charging, and the source terminal is connected to the reset node QB.

The third switching element Tr3 is controlled by the second clock pulse CLK2 from the second clock transmission line and is connected between the discharge power supply line and the reset node QB. That is, the gate terminal of the third switching element Tr3 is connected to the second clock transmission line, the drain terminal is connected to the discharge power supply line, and the source terminal is connected to the reset node QB.

The node controller of FIG. 8 includes fourth to seventh switching elements Tr7.

The fourth switching device Tr4 of FIG. 8 is the same as the fourth switching device Tr4 of FIG. 4, and the sixth switching device Tr6 of FIG. 8 is the same as the sixth switching device Tr6 of FIG. 4. The eighth switching device Tr8 of FIG. 8 is the same as the sixth switching device Tr6 of FIG. 4, and the seventh switching device Tr7 of FIG. 8 is the same as the seventh switching device Tr7 of FIG. 4.

The fifth switching element Tr5 of FIG. 8 is controlled by the signal supplied to the reset node QB, and is connected between the set node Q and the output terminal. That is, the gate terminal of the fifth switching element Tr5 is connected to the reset node QB, the drain terminal is connected to the set node Q, and the source terminal is output of the first stage ST1. Connected to the terminal.

Referring to the operation of the shift register having a stage as shown in Figure 8 in detail as follows.

During the initial period TO, as shown in FIG. 3, only the start pulse Vst and the second clock pulse CLK2 are kept high, and the first clock pulse CLK1 is kept low.

The start pulse Vst and the second clock pulse CLK2 are input to the first stage ST1. Specifically, the start pulse Vst is supplied to the gate terminals of the fourth and seventh switching elements Tr4 and Tr7 provided in the first stage ST1, and the second clock pulse CLK2 is applied to the first terminal ST1. The gate terminal of the third switching device Tr3 provided in the first stage ST1 is supplied.

Then, the fourth, seventh and third switching elements Tr4, Tr7 and Tr3 of the first stage ST1 are turned on.

Accordingly, the charging voltage source VDD is supplied to the set node Q of the first stage ST1 through the turned-on fourth switching device Tr4, and the turned-on seventh switching device ( The discharge voltage source VSS is supplied to the reset node QB through Tr7, and the discharge voltage source VSS is supplied through the turned-on third switching device Tr3 to the first stage ST1. Is supplied to the reset node QB. In addition, the common node N is also supplied with the charging voltage source VDD via the second switching element Tr2 which is always turned on.

Then, the set node Q of the first stage ST1 is in a charged state, and the reset node QB is in a discharged state.

Here, as the set node Q is charged, the first switching element Tr1 and the pull-up switching element Trpu, whose gate terminals are connected to the set node Q, are turned on. In addition, as the reset node QB is discharged, the fifth switching element Tr5 and the pull-down switching element Trpd having the gate terminal connected to the reset node QB are turned off.

In addition, since there is no second scan pulse Vout2 from the second stage ST2 in this initial period T0, the sixth switching element Tr6 provided in the first stage ST1 is turned off. .

The reset node QB is supplied with a discharge voltage source VSS and a charge voltage source VDD, and each channel of each of the switching elements Tr1, Tr3, and Tr7 discharges the reset node QB. Since the area is larger than the channel area of the switching element Tr2 which charges the reset node QB, the reset node QB is maintained in the discharged state during this initial period T0.

The operation during the first period T1 will now be described.

During the first period T1, as shown in FIG. 3, only the first clock pulse CLK1 is kept high, and the start pulse Vst and the second clock pulse CLK2 are kept low. .

Therefore, the fourth and seventh switching elements Tr4 and Tr7 of the first stage ST1 are turned off in response to the start pulse Vst in the low state.

At this time, as the fourth switching device Tr4 is turned off, the set node Q of the first stage ST1 is maintained in a floating state.

Therefore, the set node Q of the first stage ST1 is kept in the charged state by the charging voltage source VDD which has been applied during the initial period T0.

Accordingly, the pull-up switching device Trpu and the first switching device Tr1 of the first stage ST1 having the gate terminal connected to the set node Q are maintained in the turn-on state.

In this case, the first clock pulse CLK1 is supplied to the drain terminal of the turned-on pull-up switching device Trpu. Then, the charging voltage source VDD charged in the set node Q of the first stage ST1 is amplified (bootstrapping phenomenon bootstrapping).

Therefore, the first clock pulse CLK1 supplied to the drain terminal of the pull-up switching device Trpu provided in the first stage ST1 is the source terminal of the pull-up switching device Trpu (that is, the first stage ST1). It is output stably through the output terminal of). The first clock pulse CLK1 output from the pull-up switching device Trpu is a first scan pulse Vout1.

The output first scan pulse Vout1 is supplied to the first gate line and serves as a scan pulse for driving the first gate line GL1.

In addition, the first scan pulse Vout1 output from the pull-up switching device Trpu of the first stage ST1 is supplied to the second stage ST2 to supply the node n of the second stage ST2. It acts as a start pulse Vst for charging.

That is, the first scan pulse Vout1 output from the first stage ST1 in the first period T1 is applied to the fourth and seventh switching elements Tr4 and Tr7 included in the second stage ST2. It is supplied to the gate terminal.

In addition, the first clock pulse CLK1 is also supplied to the second stage ST2. That is, the first clock pulse CLK1 is used as a control clock pulse in the second stage ST2. The first clock pulse CLK1 is a third switching device provided in the second stage ST2. It is supplied to the gate terminal of (Tr3).

Accordingly, as the first stage ST1 is enabled in the initial period T0, the second stage ST2 is enabled in the first period T1.

Thereafter, in the second period T2, the second stage ST2 outputs the second clock pulse CLK2 as the second scan pulse Vout2, and the second gate line, the third stage ST3, and It supplies to the 1st stage ST1.

Accordingly, the third stage ST3 is enabled in the second period T2, and the first stage ST1 is disabled.

The disable operation of the first stage ST1 will be described below.

The second scan pulse Vout2 output from the second stage ST2 in the second period T2 is supplied to the gate terminal of the sixth switching element Tr6 provided in the first stage ST1.

Then, the sixth switching device Tr6 is turned on, and at this time, the discharge voltage source VSS is set for the set node Q of the first stage ST1 through the turned-on sixth switching device Tr6. Is supplied. Then, the set node Q is discharged, and the pull-up switching device Trpu and the first switching device Tr1 having the gate terminal connected to the discharged set node Q are turned off.

In the second period T2, the second clock pulse maintains a high state. While the second clock pulse CLK2 maintains a high state, the third switching element of the first stage ST1 ( Tr3) remains on. However, as the second clock pulse CLK2 transitions from a high state to a low state at the end of the second period T2, the falling edge of the second clock pulse CLK2 corresponds to a falling edge. At this point in time, the third switching device Tr3 is turned off.

Accordingly, switching elements for discharging the common node N of the first stage ST1 in the period between the second period T2 and the third period T3, that is, the first, third, and first 7 The switching elements T1, T3, and T7 are all maintained in the turn-off state. Accordingly, the charging voltage source VDD may be supplied to the reset node QB of the first stage ST1 through the second switching element Tr2.

As the reset node QB is charged as described above, the seventh switching element Tr7 having the gate terminal connected to the charged reset node QB is turned on. The discharge voltage source VSS is supplied to the set node Q through the turned-on seventh switching element Tr7. Therefore, the set node Q of the first stage ST1 is discharged.

Thereafter, the first clock pulse CLK1 is supplied to the pull-up switching device Trpu of the first stage ST1 in the third period T3, and before this third period (that is, in the second period and the third period), Since the set node Q of the first stage ST1 has already been discharged during the period, the coupling phenomenon can be reduced.

On the other hand, whenever the control clock pulse in the high state, that is, the second clock pulse CLK2 in the high state is supplied to the first stage ST1 in the non-output period, the third switching element Tr3 of the first stage ST1 is supplied. ) Is turned on. Accordingly, the discharge voltage source VSS is supplied to the reset node QB of the first stage ST1 through the turned-on third switching element Tr3.

Therefore, the reset node QB of the first stage ST1 is discharged whenever the second clock pulse CLK2 is supplied to the first stage ST1 in the non-output period.

As described above, the first stage ST1 uses the first clock pulse CLK1 as the control clock pulse to periodically charge and discharge the reset node QB in the non-output period so as to reset the reset stage QB. It is possible to prevent deterioration of the switching elements having the gate terminal connected to the dragon node QB.

In this manner, the 2k-1 stages including the third stage ST3 prevent the coupling phenomenon and the deterioration by performing the operation as described above using the second clock pulse CLK2.

In contrast, the second k stages including the second stage ST2 prevent the coupling phenomenon and the deterioration by performing the above-described operation using the first clock pulse CLK1.

FIG. 9 is a diagram illustrating still another circuit configuration of the first stage shown in FIG. 2.

The circuit configuration of the stage shown in FIG. 9 is the same as that shown in FIG. 8, and differs only in the connection relationship of the pull-down switching element Trpd as follows.

That is, as shown in FIG. 9, the pull-down switching device Trpd is controlled by the second clock pulse CLK2, which is a control clock pulse.

All the switching elements described above may use a transistor having a semiconductor layer made of a-Si (amorphous silicon) or poly-Si (polysilicon).

In this case, the above-described switching elements may be n-type or p-type transistors, and the switching elements shown in the drawing are n-type transistors, which are turned on in the high state of the aforementioned clock pulse or start pulse and turned on in the low state. -Off.

When each switching element is a p-type transistor, the switching elements are turned on in the low state of the clock pulse or the start pulse and turned off in the high state.

The active state of each clock pulse and start pulse described previously may be high or low depending on the type of the transistor.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

The shift register according to the present invention as described above has the following effects.

The coupling remover provided in the shift register according to the present invention periodically charges and discharges a reset node in a non-output period, and an active scan clock pulse is applied to the pull-up switching element during the non-output period. The reset node is charged before being supplied.

Therefore, it is possible to prevent the multi output due to the coupling phenomenon and to prevent the deterioration of the switching elements connected to the reset node, in particular the pull-down switching element.

Claims (13)

A plurality of stages for sequentially outputting scan pulses through an output terminal; Each stage, A node controller for controlling the charge and discharge states of the set node and the reset node; A pull-up switching element controlled by a signal supplied to the set node and connected to the scan clock transmission line for transmitting a scan clock pulse and the output terminal; A pull-down switching element controlled by a control signal from the outside and connected between a discharge power supply line for transmitting a discharge voltage source and the output terminal; And Periodically charging and discharging the reset node during the non-output period of the stage, and charging the reset node before the active scan clock pulse is supplied to the pull-up switching element during the non-output period. A coupling remover; The coupling remover is supplied with a control clock pulse to discharge the reset node every time the control clock pulse remains active during the non-output period, and the control clock pulse is inactive during the non-output period. Charging the reset node every time the state is held; The length of the active period of the scan clock pulse and the length of the active period of the control clock pulse are the same; The length of the inactive period of the scan clock pulse and the length of the inactive period of the control clock pulse are the same; The inactive period of the clock pulse for scanning is longer than the active period, and the inactive period of the control clock pulse is longer than the active period; The scan clock pulse is kept active within an inactive period of the control clock pulse; The control clock pulse is kept active within an inactive period of the scan clock pulse; And, The coupling remover charges the reset node at a first time point at which the control clock pulse transitions from the active state to the inactive state during the non-output period, and transitions the charged state from the control clock pulse to the active state again. Up to a second point in time; The coupling remover, A first switching element controlled by a signal supplied to the set node and connected between the discharge power supply line and a common node; A second switching element controlled by a charging voltage source from a charging power line and connected between said charging power line and said common node; A third switching element controlled by a control clock pulse from the control clock transmission line and connected between the common node and the discharge power supply line; And And a connection line connecting the common node and the reset node. delete delete delete The method of claim 1, The node control unit, A fourth switching element controlled by a start pulse or a scan pulse from a front end stage, and connected between the charging power supply line and the set node; A fifth switching element controlled by a signal supplied to the reset node and connected between the set node and a discharge power line; A sixth switching element controlled by the scan pulse from the next stage and connected between the set node and the discharge power line; And And a seventh switching element controlled by the start pulse or a scan pulse from a front end stage, and connected between the reset node and the discharge power line. 6. The method of claim 5, And a control signal for controlling the pull-down switching element is a signal supplied to the reset node or the control clock pulse. A plurality of stages for sequentially outputting scan pulses through an output terminal; Each stage, A node controller for controlling the charge and discharge states of the set node and the reset node; A pull-up switching element controlled by a signal supplied to the set node and connected to the scan clock transmission line for transmitting a scan clock pulse and the output terminal; A pull-down switching element controlled by a control signal from the outside and connected between a discharge power supply line for transmitting a discharge voltage source and the output terminal; And Periodically charging and discharging the reset node during the non-output period of the stage, and charging the reset node before the active scan clock pulse is supplied to the pull-up switching element during the non-output period. A coupling remover; The coupling remover is supplied with a control clock pulse to discharge the reset node every time the control clock pulse remains active during the non-output period, and the control clock pulse is inactive during the non-output period. Charging the reset node every time the state is held; The length of the active period of the scan clock pulse and the length of the active period of the control clock pulse are the same; The length of the inactive period of the scan clock pulse and the length of the inactive period of the control clock pulse are the same; The inactive period of the clock pulse for scanning is longer than the active period, and the inactive period of the control clock pulse is longer than the active period; The scan clock pulse is kept active within an inactive period of the control clock pulse; The control clock pulse is kept active within an inactive period of the scan clock pulse; And, The coupling remover charges the reset node at a first time point at which the control clock pulse transitions from the active state to the inactive state during the non-output period, and transitions the charged state from the control clock pulse to the active state again. Up to a second point in time; The coupling remover, A first switching element controlled by a signal supplied to the set node and connected between the discharge power supply line and a common node; A second switching element controlled by a charging voltage source from a charging power line and connected between said charging power line and said common node; A third switching element controlled by a control clock pulse from the control clock transmission line and connected between the common node and the discharge power supply line; A fourth switching element controlled by a start pulse or a scan pulse from a front end stage and connected between the common node and a discharge power line; And And a fifth switching element controlled by a signal supplied to the common node and connected between the charging power line and a reset node. The method of claim 7, wherein The node control unit, A sixth switching element controlled by a start pulse or a scan pulse from a front end stage and connected between the charging power supply line and the set node; A seventh switching element controlled by a signal supplied to the reset node and connected between the set node and a discharge power line; An eighth switching element controlled by a scan pulse from a next stage and connected between said set node and a discharge power line; A ninth switching element controlled by the start pulse or the scan pulse from the front end stage and connected between the reset node and the discharge power line; A tenth switching element controlled by a control clock pulse from the control clock transmission line and connected between the reset node and a discharge power line; And And an eleventh switching element controlled by a signal supplied to said set node and connected between said reset node and said discharge power line. The method of claim 7, wherein And a control signal for controlling the pull-down switching element is a signal supplied to the reset node or the control clock pulse. A plurality of stages for sequentially outputting scan pulses through an output terminal; Each stage, A node controller for controlling the charge and discharge states of the set node and the reset node; A pull-up switching element controlled by a signal supplied to the set node and connected to the scan clock transmission line for transmitting a scan clock pulse and the output terminal; A pull-down switching element controlled by a control signal from the outside and connected between a discharge power supply line for transmitting a discharge voltage source and the output terminal; And Periodically charging and discharging the reset node during the non-output period of the stage, and charging the reset node before the active scan clock pulse is supplied to the pull-up switching element during the non-output period. A coupling remover; The coupling remover is supplied with a control clock pulse to discharge the reset node every time the control clock pulse remains active during the non-output period, and the control clock pulse is inactive during the non-output period. Charging the reset node every time the state is held; The length of the active period of the scan clock pulse and the length of the active period of the control clock pulse are the same; The length of the inactive period of the scan clock pulse and the length of the inactive period of the control clock pulse are the same; The inactive period of the clock pulse for scanning is longer than the active period, and the inactive period of the control clock pulse is longer than the active period; The scan clock pulse is kept active within an inactive period of the control clock pulse; The control clock pulse is kept active within an inactive period of the scan clock pulse; And, The coupling remover charges the reset node at a first time point at which the control clock pulse transitions from the active state to the inactive state during the non-output period, and transitions the charged state from the control clock pulse to the active state again. Up to a second point in time; The coupling remover, A first switching element controlled by a signal supplied to said set node and connected between a discharge power supply line and a reset node; A second switching element controlled by a charging voltage source from a charging power line and connected between said charging power line and said reset node; And And a third switching element controlled by a control clock pulse from the control clock transmission line and connected between the discharge power supply line and the reset node. 11. The method of claim 10, The node control unit, A fourth switching element controlled by a start pulse or a scan pulse from a front end stage, and connected between the charging power supply line and the set node; A fifth switching element controlled by a signal supplied to the reset node and connected between the set node and an output terminal; A sixth switching element controlled by the scan pulse from the next stage and connected between the set node and the discharge power line; And And a seventh switching element controlled by the start pulse or a scan pulse from a front end stage and connected between the reset node and a discharge power line. The method of claim 11, And a control signal for controlling the pull-down switching element is a signal supplied to the reset node or the control clock pulse. The method according to any one of claims 1, 7, and 10, The scan clock pulse supplied to the odd stage and the control clock pulse supplied to the even-numbered stage are the same; And, And a control clock pulse supplied to the odd stage and a scan clock pulse supplied to the even stage.

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