KR101339580B1 - Manufacturing method for epitaxial soi wafer manufacturing apparatus - Google Patents

Abstract

The present invention relates to an epitaxial layer manufacturing method of a soy wafer capable of growing an epitaxial layer on a soy wafer to have a uniform thickness and a plan view.
The ball invention heats the center of the soy wafer to a temperature higher than the circumference while the source gas is introduced and heats the circumference of the soy wafer to a temperature higher than the center, thereby reducing the slip of the soy wafer, which was frequently generated at the beginning of deposition. In addition, the defect rate can be reduced, the quality of the soy wafer can be maintained uniformly, and the flatness can be increased.
In addition, the present invention can easily adjust the position and thickness of the source gas is deposited on the soy wafer by adjusting the lamps and the power supplied to the heating by dividing the center / circumference in the top / bottom of the soy wafer, the desired specification easily A soy wafer having an epitaxial layer of can be produced.

Description

Method of manufacturing epi layer of soy wafer {MANUFACTURING METHOD FOR EPITAXIAL SOI WAFER MANUFACTURING APPARATUS}

The present invention relates to an epitaxial layer manufacturing method of a soy wafer capable of growing an epitaxial layer on a soy wafer to have a uniform thickness and a plan view.

Generally, a silicon wafer is a crystalline silicon thin film made of polycrystalline silicon as a raw material, depending on a processing method, a polished wafer, an epitaxial wafer, a silicon on insulator wafer, and a diffused wafer. It is divided into a diffused wafer and a high wafer.

An epitaxial wafer is formed by growing an epitaxial layer, which is another single crystal layer, on the surface of a silicon wafer, and has fewer surface defects, and has characteristics that can control the concentration and type of impurities. At this time, the epi layer has advantages of high purity, excellent crystal characteristics, and improved yield and device characteristics of semiconductor devices that are highly integrated.

A silicon-on-insulator wafer is a wafer with a silicon single crystal layer on an insulating film, commonly referred to as SOI. Since a thin insulating layer is formed between the substrate surface forming the circuit and the lower layer, parasitic capacitance is reduced, thereby improving the performance of the device. The speed of operation can be increased at the same voltage, and the supply voltage can be lowered at the same speed.

Such a soy wafer may be used to form an epitaxial layer. Recently, as the diameter of the wafer increases, it is difficult to form an epitaxial layer having a uniform thickness and a plan view up to the circumferential portion of the wafer. Thus, the flow of the source gas to be deposited on the wafer surface is controlled to uniformly form the epi layer of the wafer.

However, the SOI wafer is composed of a top Si layer, a box (buried oxide layer), and a Si substrate. Since the thermal conductivity and thermal expansion coefficient of the buried oxide layer and Si are different, chemical vapor deposition (CVD) is used to form an epitaxial layer. It shows a different heat distribution than a general silicon wafer under a thermal process such as.

Therefore, when the epi layer is deposited on the SOI wafer under the same conditions as that of the general silicon wafer, that is, in a temperature environment, since the thermal distribution of the SOI wafer is different from that of the general silicon wafer, slip is caused on the circumference of the SOI wafer due to thermal stress. In addition, the thickness and flatness of the soy wafer are not uniform in the center and the circumference of the soy wafer, and it is difficult to match the set value, thereby degrading the quality of the manufactured wafer.

The present invention has been made to solve the above problems of the prior art, and an object of the present invention is to provide an epi layer manufacturing method of a soy wafer that can reduce the occurrence of slip even when the epi layer is deposited on the soy wafer.

It is an object of the present invention to provide a method for manufacturing an epi layer of a soy wafer which can form the epi layer with a uniform thickness and a plan view even when the epi layer is deposited on the soy wafer.

The present invention is a loading step of loading a soy wafer; A deposition step of growing an epitaxial layer as the source gas is injected into the soy wafer loaded in the loading step; A first heating step of heating the center of the soy wafer to a temperature higher than the circumference of the soy wafer during the initial first set time t1 of the deposition step; And a second heating step of heating the circumference of the soy wafer to a temperature higher than the center of the soy wafer for a second predetermined time t2 after the first heating step, in which the deposition step is completed. The step includes controlling the power supplied to the lower lamps heating the lower surface of the soy wafer in the range of 72 to 78% relative to the total power supplied to the upper / lower lamps heating the upper and lower surfaces of the soy wafer. A soy wafer epi layer manufacturing method is provided.

Preferably, the loading step may include a process in which the soy wafer is rotatably supported.

delete

In addition, in the present invention, the first heating step is 17 ~ 27% of the power supplied to the lower inner lamp for heating the center of the lower surface of the soy wafer with respect to the power supplied to the lower lamps for heating the lower surface of the soy wafer. It may include the process of controlling.

In the present invention, the first heating step is 21 ~ 37% of the power supplied to the lower inner lamp for heating the center of the lower surface of the soy wafer with respect to the power supplied to the lower outer lamp for heating the lower peripheral portion of the soy wafer It may include a process to control the range.

Further, in the present invention, the second heating step is 21% or less of the power supplied to the lower inner lamp for heating the center of the lower surface of the soy wafer with respect to the power supplied to the lower outer lamp for heating the lower peripheral portion of the soy wafer It may include the process of controlling.

An apparatus for manufacturing an epi layer of a soy wafer and a method for manufacturing the same according to the present invention provide a power source to heat a center of a soy wafer, which has a large amount of slip in the circumference, during an initial setting time for depositing the epi layer on the soy wafer. Since it is possible to control the occurrence of slip in the circumference, there is an advantage that can reduce the defective rate.

In addition, the apparatus for manufacturing an epi layer of the soy wafer and the method for manufacturing the same according to the present invention sequentially control the power supplied to the lamps that heat the center and the circumference of the soy wafer while the f layer is deposited on the soy wafer. It is possible to form an epitaxial layer having a uniform thickness and a flatness over the entire wafer, thereby increasing the quality reliability of the fabricated wafer, and the thickness and top view of the epitaxial layer formed on the soy wafer depending on the power supplied to the lamps. There is an advantage that can be easily controlled.

1 is a view showing an epi layer manufacturing apparatus of a soy wafer according to the present invention.
2 is a flowchart illustrating a method of manufacturing an epi layer of a soy wafer according to the present invention.
3a and 3b is a view showing the epi-layer slip generation pattern of the soy wafer in accordance with the power supply supplied to the lower lamps of the epi-layer manufacturing apparatus of the soy wafer in accordance with the present invention.
Figures 4a and 4b is a view showing the epi-layer slip generation pattern of the soy wafer in accordance with the power supply supplied to the entire lamp of the epi-layer manufacturing apparatus of the soy wafer according to the present invention.
5 is a graph showing the thickness of the epi layer deposited by the epi layer manufacturing method of the conventional soy wafer according to the present invention.
6a and 6b are a map showing a plan view of the epi layer deposited by the epi layer manufacturing method of the soy wafer according to the prior art and the present invention.

Hereinafter, the present embodiment will be described in detail with reference to the accompanying drawings. It should be understood, however, that the scope of the inventive concept of the present embodiment can be determined from the matters disclosed in the present embodiment, and the spirit of the present invention possessed by the present embodiment is not limited to the embodiments in which addition, Variations.

1 is a view showing an epi layer manufacturing apparatus of a soy wafer according to the present invention.

As shown in FIG. 1, an epitaxial layer manufacturing apparatus of a soy wafer according to the present invention includes a rotating plate 110 on which the soy wafer W is placed, and an upper surface of the soy wafer W by radiant heat from the upper side of the rotating plate 110. Upper lamps 120 for heating the lower lamps, lower lamps 130 for heating the lower surface of the rotating plate 110 and the soy wafer W with radiant heat under the rotating plate 110, and the lamps 120 and 130. It may include a power control unit 140 for sequentially controlling the power supplied to the epi layer deposition is performed.

The rotating plate 110 has a disk shape, soy wafer (W) may be seated on the upper surface. In this case, a rotating shaft 111 is provided at the center of the lower surface of the rotating plate 110 and may be connected to a driving motor (not shown) for driving the rotating shaft 111. Of course, a plurality of supports (not shown) may be installed between the rotating plate 110 and the rotating shaft 111 to support the rotating plate 110 at a predetermined interval in order to support the rotating plate 110 more stably. In the present invention and drawings will be omitted.

The upper lamps 120 heat the upper inner lamp 121 provided on the center side of the rotating plate 110 and the upper circumference of the soy wafer W so as to heat the upper center of the top surface of the soy wafer W. It may be made of an upper outer lamp 122 provided on the upper side of the circumference of the rotating plate (110). In this case, the upper lamps 120 are installed to be in close proximity or contact, but may be operated by power supplied separately by the power control unit 140.

The lower lamps 130 heat the lower inner lamp 131 provided on the lower side of the lower center of the rotating plate 110 to heat the center of the soy wafer W, and the lower circumference of the soy wafer W. It may be made of a lower outer lamp 132 provided on the lower side of the circumferential portion of the rotating plate 110. Likewise, the lower lamps 130 are installed to be in close proximity or contact, but may be operated by power supplied separately by the power control unit 140.

Such lamps 120 and 130 are configured to vary in heating degree according to a power supply. For example, halogen lamps may be applied, but various types of lamps may be applied.

The power control unit 140 sequentially controls the power supplied to the lamps 120 and 130 according to the set time during the deposition of the epi layer, based on the time point at which the source gas is injected around the soy wafer (W). The power is controlled. Of course, the power control unit 140 supplies power to the lamps 120 and 130 to heat the soy wafer and the chamber space where the soy wafer W is placed even before the source gas is introduced into the soy wafer W.

In this case, the power control unit 140 divides the amount of power that can be supplied to all of the lamps 120 and 130 by the ratio of supplying the power to the upper lamps 120 and the lower lamps 130, and thus the upper part determined accordingly. The amount of power that can be supplied to the lamps 120 is divided by the ratio that can be supplied to the upper inner lamp 121 and the upper outer lamp 122, and thus the power supply to the lower lamps 130 determined accordingly. The size of is divided by the ratio that can be supplied to the lower inner lamp 131 and the lower outer lamp 132.

However, the magnitude of the power supplied to the inner lamps 121 and 131 to be described below refers to the sum of the magnitudes of the power supplied to the upper inner lamp 121 and the lower inner lamp 131, respectively. The size of the power supplied to the fields 122 and 132 also refers to the sum of the sizes of the power supplied to the upper external lamp 122 and the lower external lamp 132, respectively.

In detail, the power control unit 140 controls the soy wafer W during the first preset time t1 from the time when the soy wafer W is loaded onto the rotating plate 110 to the initial time when the epi layer is deposited. The size of the power supplied to the lower inner lamps 131 is increased so that the center portion is heated to a temperature higher than the circumference portion. In this case, the wafer mounted on the rotating plate 110 is more affected by the temperature of the lower lamps 131 and 132 positioned directly below the rotating plate 110 than the upper lamps 121 and 122. That is, the wafer mounted on the rotating plate 110 receives radiation heat from the upper lamps 121 and 122, while the lower lamps 131 and 132 receive conductive heat transfer from the lower lamps 131 and 132 through the rotating plate 110. Heat transfer by) occurs more significantly. Therefore, at the initial stage of depositing the epitaxial layer, the size of the power source supplied to the lower internal lamp 131 is larger than that of the power supplied to the lower internal lamp 131 supplied during normal epi product progress. As heat is concentrated to the house part and heat transferred to the circumferential part is reduced, the occurrence of slip caused by thermal stress at the circumferential part of the soy wafer can be significantly reduced.

Thereafter, the power control unit 140 performs a soy wafer during the second set time t2, which is a time after the first set time t1, which is an initial time point at which the epitaxial layer is deposited on the soy wafer W, and until the end of the epi process. The size of the power supplied to the outer lamps 122 and 132 is controlled to be greater than that of the power supplied to the inner lamps 121 and 131 so that the circumference of (W) is heated to a temperature higher than the center portion. Therefore, even if the epi layer is thickly deposited at the center of the soy wafer W during the initial first setting time t1, the epi layer is thickly deposited at the circumference of the soy wafer W during the second setting time t2. The thickness and flatness can be kept uniform. In this case, the first set time (t1) is a time corresponding to 20 to 25% of the total epilayer deposition time, the second set time (t2) is a time corresponding to the remaining 75 to 80%.

As such, even if the power is adjusted, the size of the power supplied to the lower inner lamp 131 is larger than that of the conventional epi product, which is most likely to slip on the circumference of the soy wafer (W). In order to prevent the occurrence of much, it is preferable to maintain a relatively high temperature in the center of the soy wafer (W).

As described above, not only the slip is not generated by the power control unit 140 but also the range of limiting the size of the power supplied to the lamps 120 and 130 in order to maintain the thickness and flatness of the epi layer uniformly. This will be explained in detail later.

2 is a flowchart illustrating a method of manufacturing an epi layer of a soy wafer according to the present invention.

Looking at the epi layer manufacturing method of the soy wafer according to the present invention with reference to Figures 1 to 2, the soy wafer (W) is loaded, the deposition of the epi layer as the source gas is introduced (see S1, S2).

At this time, the soy wafer (W) is seated on the rotating plate 110 located in the chamber of about 500 ℃, by the radiant heat of the lamps (120, 130), the chamber and the soy wafer (W), is heated, bake (Bake) is made at a process temperature of about 1100 ~ 1300 ℃.

As described above, after baking of the soy wafer W, the temperature inside the chamber is adjusted in a stepwise manner by controlling the power supplied to the lamps 120 and 130 according to the process temperature during subsequent epilayer deposition. do. Thereafter, as the source plate is introduced into the chamber and the rotating plate 110 is rotated, the source gas is grown in the epi layer on the surface of the soy wafer (W).

Next, during the first predetermined time t1, the center of the soy wafer W is heated to a temperature higher than the circumference portion (see S3 and S4).

In this case, the first predetermined time t1 refers to a time from when the Soy wafer W is loaded to an initial time when the epi layer is deposited on the Soy wafer W.

In addition, the size of the power supplied to the lower lamps 131 and 132 is set to be much higher than that of the power supplied to the upper lamps 121 and 122 in order to heat the center of the soy wafer W to a temperature higher than the circumference. Preferably, the size of power supplied to the lower lamps may be adjusted in a range of 72 to 78% relative to the size of power supplied to the upper / lower lamps. In this case, since heat generated in the lower lamps 131 and 132 is directly transferred to the wafer through the rotation shaft 110, the heat transfer effects of the lower lamps 131 and 132 are more affected than the upper lamps 121 and 122. It is desirable to adjust this accordingly.

In addition, in order to heat the center of the soy wafer (W) to a temperature higher than the circumference, the size of the power supplied to the lower inner lamp 131 is set higher than before, preferably the lower lamps (131, 132) The amount of power supplied to the lower inner lamp 131 is adjusted to 17 to 27% with respect to the amount of power supplied to the lower inner lamp 131 or the lower inner lamp 131 with respect to the power supplied to the lower outer lamp 132. You can adjust the size of the power supply to 21 to 37%.

Next, during the second predetermined time t2, the circumferential portion of the soy wafer W is heated to a temperature higher than the center portion (see S5 and S6).

In this case, the second set time t2 refers to the time after the first set time t1 has elapsed until the deposition of the epi layer on the soy wafer W is completed.

In addition, the size of the power supplied to the lower external lamp 132 is controlled to be higher than the size of the power supplied to the lower inner lamp 131 to heat the circumferential portion of the soy wafer (W) to a temperature higher than the center portion. Preferably, the size of the power supplied to the lower inner lamp 131 with respect to the power supplied to the lower outer lamp 132 may be adjusted to 21% or less.

In this manner, when the epi layer is deposited on the soy wafer W at the set thickness, the source gas is stopped and the epi process is completed (see S7).

3a and 3b is a view showing the epi-layer slip generation pattern of the soy wafer in accordance with the power supply supplied to the lower lamps of the epilayer manufacturing apparatus of the soy wafer according to the present invention, Figures 4a and 4b Figure 1 shows the epilayer slip generation pattern of the Soy wafer according to the power supply supplied to all lamps of the epilayer manufacturing apparatus of the soy wafer.

The epitaxial wafer manufacturing apparatus of the soy wafer according to the present invention can properly maintain the thickness and flatness of the epitaxial layer as well as not slipping the soy wafer by appropriately adjusting the power supplied to the lamps. As such, the size of the power supplied to the lamps may be defined as follows through repeated experiments.

The numerical values to be described below are expressed as the ratio of controlling the power supplied to the lamps during the first preset time t1, and the ratio of controlling the power supplied to the lamps during the second preset time t2. The conditions used for manufacturing a general epi wafer during the set time t2 are applied. In this case, the conditions used when fabricating a general epi wafer are 58% of the power supplied to the lower lamps and the power supply to the upper lamps, compared to the power supply to the upper / lower lamps. The size of the power supplied to the lower internal lamp is controlled to 72% for the size of the power supplied to the upper internal lamp, and 17.5% to the size of the power that can be supplied to the lower lamps for the size of. At this time, the supply power of the lower internal lamp to the supply power of the lower external lamp is maintained at about 21%.

Referring to the figures shown in FIGS. 3A to 3B, the size of the power supplied to the lower lamps is 76% and the upper lamp is about the size of the power supply to the upper / lower lamps during the first preset time t1. 58% of the power supplied to the upper internal lamp for the amount of power that can be supplied to the lower lamp, and 17% of the power supplied to the lower internal lamp for the amount of power that can be supplied to the lower lamps. Adjusted to 27%.

That is, as the power supplied to the lower internal lamp is lower than 17% with respect to the power to be supplied to the lower lamps, slippage of 307 mm or more occurs at the circumference of the soy wafer, and the size of the power supply is reduced to 27%. The higher the% or more, the more than 460mm slip occurs in the center of the soy wafer. Therefore, as the heat supplied to the lower center of the soy wafer is excessively low, thermal stress is concentrated on the circumference of the soy wafer, so that slip occurs at the circumference of the soy wafer, and the heat supplied to the lower center of the soy wafer is excessive. As the number increases, as the thermal stress is concentrated in the center of the soy wafer, slip may occur in the center of the soy wafer, and it is preferable that the soy wafer is appropriately defined within the above-mentioned range.

Referring to the numerical values shown in FIGS. 4A to 4B, 79% to 71% of the power supplied to the lower lamps with respect to the amount of power that can be supplied to the upper / lower lamps during the first preset time t2. For the amount of power that can be supplied to the upper lamps, 58% of the power is supplied to the upper internal lamps, and for the amount of power that can be supplied to the lower lamps, Adjusted to 18%.

That is, as the size of the power supplied to the lower lamps is higher than 79% with respect to the size of the power that can be supplied to the upper / lower lamps, a slip of 40 mm or more occurs in the center of the soy wafer, and the size of the power is increased. The lower the 71% or less, the more than 1606mm slip occurs in the circumference of the soy wafer. Therefore, as the amount of heat supplied from the bottom of the soy wafer is excessive, thermal stress is concentrated in the center of the soy wafer, so that slip occurs in the center of the soy wafer. As the thermal stress is concentrated at the circumference of, the slip may occur at the circumference of the soy wafer, and it is preferable to be appropriately limited within the above-mentioned range.

As a result, during the initial first set time t1 of depositing the epi layer, the supply power of the lower lamps is limited to the range of 72-78% for the supply power of the entire lamps, and the lower internal lamps for the supply power of the lower lamps. The supply power of may be limited to 17 to 27% range. At this time, the supply power of the lower inner lamp to the supply power of the lower outer lamp may be limited to 21 ~ 37% range, which is set higher than the conventional.

Figure 5 is a graph showing the thickness of the epi layer deposited by a conventional method for producing an epi layer of a soy wafer according to the present invention, Figures 6a and 6b is a conventional deposition method of the epi layer of a soy wafer according to the present invention A plan view of the epi layer is shown.

According to the conventional method of manufacturing an epi layer of a soy wafer, the power supplied to the lamps is controlled by only one step, and the size of the power supplied to the lower lamps with respect to the size of the power that can be supplied to the upper / lower lamps. 58%, for the amount of power that can be supplied to the upper lamps 72% for the amount of power that can be supplied to the upper lamps, and for the amount of power that can be supplied to the lower lamps The epi layer was grown while controlling the size of 17.5%.

In the method of manufacturing an epi layer of the soy wafer according to the present invention, the power supplied to the lamps is controlled in two stages, and the size of the power that can be supplied to the upper / lower lamps during the first preset time t1 is determined. 76% of the power supplied to the lower lamps, 58% of the power supplied to the upper internal lamps relative to the amount of power that can be supplied to the upper lamps, and of the power that can be supplied to the lower lamps Control the amount of power supplied to the lower internal lamp to 26% for The epi layer is grown thicker in the center than the circumference of the soy wafer, and then the size of the power supplied to the lower lamps is compared with the size of the power that can be supplied to the upper / lower lamps for the second set time t2. 58% of the power supplied to the upper lamps relative to the amount of power that can be supplied to the upper lamps 72%, of the power to the lower lamps relative to the amount of power supplied to the lower lamps By controlling the size to 17.5%, the epi layer grows thicker on the circumference than the center of the SOI wafer to match the overall thickness.

As shown in FIG. 5, the epi layer of the soy wafer manufactured according to the conventional manufacturing method is rapidly thick at the center side, whereas the epi layer of the soy wafer manufactured according to the manufacturing method of the present invention is thick at the center side. It can be seen that is lowered relatively. In general, the thickness uniformity of the epitaxial layer (Thickness Uniformity) to satisfy the average within 3% to guarantee the quality, while the uniformity of the epi layer thickness of the Soy wafer made according to the prior art is 3.59%, it is difficult to guarantee the quality, The uniformity of the epi layer thickness of the soy wafer manufactured according to the present invention is 2.62% to guarantee the quality.

In addition, the flatness (flatness) of the Soy wafer is usually expressed by the Site Frontside Least Squares Focal Plane Range metric (SFQR) value, and the quality must be satisfied within the SFQR Max 0.16 μm.

As shown in FIG. 6A, the epi layer of the soy wafer manufactured according to the conventional manufacturing method cannot guarantee the quality to the level of SFQR Max 0.20 to 0.25 μm, whereas the epi layer of the soy wafer manufactured according to the manufacturing method of the present invention. The layer plan is not only improved to SFQR Max 0.08 ~ 0.10µm level but also can guarantee quality.

The present invention heats the center of the soy wafer to a temperature higher than the circumference portion while the source gas is introduced, and heats the circumference of the soy wafer to a temperature higher than the center portion, thereby reducing slip of the soy wafer, which is frequently generated at the beginning of deposition. In addition, the defect rate can be reduced, the quality of the soy wafer can be maintained uniformly, and the flatness can be increased.

In addition, the present invention can easily adjust the position and thickness of the source gas is deposited on the soy wafer by adjusting the lamps and the power supplied to the heating by dividing the center / circumference in the top / bottom of the soy wafer, the desired specification easily A soy wafer having an epitaxial layer of can be produced.

110: rotating plate 120: upper lamp
130: lower lamp 140: power control unit

Claims (6)

A loading step in which the soy wafer is loaded;
A deposition step of growing an epitaxial layer as the source gas is injected into the soy wafer loaded in the loading step;
A first heating step of heating the center of the soy wafer to a temperature higher than the circumference of the soy wafer during the initial first set time t1 of the deposition step; And
And a second heating step of heating the circumference of the soy wafer to a temperature higher than the center of the soy wafer for a second predetermined time t2 after the first heating step, in which the deposition step is completed.
The first heating step controls the power supplied to the lower lamps heating the lower surface of the soy wafer in the range of 72 to 78% with respect to the total power supplied to the upper / lower lamps heating the upper and lower surfaces of the soy wafer. Soy wafer epilayer manufacturing method comprising a process. The method of claim 1,
The loading step is a soy wafer epitaxial manufacturing method comprising the step of rotatably supporting the soy wafer. delete The method of claim 1,
The first heating step includes controlling power supplied to a lower internal lamp heating a center of a lower surface of the soy wafer in a range of 17 to 27% with respect to power supplied to the lower lamps heating the lower surface of the soy wafer. Soy wafer epi layer manufacturing method. 5. The method of claim 4,
The first heating step controls the power supplied to the lower inner lamp for heating the center of the lower surface of the soy wafer with respect to the power supplied to the lower outer lamp for heating the lower circumference of the soy wafer in the range of 21 to 37%. Soy wafer epilayer manufacturing method comprising. The method of claim 1,
The second heating step includes controlling the power supplied to the lower inner lamp for heating the center of the lower surface of the soy wafer to 21% or less with respect to the power supplied to the lower outer lamp for heating the lower circumference of the soy wafer. Soy wafer epi layer manufacturing method.

Images