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KR101332332B1 - Semiconductor package having electromagnetic waves shielding means, and method for manufacturing the same - Google Patents

Semiconductor package having electromagnetic waves shielding means, and method for manufacturing the same Download PDF

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KR101332332B1
KR101332332B1 KR1020110142940A KR20110142940A KR101332332B1 KR 101332332 B1 KR101332332 B1 KR 101332332B1 KR 1020110142940 A KR1020110142940 A KR 1020110142940A KR 20110142940 A KR20110142940 A KR 20110142940A KR 101332332 B1 KR101332332 B1 KR 101332332B1
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substrate
semiconductor chips
electromagnetic shielding
grounding means
molding compound
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KR20130074869A (en
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김지현
김병진
배재민
남궁윤기
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앰코 테크놀로지 코리아 주식회사
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/268Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293Organic, e.g. plastic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/1815Shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

본 발명은 전자파 차폐수단을 갖는 반도체 패키지 및 그 제조 방법에 관한 것으로서, 더욱 상세하게는 기판에 부착된 각 반도체 칩을 독립적으로 구획화시켜 전자파 차폐를 실현할 수 있도록 한 전자파 차폐수단을 갖는 반도체 패키지 및 그 제조 방법에 관한 것이다.
이를 위해, 본 발명은 기판과, 기판에 도전 가능하게 부착되는 복수의 반도체 칩 및 수동소자를 포함하는 전자파 차폐수단을 갖는 반도체 패키지에 있어서, 상기 복수의 반도체 칩 및 수동소자를 구획하면서 기판에 도전 가능하게 부착되는 접지수단과; 복수의 반도체 칩 및 수동소자를 봉지시키는 동시에 접지수단의 상면을 노출시키면서 기판 위에 몰딩되는 몰딩 컴파운드 수지와; 상기 몰딩 컴파운드 수지의 표면 및 접지수단의 상면에 걸쳐 도포되는 전자파 차폐물질; 을 포함하여 구성된 것을 특징으로 하는 전자파 차폐수단을 갖는 반도체 패키지 및 그 제조 방법을 제공한다.
The present invention relates to a semiconductor package having electromagnetic shielding means and a method of manufacturing the same, and more particularly, to a semiconductor package having electromagnetic shielding means capable of realizing electromagnetic shielding by partitioning each semiconductor chip attached to a substrate independently. It relates to a manufacturing method.
To this end, the present invention provides a semiconductor package having a substrate and electromagnetic wave shielding means including a plurality of semiconductor chips and passive elements that are conductively attached to the substrate, wherein the plurality of semiconductor chips and the passive elements are separated from each other. A grounding means that is possibly attached; A molding compound resin molded on the substrate while encapsulating the plurality of semiconductor chips and the passive elements and exposing the top surface of the grounding means; An electromagnetic shielding material applied over the surface of the molding compound resin and the upper surface of the grounding means; It provides a semiconductor package having an electromagnetic shielding means, and a method for manufacturing the same, characterized in that configured to include.

Description

전자파 차폐수단을 갖는 반도체 패키지 및 그 제조 방법{Semiconductor package having electromagnetic waves shielding means, and method for manufacturing the same}Semiconductor package having electromagnetic waves shielding means, and method for manufacturing the same

본 발명은 전자파 차폐수단을 갖는 반도체 패키지 및 그 제조 방법에 관한 것으로서, 더욱 상세하게는 기판에 부착된 각 반도체 칩을 독립적으로 구획화시켜 전자파 차폐를 실현할 수 있도록 한 전자파 차폐수단을 갖는 반도체 패키지 및 그 제조 방법에 관한 것이다.
The present invention relates to a semiconductor package having electromagnetic shielding means and a method of manufacturing the same, and more particularly, to a semiconductor package having electromagnetic shielding means capable of realizing electromagnetic shielding by partitioning each semiconductor chip attached to a substrate independently. It relates to a manufacturing method.

잘 알려진 바와 같이, 각종 전자기기에는 다양한 구조로 제조된 다수개의 반도체 패키지 뿐만아니라, 각종 신호 교환용 전자소자들이 한꺼번에 설치되는 바, 이러한 반도체 패키지와 전자소자들은 전기적인 작동중에 전자파를 발산시키는 것으로 알려져 있다.As is well known, as well as a plurality of semiconductor packages made of various structures in various electronic devices, various signal exchange electronic devices are installed at a time, and these semiconductor packages and electronic devices are known to emit electromagnetic waves during electrical operation. have.

통상, 전자파는 전계(電界)와 자계(磁界)의 합성파로 정의되는데, 도체를 통하여 전류가 흐르게 되면, 이 전류에 의하여 형성되는 전계와 자계를 합쳐서 전자파라고 부른다.Normally, electromagnetic waves are defined as synthesized waves of an electric field and a magnetic field. When a current flows through a conductor, the electric field formed by the current and the magnetic field are called electromagnetic waves.

이러한 전자파들은 인체에 유해한 것으로 밝혀지고 있고, 특히 각종 전자기기의 마더보드에 좁은 간격으로 실장된 반도체 패키지와 기기들로부터 전자파가 발산되면, 그 주변에 실장된 반도체 패키지에까지 직간접으로 영향이 미치게 되어, 칩 회로에 손상을 입히는 것으로 밝혀지고 있다.These electromagnetic waves have been found to be harmful to the human body, and especially when electromagnetic waves are emitted from semiconductor packages and devices mounted on the motherboard of various electronic devices at narrow intervals, they directly or indirectly affect the semiconductor packages mounted around them. It has been found to damage chip circuits.

즉, 마더보드와 같은 기판상의 각 반도체 패키지 및 회로기기들은 전자파를 발생하게 되고, 이러한 전자파의 간섭으로 인하여 전자장치 자체에 회로기능 약화 및 동작 불량 등의 기능 장애 및 고장을 유발하게 된다.That is, each semiconductor package and circuit devices on a substrate such as a motherboard generate electromagnetic waves, and due to the interference of the electromagnetic waves, functional failures and failures such as a weak circuit function and an operation failure occur in the electronic device itself.

최근에는 반도체 제품의 고속화, 고성능화 추세에 따라, 더욱이 시스템-인-패키지(system-in-package; SIP), 멀티 스택 패키지(multi stack package)와 같이 시스템 자체가 패키지 안에 집적되는 구조가 제안되면서 패키지 레벨에서도 전자파 장해 문제가 발생하고 있다.Recently, in accordance with the trend of high speed and high performance of semiconductor products, the system itself is integrated into a package, such as a system-in-package (SIP) and a multi stack package. At the level, there is a problem of electromagnetic interference.

이러한 전자파 장애를 해결하기 위하여, 기판에 칩을 커버하는 메탈 캔(metal can)을 접지 가능하게 탑재하여 전자파를 접지시켜 제거하는 방식과, 전자파 차폐물질을 패키지의 표면에 도포하는 동시에 기판과 전자파 차폐물질을 구리포스트로 접지 가능하게 연결하는 방식 등 여러가지 방안 등이 모색되고 있다.In order to solve this electromagnetic interference, a metal can covering a chip is mounted on the substrate to be grounded to remove the electromagnetic waves by grounding, and the electromagnetic shielding material is applied to the surface of the package while simultaneously shielding the substrate and the electromagnetic waves. There are many ways to find ways to connect materials to ground with copper posts.

그러나, 하나의 기판 위에 로직 칩(logic chip), 복수의 메모리 칩, 수동소자(저항, 인덕터, 커패시터 등) 등의 구성들이 한꺼번에 탑재된 시스템 인 패키지의 경우에는 각 구성들이 기판에 접지 가능하게 탑재되는 하나의 메탈 캔에 의하여 감싸여져 전자파 차폐를 받을 수 있으나, 각 구성들로부터 발산되는 전자파가 각 구성들 상호 간에 영향을 미칠 수 있는 문제점이 있다.However, in the case of a system-in-package in which components such as logic chips, a plurality of memory chips, and passive elements (resistors, inductors, capacitors, etc.) are mounted on one substrate at the same time, the components are grounded on the substrate. It may be wrapped by one metal can to be subjected to electromagnetic shielding, but there is a problem that electromagnetic waves emitted from each component may influence each other.

예를 들어, 로직 칩, 메모리 칩, 수동소자 등이 하나의 전자파 차폐를 위한 메탈 캔으로 감싸여진 상태에서, 외부로부터의 전자파는 메탈 캔에 의하여 차폐될 수 있으나, 하나의 메탈 캔내의 로직 칩에서 발산되는 전자파가 인접한 메모리 칩에 영향을 미치거나 메모리 칩에서 발산되는 전자파가 로직 칩에 영향을 미치는 등의 문제점이 있다.
For example, in a state in which a logic chip, a memory chip, a passive element, and the like are wrapped in a metal can for shielding electromagnetic waves, electromagnetic waves from the outside may be shielded by the metal can, but in a logic chip in one metal can. There are problems that the emitted electromagnetic wave affects the adjacent memory chip or the electromagnetic wave emitted from the memory chip affects the logic chip.

본 발명은 상기와 같은 점을 해결하기 위하여 안출한 것으로서, 하나의 기판에 여러개의 반도체 칩과 수동소자 등이 부착된 경우, 각 반도체 칩과 수동소자 등을 각기 독립적인 공간으로 만들어주는 구획형 전자파 차폐수단을 기판에 접지 가능하게 형성함으로써, 외부로부터의 전자파 차폐는 물론 기판에 부착된 칩과 칩 또는 칩과 수동소자 끼리도 전자파 차폐가 용이하게 이루어질 수 있도록 한 전자파 차폐수단을 갖는 반도체 패키지 및 그 제조 방법을 제공하는데 그 목적이 있다.
The present invention has been made to solve the above-mentioned problems, and, when a plurality of semiconductor chips and passive elements are attached to a single substrate, the compartmentalized electromagnetic waves that make each semiconductor chip and passive elements, etc., become independent spaces. A semiconductor package having electromagnetic shielding means for easily shielding electromagnetic waves from the outside as well as the electromagnetic wave shielding from the outside as well as the shielding means formed on the substrate to be grounded to the substrate, and the manufacture of the semiconductor package and its manufacture The purpose is to provide a method.

상기한 목적을 달성하기 위한 본 발명의 일 구현예는: 기판과, 기판에 도전 가능하게 부착되는 복수의 반도체 칩 및 수동소자를 포함하는 전자파 차폐수단을 갖는 반도체 패키지에 있어서, 상기 복수의 반도체 칩 및 수동소자를 구획하면서 기판에 도전 가능하게 부착되는 접지수단과; 복수의 반도체 칩 및 수동소자를 봉지시키는 동시에 접지수단의 상면을 노출시키면서 기판 위에 몰딩되는 몰딩 컴파운드 수지와; 상기 몰딩 컴파운드 수지의 표면 및 접지수단의 상면에 걸쳐 도포되는 전자파 차폐물질; 을 포함하여 구성된 것을 특징으로 하는 전자파 차폐수단을 갖는 반도체 패키지를 제공한다.An embodiment of the present invention for achieving the above object is a semiconductor package having a substrate, electromagnetic shielding means comprising a plurality of semiconductor chips and passive elements that are conductively attached to the substrate, the plurality of semiconductor chips And grounding means electrically conductively attached to the substrate while partitioning the passive elements; A molding compound resin molded on the substrate while encapsulating the plurality of semiconductor chips and the passive elements and exposing the top surface of the grounding means; An electromagnetic shielding material applied over the surface of the molding compound resin and the upper surface of the grounding means; It provides a semiconductor package having an electromagnetic shielding means, characterized in that configured to include.

본 발명의 일 구현예에서, 상기 접지수단은 복수의 반도체 칩 및 수동소자를 독립적으로 구획하며 기판에 도전 가능하게 부착되는 다수개의 금속 포스트, 솔더볼, 도전성 페이스트, 도전성 에폭시 중 선택된 어느 하나로 채택된 것을 특징으로 한다.In one embodiment of the present invention, the grounding means is independently selected to any one selected from a plurality of metal posts, solder balls, conductive pastes, conductive epoxy that is independently partitioned and electrically conductively attached to a plurality of semiconductor chips and passive elements. It features.

더욱 바람직하게는, 상기 접지수단은 복수의 반도체 칩 및 수동소자를 독립적으로 구획하는 형상으로 구비되어, 기판에 도전 가능하게 부착되는 일체형의 금속 플레이트로 채택된 것을 특징으로 한다.More preferably, the grounding means is provided in a shape that partitions a plurality of semiconductor chips and passive elements independently, and is adopted as an integral metal plate that is conductively attached to a substrate.

또한, 상기 몰딩 컴파운드 수지의 상면에는 접지수단의 상면이 노출되도록 레이저 가공에 의한 그루브가 형성된 것을 특징으로 한다.In addition, the upper surface of the molding compound resin is characterized in that the groove is formed by laser processing so that the upper surface of the grounding means is exposed.

바람직하게는, 상기 전자파 차폐물질은 금속 분말이 혼합된 도전성 페이스트인 것을 특징으로 한다.Preferably, the electromagnetic shielding material is characterized in that the conductive paste mixed with metal powder.

상기한 목적을 달성하기 위한 본 발명의 다른 구현예는: 기판에 복수의 반도체 칩 및 수동소자를 부착하는 단계와; 상기 복수의 반도체 칩 및 수동소자를 독립적으로 구획하는 접지수단을 기판에 도전 가능하게 부착하는 단계와; 복수의 반도체 칩 및 수동소자가 봉지되도록 기판 위에 몰딩 컴파운드 수지를 몰딩하는 단계와; 상기 접지수단이 배열된 라인을 따라 몰딩 컴파운드 수지의 표면에 레이저 가공에 의한 그루브를 형성하는 동시에 그루브를 통하여 접지수단의 상면이 노출되게 하는 단계와; 몰딩 컴파운드 수지의 표면 및 그루브를 통해 노출된 접지수단의 상면에 걸쳐 전자파 차폐물질을 도포하는 단계; 를 포함하는 것을 특징으로 하는 전자파 차폐수단을 갖는 반도체 패키지 제조 방법을 제공한다.
Another embodiment of the present invention for achieving the above object comprises the steps of: attaching a plurality of semiconductor chips and passive elements to the substrate; Conductively attaching a grounding means for independently partitioning the plurality of semiconductor chips and the passive element to a substrate; Molding a molding compound resin on a substrate to encapsulate a plurality of semiconductor chips and passive elements; Forming grooves on the surface of the molding compound resin along the line on which the grounding means is arranged by laser processing and exposing the upper surface of the grounding means through the grooves; Applying an electromagnetic shielding material over the surface of the molding compound resin and the top surface of the grounding means exposed through the groove; It provides a semiconductor package manufacturing method having an electromagnetic shielding means comprising a.

상기한 과제 해결 수단을 통하여, 본 발명은 다음과 같은 효과를 제공한다.Through the above-mentioned means for solving the problems, the present invention provides the following effects.

본 발명에 따르면, 하나의 기판에 여러개의 반도체 칩과 수동소자 등이 부착되는 반도체 패키지의 경우, 각 반도체 칩과 수동소자 등을 각기 독립적인 공간으로 만들어주는 구획형 전자파 차폐수단을 기판에 접지 가능하게 형성함으로써, 외부로부터의 전자파를 접지시켜 제거함은 물론 기판에 부착된 칩과 칩 또는 칩과 수동소자 끼리도 전자파 차폐가 용이하게 이루어질 수 있다.
According to the present invention, in the case of a semiconductor package in which a plurality of semiconductor chips and passive elements are attached to a single substrate, a compartmentalized electromagnetic shielding means for making each semiconductor chip and the passive elements into independent spaces can be grounded on the substrate. By forming it, the electromagnetic wave from the outside can be grounded and removed, as well as the chip and the chip or the chip and passive elements attached to the substrate can be easily shielded.

도 1 및 도 2는 본 발명에 따른 전자파 차폐수단을 갖는 반도체 패키지를 나타내는 사시도 및 단면도,
도 3 및 도 4는 본 발명에 따른 전자파 차폐수단을 갖는 반도체 패키지의 제조 방법을 나타내는 사시도 및 단면도,
도 5는 본 발명에 따른 전자파 차폐수단을 갖는 반도체 패키지의 접지수단 예를 나타내는 사시도.
1 and 2 are a perspective view and a cross-sectional view showing a semiconductor package having an electromagnetic shielding means according to the present invention;
3 and 4 are a perspective view and a cross-sectional view showing a method of manufacturing a semiconductor package having an electromagnetic shielding means according to the present invention;
5 is a perspective view showing an example of the grounding means of the semiconductor package having the electromagnetic shielding means according to the present invention.

이하, 본 발명의 바람직한 실시예를 첨부도면을 참조로 상세하게 설명하기로 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

첨부한 도 1 및 도 2에 도시된 바와 같이, 본 발명에 따른 반도체 패키지는 기판(10)과, 기판(10) 위에 서로 수평 배열을 이루면서 도전 가능하게 부착되는 복수의 반도체 칩(12,14) 및 수동소자(16, 저항, 인덕터, 커패시터 등)를 포함한다,As shown in FIG. 1 and FIG. 2, the semiconductor package according to the present invention includes a substrate 10 and a plurality of semiconductor chips 12 and 14 electrically conductively attached to each other in a horizontal arrangement on the substrate 10. And passive elements 16, resistors, inductors, capacitors, etc.,

특히, 상기 기판(10)에는 전자파를 접지시켜 제거할 수 있는 접지수단(20)이 부착되는 바, 이 접지수단(20)은 복수의 반도체 칩(12,14) 및 수동소자(16)를 독립적으로 구획시키면서 기판(10)에 도전 가능하게 부착된다.In particular, the substrate 10 is attached to the ground means 20 that can be removed by grounding the electromagnetic wave, the ground means 20 is independent of the plurality of semiconductor chips 12, 14 and the passive element 16 The substrate 10 is electrically conductively attached to the substrate 10 while being partitioned by the substrate.

즉, 상기 접지수단(20)은 기판(10)에 부착된 복수의 반도체 칩(12,24)의 경계부를 따라 부착됨으로써, 각 반도체 칩(12,24)들이 공간적으로 서로 분리되는 상태가 된다.That is, the grounding means 20 is attached along the boundary of the plurality of semiconductor chips 12 and 24 attached to the substrate 10, so that the semiconductor chips 12 and 24 are separated from each other spatially.

바람직하게는, 상기 접지수단(20)은 기판(10)의 복수의 반도체 칩(12,24)의 경계부를 따라 부착되는 다수개의 금속 포스트(20a)를 이용할 수 있고, 또한 첨부한 도 5에 도시된 바와 같이 기판(10)에 도전 가능하게 부착되는 솔더볼(20b), 도전성 페이스트 또는 도전성 에폭시(20c) 등을 이용할 수 있다.Preferably, the grounding means 20 may use a plurality of metal posts 20a attached along the boundaries of the plurality of semiconductor chips 12, 24 of the substrate 10, and also shown in FIG. As described above, a solder ball 20b, a conductive paste, a conductive epoxy 20c, or the like that is conductively attached to the substrate 10 may be used.

더욱 바람직하게는, 상기 접지수단(20)은 복수의 반도체 칩(12,14) 및 수동소자(16)를 공간적으로 완전하게 구획하는 형상(예를 들어, 도 5에서 보듯이 T자 형상)으로 구비된 것으로서, 기판(10)에 도전 가능하게 부착되는 일체형의 금속 플레이트(20d)를 이용할 수 있다.More preferably, the grounding means 20 has a shape (for example, a T-shape as shown in FIG. 5) that completely partitions the plurality of semiconductor chips 12 and 14 and the passive element 16. As provided, it is possible to use an integral metal plate 20d attached to the substrate 10 so as to be conductive.

이때, 상기 기판(10) 위에 몰딩 컴파운드 수지(18)가 몰딩됨으로써, 기판(10)에 부착된 각 반도체 칩(12,14)과 수동소자(16), 그리고 접지수단(20) 등이 봉지되는 상태가 되고, 각 반도체 칩(12,14)은 접지수단(20)에 의하여 상호 분리되는 상태가 된다.In this case, the molding compound resin 18 is molded on the substrate 10 to encapsulate the semiconductor chips 12 and 14, the passive element 16, and the grounding means 20 attached to the substrate 10. And the semiconductor chips 12 and 14 are separated from each other by the grounding means 20.

또한, 상기 몰딩 컴파운드 수지(18)의 상면에는 접지수단(20)이 부착된 라인을 따라 레이저 가공에 의한 그루브(24, groove)가 형성되며, 이에 몰딩 컴파운드 수지(18)의 그루브(24)를 통하여 접지수단(20)의 상면이 노출되는 상태가 된다.In addition, grooves 24 are formed on the upper surface of the molding compound resin 18 by laser processing along a line to which the grounding means 20 is attached, thereby forming the grooves 24 of the molding compound resin 18. Through this, the upper surface of the grounding means 20 is exposed.

특히, 상기 몰딩 컴파운드 수지(18)의 표면과, 몰딩 컴파운드 수지(18)에 형성된 그루브(24)를 통하여 노출된 접지수단(20)의 상면에 걸쳐 전자파 차폐물질(22)로서, 금속 분말이 혼합된 도전성 페이스트가 분사되어 도포된다.In particular, metal powder is mixed as the electromagnetic shielding material 22 over the surface of the molding compound resin 18 and the upper surface of the grounding means 20 exposed through the grooves 24 formed in the molding compound resin 18. The conductive paste is sprayed and applied.

따라서, 접지수단(20)에 의하여 각 반도체 칩(12,14) 및 수동소자(16) 등이 독립적으로 분리된 상태에서, 각 반도체 칩 상호간 또는 반도체 칩과 수동소자 상호 간에 영향을 미치는 전자파를 접지수단에서 차폐하게 되고, 물론 외부로부터 전달되는 전자파도 접지수단에서 접지시켜 용이하게 제거될 수 있다.Therefore, in the state in which each of the semiconductor chips 12 and 14 and the passive element 16 are independently separated by the grounding means 20, the electromagnetic waves affecting each of the semiconductor chips or between the semiconductor chip and the passive element are grounded. The shield is shielded by the means, and of course electromagnetic waves transmitted from the outside can be easily removed by grounding the ground means.

여기서, 상기한 구성으로 이루어진 본 발명의 반도체 패키지에 대한 제조 방법을 첨부한 도 3 및 도 4를 참조로 살펴보면 다음과 같다.Here, referring to Figures 3 and 4 attached to the manufacturing method for the semiconductor package of the present invention having the above configuration are as follows.

먼저, 기판(10)에 복수의 반도체 칩(12,14) 및 수동소자(16)를 도전 가능하게 부착하는 단계가 선행된다.First, the step of electrically attaching a plurality of semiconductor chips 12 and 14 and a passive element 16 to the substrate 10 is preceded.

다음으로, 상기 복수의 반도체 칩(12,14) 및 수동소자(16)를 독립적으로 구획하는 접지수단(20)을 기판(10)에 도전 가능하게 부착한다.Next, a grounding means 20 for independently partitioning the plurality of semiconductor chips 12 and 14 and the passive element 16 is attached to the substrate 10 so as to be conductive.

즉, 기판(10)에 부착된 복수의 반도체 칩(12,14) 사이, 그리고 반도체 칩(12,14)과 수동소자(16) 사이에 다수개의 금속 포스트(20a)를 부착하거나, 첨부한 도 5에 도시된 바와 같이 다수개의 솔더볼(20b)을 부착하거나, 또는 도전성 페이스트 또는 도전성 에폭시(20c)를 도포하여 경화시키는 방법이 선택적으로 이루어진다.That is, a plurality of metal posts 20a are attached or attached between the plurality of semiconductor chips 12 and 14 attached to the substrate 10 and between the semiconductor chips 12 and 14 and the passive element 16. As shown in FIG. 5, a method of attaching a plurality of solder balls 20b or applying a conductive paste or a conductive epoxy 20c to harden is optionally performed.

또는, 상기 접지수단(20)으로서, 첨부한 도 5에 도시된 바와 같이 복수의 반도체 칩(12,14) 및 수동소자(16)를 독립적으로 구획할 수 있는 일체형의 금속 플레이트(20d, 예를 들어 T자형의 평면 형상을 갖는 금속 플레이트)를 기판(10)에 도전 가능하게 부착할 수 있다.Alternatively, as the grounding means 20, an integrated metal plate 20d capable of independently partitioning the plurality of semiconductor chips 12 and 14 and the passive element 16 as shown in FIG. For example, a metal plate having a T-shaped planar shape) can be electrically attached to the substrate 10.

다음으로, 상기 복수의 반도체 칩(12,14) 및 수동소자(16)를 외부로부터 보호하기 위하여 기판(10) 위에 몰딩 컴파운드 수지(18)를 몰딩하는 단계가 진행됨으로써, 복수의 반도체 칩(12,14) 및 수동소자(16) 등이 몰딩 컴파운드 수지(18)에 의하여 감싸여지며 봉지되는 상태가 되도록 한다.Next, in order to protect the plurality of semiconductor chips 12 and 14 and the passive element 16 from the outside, the molding compound resin 18 is molded on the substrate 10, thereby providing a plurality of semiconductor chips 12. 14 and the passive element 16 are wrapped and encapsulated by the molding compound resin 18.

이어서, 상기 접지수단(20)의 상면을 노출시키기 위하여, 몰딩 컴파운드 수지(18)의 상면에 레이저 가공을 실시하여 접지수단(20)이 배열된 라인을 따라 그루브(24)를 형성하는 단계가 진행된다.Subsequently, in order to expose the top surface of the grounding means 20, laser processing is performed on the top surface of the molding compound resin 18 to form the grooves 24 along the line where the grounding means 20 are arranged. do.

마지막으로, 상기 몰딩 컴파운드 수지(18)의 전체 표면과, 몰딩 컴파운드 수지(18)의 그루브(24)를 통해 외부로 노출된 접지수단(20)의 상면에 걸쳐 전자파 차폐물질(22)로서, 금속 분말이 혼합된 도전성 페이스트를 분사하여 도포해줌으로써, 본 발명의 전자파 차폐수단을 갖는 반도체 패키지가 완성된다.
Finally, as the electromagnetic shielding material 22 over the entire surface of the molding compound resin 18 and the upper surface of the grounding means 20 exposed to the outside through the groove 24 of the molding compound resin 18, By spraying and applying the conductive paste mixed with the powder, the semiconductor package having the electromagnetic shielding means of the present invention is completed.

10 : 기판
12,14 : 반도체 칩
16 : 수동소자
18 : 몰딩 컴파운드 수지
20 : 접지수단
20a : 금속 포스트
20b : 솔더볼
20c : 도전성 페이스트 또는 도전성 에폭시
20d : 금속 플레이트
22 : 전자파 차폐물질
24 : 그루브
10: substrate
12,14: Semiconductor Chip
16: passive element
18: Molding compound resin
20: grounding means
20a: metal post
20b: Solder Ball
20c: conductive paste or conductive epoxy
20d: metal plate
22: electromagnetic shielding material
24 groove

Claims (9)

기판(10)과, 기판(10)에 도전 가능하게 부착되는 복수의 반도체 칩(12,14) 및 수동소자(16)를 포함하는 전자파 차폐수단을 갖는 반도체 패키지에 있어서,
상기 복수의 반도체 칩(12,14) 및 수동소자(16)를 공간적으로 완전하게 구획하는 접지수단(20)으로서 T자 형상으로 구비되어 기판(10)에 도전 가능하게 부착되는 일체형의 금속 플레이트(20d)와;
복수의 반도체 칩(12,14) 및 수동소자(16)를 봉지시키는 동시에 접지수단(20)의 상면을 노출시키면서 기판(10) 위에 몰딩되는 몰딩 컴파운드 수지(18)와;
상기 금속 플레이트(20d)의 상면이 노출되도록 몰딩 컴파운드 수지(18)의 상면에 레이저 가공에 의하여 형성되는 그루브(24)와;
상기 몰딩 컴파운드 수지(18)의 표면 및 접지수단(20)의 상면에 걸쳐 도포되는 전자파 차폐물질(22);
을 포함하여 구성된 것을 특징으로 하는 전자파 차폐수단을 갖는 반도체 패키지.
In a semiconductor package having an electromagnetic shielding means including a substrate 10, a plurality of semiconductor chips 12, 14 and a passive element 16 conductively attached to the substrate 10,
An integrated metal plate provided in a T-shape and electrically attached to the substrate 10 as a grounding means 20 for spatially and completely partitioning the plurality of semiconductor chips 12 and 14 and the passive element 16. 20d);
A molding compound resin 18 molded on the substrate 10 while encapsulating the plurality of semiconductor chips 12, 14 and the passive element 16 while exposing the top surface of the grounding means 20;
A groove 24 formed by laser machining on the upper surface of the molding compound resin 18 so that the upper surface of the metal plate 20d is exposed;
An electromagnetic shielding material 22 applied over the surface of the molding compound resin 18 and the upper surface of the grounding means 20;
Semiconductor package having an electromagnetic shielding means characterized in that comprises a.
삭제delete 삭제delete 삭제delete 삭제delete 기판(10)에 복수의 반도체 칩(12,14) 및 수동소자(16)를 부착하는 단계와;
상기 복수의 반도체 칩(12,14) 및 수동소자(16)를 공간적으로 완전하게 구획하는 접지수단(20)인 T자 형상을 갖는 일체형의 금속 플레이트(20d)를 기판(10)에 도전 가능하게 부착하는 단계와;
복수의 반도체 칩(12,14) 및 수동소자(16), 금속 플레이트(20d)가 봉지되도록 기판(10) 위에 몰딩 컴파운드 수지(18)를 몰딩하는 단계와;
상기 접지수단(20)의 상면이 노출되도록 접지수단(20)이 배열된 라인을 따라 몰딩 컴파운드 수지(18)의 표면에 레이저 가공에 의한 그루브(24)를 형성하는 단계와;
상기 몰딩 컴파운드 수지(18)의 표면 및 그루브(24)를 통해 노출된 접지수단(20)의 상면에 걸쳐 전자파 차폐물질(22)을 도포하는 단계;
를 포함하는 것을 특징으로 하는 전자파 차폐수단을 갖는 반도체 패키지 제조 방법.
Attaching a plurality of semiconductor chips (12, 14) and passive elements (16) to the substrate (10);
An integrated metal plate 20d having a T-shape, which is a grounding means 20 for spatially and completely partitioning the plurality of semiconductor chips 12 and 14 and the passive element 16, may be electrically conductive to the substrate 10. Attaching;
Molding a molding compound resin (18) on the substrate (10) to seal the plurality of semiconductor chips (12, 14), the passive elements (16), and the metal plate (20d);
Forming a groove (24) by laser machining on the surface of the molding compound resin (18) along a line where the grounding means (20) is arranged so that the upper surface of the grounding means (20) is exposed;
Applying an electromagnetic shielding material (22) over the surface of the molding compound resin (18) and the top surface of the grounding means (20) exposed through the groove (24);
Method of manufacturing a semiconductor package having an electromagnetic shielding means comprising a.
삭제delete 삭제delete 삭제delete
KR1020110142940A 2011-12-27 2011-12-27 Semiconductor package having electromagnetic waves shielding means, and method for manufacturing the same KR101332332B1 (en)

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US9355969B2 (en) 2014-09-05 2016-05-31 Samsung Electronics Co., Ltd. Semiconductor package
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US10872866B2 (en) 2018-10-08 2020-12-22 Advanced Semiconductor Engineering, Inc. Semiconductor package and method of manufacturing the same
US11638346B2 (en) 2020-08-11 2023-04-25 Samsung Electro-Mechanics Co., Ltd. Component package and printed circuit board for the same

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US10784230B2 (en) * 2016-11-15 2020-09-22 Advanced Semiconductor Engineering, Inc. Compartment shielding for warpage improvement
US10418332B2 (en) * 2017-03-13 2019-09-17 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming partition fence and shielding layer around semiconductor components
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US11450618B2 (en) 2020-01-17 2022-09-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of compartment shielding using bond wires
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KR20200013373A (en) 2018-07-30 2020-02-07 삼성전기주식회사 Electronic component module and manufacturing mehtod thereof
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