KR101328831B1 - Liquid crystal display device and method driving of the same - Google Patents

Abstract

A liquid crystal display device capable of improving the temperature of a driver IC is disclosed.

According to an exemplary embodiment of the present invention, a liquid crystal display includes: a liquid crystal panel in which a plurality of gate lines and a plurality of data lines are arranged; a data driver for supplying pixel data voltages inputted to pixels on the liquid crystal panel by one line; And an gradation change adaptive polarity inversion signal generator for outputting, to the data driver, a polarity inversion signal having a different period depending on the degree of gradation change between pixels of the pixel data from the input unit. It is done.

Power Consumption, Heat Generation Temperature, Polarity Reversal Signal

Description

[0001] The present invention relates to a liquid crystal display device and a driving method thereof,

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view showing a liquid crystal display device according to the present invention. Fig.

2 is a view illustrating in detail the data change detection unit of FIG.

3 is a view illustrating in detail the polarity inversion signal selection unit of FIG.

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

102: liquid crystal panel 104: gate driver

106: data driver

108: gradation change adaptive polarity inversion signal generator

110: frame delay unit 112: data change detection unit

114: polarity inversion signal output unit 116: timing controller

120: line delay 122: subtraction part

124: first comparison unit 126: first cumulative counter

128: first latch portion 130: second comparison portion

132: second cumulative counter 134: second latch

136: third comparison unit 138: first divider

140: second frequency divider 142: multiplexer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof capable of improving the heat generation temperature of a driver IC.

Liquid crystal display device (Liquid crystal display device) is a trend that the application range is gradually widened due to the characteristics such as light weight, thin, low power consumption. In accordance with this trend, the liquid crystal display device is used for office automation equipment, audio / video equipment, and the like. On the other hand, the liquid crystal display device displays the desired image on the screen by adjusting the transmission amount of the light beam according to the image signal applied to the plurality of control switches arranged in a matrix form.

Liquid crystal display devices having such a configuration are being replaced from cathode ray tube (CRT) displays due to their characteristics of thin type and low power consumption. Background of this replacement is a technological innovation in improving the image quality of the liquid crystal display. In particular, there is a strong demand for moving picture display represented by television images in recent years, and improvements have been made by liquid crystal materials and driving methods. In the liquid crystal display, when a specific still image is driven for a long time and another image is displayed, an afterimage in which the previous image pattern remains is generated. The afterimage occurs when a DC voltage is applied to the liquid crystal layer between the pixel electrode and the common electrode of the liquid crystal display. Since the liquid crystal of the liquid crystal display basically has refractive index anisotropy and is easily deteriorated by the DC voltage, such an afterimage is likely to occur, and AC driving is usually performed to prevent it.

In the liquid crystal display, the afterimage phenomenon may be intensified if the polarity of the voltage applied to the pixel electrode and the common electrode is always a fixed value. Driven by.

However, since the cathode ray tube (CRT) is an impulse type light emission by scanning an electron gun, the liquid crystal display device is a hold type light emission using a backlight system using a linear lamp (fluorescent lamp) as an illumination light source, so that complete moving picture display is difficult. That is, when moving picture display is performed with a liquid crystal display device, so-called motion blurring (image outline deterioration) occurs due to the hold characteristic, and image quality is deteriorated.

Accordingly, a liquid crystal display device is disclosed which processes input data at a high frequency in order to prevent motion blur (motion image contour deterioration) of moving image display. For example, in the case of a liquid crystal display device driven at a high frequency of 120 Hz, the data switching frequency is increased. In order to process data at a high frequency to prevent motion blur for a predetermined period, one frame increases the data switching frequency for processing the data. When the data switching frequency for processing the data is increased, the heat generation temperature of the data driver IC for processing the data is increased by the increased frequency.

The following formula relates to the heat generation of the data driver IC.

P: Power consumption N: Number of data lines

C: Load F: Switching Frequency

V: switching voltage level

As described above, factors influencing the power consumption of the data driver IC include the number of data lines, the switching frequency for switching the load and data along the data lines, and the switching voltage level of the data. The number of data lines and switching voltage levels of loads and data according to data lines are determined, and the switching frequency is a variable. Therefore, the most fluid factor affecting the power consumption of the data driver IC is the data switching frequency. When the data switching frequency is increased, power consumption of the data driver IC is increased.

As such, when the power consumption of the data driver IC increases, the heat generation temperature of the data driver IC also increases. When the heat generation temperature of the data driver IC increases, there is a problem in that the driving circuits inside the data driver IC are damaged or damaged, causing the data driver IC to malfunction.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device and a driving method thereof capable of improving the heat generation temperature of a driver IC.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes a liquid crystal panel in which a plurality of gate lines and a plurality of data lines are arranged, and data for supplying pixel data voltages to be input to pixels on the liquid crystal panel for one line. A gray level adaptive adaptive polarity inversion which outputs to the data driver a polarity inversion signal having a period different from the driver, an input unit for inputting pixel data supplied to the data driver, and pixel data from the input unit according to the degree of grayscale change between pixels. It characterized in that it comprises a signal generator.

A driving method of a liquid crystal display device according to the present invention which can achieve the above object is a driving method of a liquid crystal display device including a liquid crystal panel in which a plurality of gate lines and a plurality of data lines are arranged, and inputs pixel data from the outside. And supplying pixel data voltages inputted to the pixels on the liquid crystal panel by one line using the pixel data, and detecting whether the gray level change between pixels is severe or large using the pixel data. And outputting a control signal according to the control signal and selectively outputting a polarity inversion signal having a different period according to the control signal.

Hereinafter, embodiments according to the present invention will be described with reference to the accompanying drawings.

1 is a view showing a liquid crystal display device according to the present invention.

As shown in FIG. 1, a liquid crystal display according to the present invention includes a liquid crystal panel 102 for displaying an image and a data driver for driving a plurality of data lines DL1 to DLm on the liquid crystal panel 102. 106, a gate driver 104 for driving a plurality of gate lines GL1 to GLn on the liquid crystal panel 102, and a timing controller for controlling driving timing of the data and gate drivers 106 and 104. 116 and a frame delay unit 110 for delaying data supplied from the outside for one frame.

The liquid crystal panel 102 includes pixels formed in regions divided by a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm. Each of these pixels includes a thin film transistor (TFT) formed at an intersection between a corresponding gate line GL and a corresponding data line DL and a thin film transistor TFT formed between the thin film transistor TFT and the common electrode (Vcom) And a cell Clc. The thin film transistor TFT switches the pixel data voltage to be supplied to the corresponding liquid crystal cell Clc from the corresponding data line DL in response to a gate scan signal on the corresponding gate line GL. The liquid crystal cell Clc includes a common electrode facing each other with a liquid crystal layer interposed therebetween, and a pixel electrode connected to the thin film transistor TFT. The liquid crystal cell Clc charges the pixel data voltage supplied via the corresponding thin film transistor TFT. In addition, the voltage charged in the liquid crystal cell Clc is updated each time the corresponding thin film transistor TFT is turned on. In addition, each of the pixels on the liquid crystal panel 102 includes a storage capacitor Cst connected between the thin film transistor TFT and the previous gate line. The storage capacitor Cst minimizes a natural decrease in the voltage charged in the liquid crystal cell Clc.

The gate driver 104 correspondingly supplies a plurality of gate scan signals to the plurality of gate lines GL1 to GLn in response to gate control signals from the timing controller 116. The plurality of gate scan signals cause the plurality of gate lines GL1 to GLn to sequentially enable one horizontal synchronizing signal period.

The data driver 106 generates a plurality of pixel data voltages whenever one of the plurality of gate lines DL1 to DLm is enabled in response to data control signals from the timing controller 116. Supply to a plurality of data lines DL1 to DLm on the liquid crystal panel 102, respectively. To this end, the data driver 106 inputs pixel data from the timing controller 116 by one line, and converts one line of pixel data into pixel data voltages in an analog form using a gamma voltage set. To convert. The pixel data voltages output from the data driver 106 alternately have a negative polarity and a positive polarity at every frame period. In another form, the pixel data voltages may alternate between the negative polarity and the positive polarity every line period (ie, the period of the horizontal synchronization signal). The generation of these negative and positive pixel data voltages is determined by the logical value of the polarity reversal signal POL.

The timing controller 116 is a data clock DCLK, a horizontal synchronization signal Hsync, a vertical synchronization signal from an external system (for example, a graphic module of a computer system or an image demodulation module of a television reception system), which is not shown. The gate control signals GCS, the data control signals DCS, and the polarity inversion signal POL are generated using the Vsync and the data enable signal DE. The gate control signals GCS are supplied to the gate driver 104 and the data control signals DCS and polarity reversal signals POL are supplied to the data driver 106. In addition, the pixel data of the frame rearranged by the timing controller 116 is sequentially supplied to the data driver 106 by one line.

The frame delay unit 110 delays the input data Data from the outside for one frame and supplies it to the timing controller 116. The reason why the data delayed by the frame delay unit 110 is delayed for one frame is whether the polarity signal controller 112 has data having a large gray level difference using the data Data input for one frame. This is to adjust the timing at which the input data Data from the outside is supplied to the data driver 106.

In the liquid crystal display of FIG. 1, the gray scale change adaptive polarity inversion signal generator for generating a polarity inversion signal POL having a different period by detecting whether the gray scale change between pixels is large or severe using data input from the outside ( 108). The gradation change adaptive polarity inversion signal generator 108 may be included in the timing controller 116.

The gradation change adaptive polarity inversion signal generator 108 may be supplied to the data driver 106 according to a signal supplied from the data change detection unit 112 and the data change detection unit 112 to detect the gradation change between pixels. A polarity inversion signal output unit 114 for outputting a polarity inversion signal POL is further provided.

The data change detector 112 determines whether there is a large or severe gray level change between the line and the pixel, and compares the comparison signal corresponding to the comparison result with a reference value determined according to the user's request. It generates and supplies to the polarity inversion signal output unit 114.

Detailed descriptions of the data change detection unit 112 and the polarity inversion signal output unit 114 will be described later with reference to FIGS. 2 and 3, respectively.

2 is a view illustrating in detail the data change detector of FIG. 1.

As illustrated in FIG. 2, the data change detection unit 112 calculates a line delay unit 120 and a subtraction unit 122 and a subtraction unit 122 that respond to data input from the outside. The first comparison unit 124 compares a value with a predetermined reference value, and the first accumulation counter 126 and the first accumulation counter 126 count the values output from the first comparison unit 124. A first latch unit 128 for latching a value for a predetermined period of time and a second comparison unit 130 for comparing the value output from the first latch unit 128 with a predetermined reference value.

In addition, the data change detection unit 112 calculates the second cumulative counter 132 for counting the value output from the second comparator 130 and the value counted by the second cumulative counter 132 for a predetermined period of time. And a second latching unit 134 for latching, and a third comparing unit 136 for comparing a value output from the second latching unit 134 with a predetermined reference value.

The line delay unit 120 delays data input from the outside by one line. Data delayed by one line by the line delay unit 120 is referred to as first data. The data for one line currently input from the outside is called second data. The first and second data are supplied to the subtractor 122.

The subtraction unit 122 calculates a difference value between the first data supplied from the line delay unit 120 and the second data supplied from the outside. In detail, the subtractor 122 calculates a difference between the pixel data grayscale value of the first data and the pixel data grayscale value of the second data, and supplies the calculated value to the first comparator 124. . As the value output from the subtractor 122 increases, the pixel data gray level difference between the first and second data increases.

The first comparison unit 124 compares the value supplied from the subtraction unit 122 with a predetermined reference gray value (for example, 30 gray) and according to the comparison result, a specific logic (for example, high). Or low) to output the first comparison signal to the accumulation counter 126. When the value supplied from the subtractor 122 is greater than the reference gray scale value, the first comparator 124 outputs a high first comparison signal and outputs the first comparable signal from the subtractor 122. When the supplied value is smaller than the reference gray scale value, the first comparator 124 outputs a low first comparison signal. The first comparator 124 outputs a first high comparison signal only when the gray level difference is large or large for each pixel on two adjacent lines. The first comparator 124 outputs a low first comparison signal when the gray level difference is small or the same for each pixel on two adjacent lines.

The first cumulative counter 126 increases the number of times the first high comparison signal is input from the first comparator 124 by one in response to the data clock signal DCLK. In addition, the first accumulation counter 126 does not count when a low first comparison signal is input from the first comparison unit 124. The first accumulation counter 126 counts the number of the first high comparison signals in one horizontal period. To this end, the first accumulation counter 126 initializes the count value to the horizontal synchronization signal (Hsync). The value incremented by one in the first accumulation counter 126 is supplied to the first latch unit 128.

The first latch unit 128 samples, by the first accumulation counter 126, the number of pixel data having a large gray level difference during one horizontal period, and compares the number of pixel data having a large gray level difference with the second comparison unit. Supply to 130. To this end, the first latch unit 128 latches the number of pixel data having a large gray level difference from the first accumulation counter 126 toward the second comparator 130 in response to a horizontal synchronization signal Hsync. do. More specifically, the first latch unit 128 includes pixel data having a large gray level difference at a specific edge (for example, rising or falling) of the horizontal synchronization signal Hsync indicating entry into the blanking period from the scanning period. Latch the number of.

The second comparison unit 130 compares the number of pixel data having a large gray level difference from the first latch unit 128 with a predetermined number of reference pixels. When the number of pixel data having a large gray level difference is greater than a logic value of the number of reference pixels, the second comparator 130 generates a second high comparison signal indicating that a change in image is a large pattern. . On the contrary, when the number of pixel data having a large gradation difference is lower than the logical value of the number of reference pixels (that is, the number of reference pixels), the second comparator 130 indicates a low pattern of image change. Generate a second comparison signal of.

The second comparison unit 130 compares the number of pixel data having a large gradation difference from the first latch unit 128 with a predetermined number of reference pixels, and according to the comparison result, a specific logic (high or low) A second comparison signal is output. The second comparison signal output from the second comparison unit 130 is supplied to the second accumulation counter 132.

The second cumulative counter 132 increases the number of times the second high comparison signal is input from the second comparator 130 by one in response to the horizontal synchronization signal Hsync. In addition, the second cumulative counter 132 does not count when a low second comparison signal is input from the second comparator 130. The second cumulative counter 132 counts the number of second high comparison signals for one frame. To this end, the second accumulation counter 132 initializes the count value to the vertical synchronization signal Vsync. The value incremented by one in the second accumulation counter 132 is supplied to the second latch unit 134.

The second latch unit 134 samples, by the second accumulation counter 132, the number of lines having a large amount of pixel data having a large gray level difference during one frame, and the third comparison unit 136. To supply. To this end, the second latch unit 134 may determine the number of lines having a large amount of pixel data having a large gray level difference from the second accumulation counter 132 in response to the vertical synchronization signal Vsync. 136). More specifically, the second latch unit 134 includes pixel data having a large gray level difference at a specific edge (for example, rising or falling) of the vertical synchronization signal Vsync indicating the entry into the blanking period between syringes. Latch the number of lines that have a lot.

The third comparison unit 136 compares the number of lines having a large amount of pixel data having a large gray level difference from the second latch unit 134 with a predetermined reference line number and specifies a specific logic according to the comparison result. For example, a third comparison signal (high or low) is generated. When the number of lines having a large amount of pixel data having a large gray level difference is larger than the reference line number, the third comparison unit 136 generates a high third comparison signal indicating that a change in image is a large pattern. do. On the contrary, if the number of lines having a large amount of pixel data having a large gradation difference is lower than the reference line number, the third comparison unit 136 may provide a low third comparison signal indicating that the pattern has little change in the image. Occurs. The high or low third comparison signal generated by the third comparison unit 136 is supplied to the polarity signal output unit 114 shown in FIG. 1.

3 is a view showing in detail the polarity inversion signal output unit of FIG.

As shown in FIG. 1 and FIG. 3, the polarity inversion signal output unit 114 uses the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync to transmit signals supplied from the outside, respectively, to the first and second polarities. The first and second dividers 138 and 140 generating the inverted signals POL1 and POL2, and the first and second dividers 138 according to the third comparison signal output from the data change detector 112. And a multiplexer 142 for selecting any one of the first and second polarity inversion signals POL1 and POL2 generated from 140.

The first divider 138 generates a first polarity inversion signal POL1 obtained by dividing the vertical synchronization signal Vsync from the outside by two. The first polarity inversion signal POL1 generated by the first divider 138 has a signal of a specific logic (eg, high or low) for one frame. The first polarity inversion signal POL1 generated by the first divider 138 is supplied to the multiplexer 142.

The second divider 140 generates a second polarity inversion signal POL2 obtained by dividing the horizontal synchronization signal Hsync from the outside by two. The second polarity inversion signal POL2 generated by the second divider 140 has a signal of a specific logic (eg, high or low) for one horizontal period. The second polarity inversion signal POL2 generated by the second divider 140 is supplied to the multiplexer 142 similarly to the first polarity inversion signal POL1. The periods of the first and second polarity inversion signals POL1 and POL2 are different from each other. The periods of the first and second polarity inversion signals POL1 and POL2 may vary depending on how many signals are supplied from the outside in the first and second dividers 138 and 140, respectively.

The multiplexer 142 receives the first and second polarity inversion signals POL1 supplied from the first and second dividers 138 and 140 according to a third comparison signal supplied from the data change detector 112. , POL2). The multiplexer 142 selects the first polarity inversion signal POL1 supplied from the first divider 138 when a third comparison signal having a high level is supplied from the data change detector 112. To the data driver 106. On the contrary, when the third comparison signal of the low is supplied from the data change detector 112, the multiplexer 142 receives the second polarity inversion signal POL2 supplied from the second divider 140. ) Is output to the data driver 106.

As described above, when data having a large gray level difference between adjacent lines and pixels on one frame is greater than or equal to a reference value, the data change detection unit 112 detects a high third comparison signal. The data change detector 112 outputs a low third comparison signal when data having a large gray level difference between adjacent lines and pixels on one frame is equal to or less than a reference value.

The multiplexer 142 selects any one of the first and second polarity inversion signals POL1 and POL2 according to the logic of the third comparison signal output from the data change detector 112.

When the first polarity inversion signal POL1 is supplied to the data driver 106, the data driver 106 supplies pixel data voltages having the same polarity to the plurality of data lines DL1 to DLm for one frame. When the second polarity inversion signal POL2 is supplied to the data driver 106, the data driver 106 transfers pixel data voltages having the same polarity to the plurality of data lines DL1 to DLm for one horizontal period. Will be supplied.

As such, when data having a large gradation difference among one frame data is greater than or equal to a reference value, the first polarity inversion signal POL1 is supplied to the data driver 106 so that the data driver 106 performs one frame. By supplying pixel data voltages having the same polarity to the plurality of data lines DL1 to DLm, power consumption of the data driver 106 can be reduced.

When the first polarity inversion signal POL1 is supplied to the data driver 106 and the second polarity inversion signal POL2 is supplied to the data driver 106, the data driver 106 is different from each other. Driven in a manner.

As a result, the data driver differs in the period of the polarity inversion signal supplied to the data driver 106 when data having a large gray level difference between adjacent lines and pixels is greater than or equal to a reference value during one frame, respectively. The power consumption of 106 can be reduced. As the power consumption of the data driver 106 is reduced, the heat generation temperature of the data driver 106, which is proportional to the power consumption, may also be reduced.

As described above, the liquid crystal display according to the present invention differs in the period of the polarity inversion signal supplied to the data driver when there is more pixel data having a larger gray level difference between adjacent lines and pixels than the reference value. By doing so, power consumption of the data driver can be reduced.

In addition, as the power consumption of the data driver is reduced, the heat generation temperature of the data driver may be reduced.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the following claims. .

Claims (10)

A liquid crystal panel in which a plurality of gate lines and a plurality of data lines are arranged; A data driver for supplying pixel data voltages inputted to the pixels on the liquid crystal panel by one line; An input unit to output the pixel data; And And a gradation change adaptive polarity inversion signal generator for outputting a polarity inversion signal having a different period according to the degree of gradation change between pixels of the pixel data to the data driver. The gray scale adaptive polarity inversion signal generator, A data change detector which receives the pixel data from the input unit and compares the gray level change between pixels of the pixel data with a reference value to generate a control signal according to the reference value; And And a polarity inversion signal output unit configured to output a polarity inversion signal having a different period according to the control signal. The polarity inversion signal output unit, A first divider for generating a first polarity inversion signal by dividing the vertical synchronization signal from the outside at a predetermined period; And And a second divider for generating a second polarity inversion signal by dividing the horizontal synchronization signal from the outside at a predetermined period. And supplying one of the first and second polarity inversion signals generated in the first and second dividers to the data driver according to the logic of the control signal. delete The method of claim 1, The polarity inversion signal output unit, Further includes a multiplexer, And the multiplexer selects one of the first and second polarity inversion signals and supplies the selected data signal to the data driver. The method of claim 1, And the periods of the first and second polarity inversion signals are different from each other. The method of claim 1, The data change detection unit, A line delay unit for delaying pixel data from the input unit by one line; A subtractor for calculating a difference between gray level values of pixel data for one line delayed by the line delay unit and pixel data for one line from the input unit; A first comparator for comparing a difference value calculated by the subtractor with a reference gray value and outputting a first comparison result signal; A first accumulation counter accumulated by a data clock signal according to the first comparison result signal; A first latch unit configured to sample the value accumulated by the first accumulation counter and to maintain the same for one horizontal period; A second comparison unit configured to output a second comparison result signal by comparing the accumulated value sampled by the first latch unit with a reference pixel number; A second accumulation counter accumulated by a horizontal synchronous signal according to the second comparison result signal; A second latch unit configured to sample a value accumulated by the second accumulation counter and to maintain the same for one vertical period; And And a third comparing unit which compares the accumulated value sampled by the second latching unit with the number of reference lines and generates a control signal to be supplied to the polarity inversion signal output unit according to the comparison result. Display. 6. The method of claim 5, And the first cumulative counter is initialized by a horizontal synchronization signal. 6. The method of claim 5, And the second cumulative counter is initialized by a vertical synchronization signal. A driving method of a liquid crystal display device comprising a liquid crystal panel in which a plurality of gate lines and a plurality of data lines are arranged, Inputting pixel data from the outside; Supplying pixel data voltages to be input to pixels on the liquid crystal panel by one line using the pixel data; Comparing the degree of gray level change between pixels with a reference value using the pixel data and outputting a control signal according thereto; And Selectively outputting a polarity inversion signal having a different period according to the control signal; Selectively outputting the polarity inversion signal, Generating a first polarity inversion signal obtained by dividing the vertical synchronization signal from the outside at regular intervals; Generating a second polarity inversion signal by dividing the horizontal synchronization signal from the outside at a predetermined period; And And selectively outputting any one of the first and second polarity inversion signals according to the control signal. delete 9. The method of claim 8, The step of outputting the control signal, Delaying the pixel data from the outside by one line: Calculating a gray level difference between the delayed pixel data for one line and pixel data for one line from the outside; Outputting a first comparison result signal by comparing the calculated difference value with a reference gray value; Accumulating by a data clock signal according to the first comparison result signal; Allowing the accumulated value to be sampled and maintained for one horizontal section; Outputting a second comparison result signal by comparing the sampled cumulative value with a reference pixel number; Accumulating by a horizontal synchronous signal according to the second comparison result signal; Allowing the accumulated value to be sampled and maintained for one vertical period; And And comparing the sampled cumulative value with the number of reference lines and generating a control signal according to the comparison result.

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