KR101319328B1 - Liquid crystal display and driving method thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display device which maintains good display quality without a tearing effect.

The liquid crystal display device comprises a liquid crystal display panel; A driving circuit for driving the liquid crystal display panel; A graphics memory in which digital video data is stored; A timing controller for supplying digital video data from the graphic memory to the driving circuit and controlling the driving circuit; And a system for supplying the digital video data to the graphics memory at a data transmission rate of 4.5Mhz to 5.53Mhz and a synchronization signal to the timing controller. The timing controller controls the driving circuit so that a time point at which data is displayed on the liquid crystal display panel is earlier than a start point of data transmission of the system.

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY AND DRIVING METHOD THEREOF}

1 is a view showing a conventional liquid crystal display device.

2 is a graph illustrating a phenomenon in which a tearing effect appears.

3 is a diagram illustrating a tearing effect appearing in a liquid crystal display panel.

4 is a graph illustrating a phenomenon in which a tearing effect appears in a liquid crystal display panel according to a data transmission speed of a system.

5 is a view showing a liquid crystal display device according to a first embodiment of the present invention.

6 is a waveform diagram showing synchronization signals.

7 is a graph showing GRAM WRITE time of a system for transmitting all data for one frame when the resolution of the liquid crystal display panel is QVGA.

8 is a graph showing an example of variable time difference between a GRAM WRITE start point and an LCD DISPLAY start point of a system.

FIG. 9 is a graph showing the minimum GRAM WRITE speed of a system without a tiering effect under the same conditions as in FIG. 8. FIG.

FIG. 10 is a graph showing a GRAM WRITE speed of a system in which a tearing effect occurs under the same conditions as in FIG. 8. FIG.

FIG. 11 is a diagram illustrating a screen position of a tiering effector as shown in FIG. 10.

12 is a graph showing a correlation between an LCD display start time and a speed and a GRAM WRITE start time and a speed of a system according to a first embodiment of the present invention.

13 is a view showing a liquid crystal display device according to a second embodiment of the present invention.

FIG. 14 is a graph showing a correlation between an LCD display start time and a speed and a GRAM WRITE start time and a speed according to a second embodiment of the present invention. FIG.

Description of the Related Art

51, 121: system 52, 122: GRAM

53, 123: Timing Controller 54, 124: Data Drive IC

55, 125: gate drive ICs 56, 126: liquid crystal display panel

127: system baud rate control unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof which maintain good display quality without a tearing effect.

The liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to a video signal. In an active matrix type liquid crystal display, switching elements are formed in each liquid crystal cell, which is advantageous for displaying a moving image. A thin film transistor (hereinafter referred to as "TFT") is mainly used as a switching element.

The small to medium sized liquid crystal module 14 of 5 inches or less includes a liquid crystal display panel 12, a driving circuit for driving the liquid crystal display panel 12, and digital video data to be displayed on the liquid crystal display panel 12 as shown in FIG. And a graphic RAM (hereinafter referred to as "GRAM") received from the system 11. The drive circuit includes a data drive integrated circuit (hereinafter referred to as an " IC "), a gate drive IC and a timing controller for controlling the ICs. Timing controllers typically have built-in GRAM. The timing controller generates a control signal for controlling the operation timing of the data drive IC and the gate drive IC using the vertical / horizontal synchronization signals Vsync and Hsync input from the system 10.

In such a small and medium-sized liquid crystal display device, according to the correlation between the GRAM write speed of the system 11 with respect to the GRAM and the speed of reading data from the GRAM and being displayed on the liquid crystal display panel 12, FIG. As described above, two display images overlap each other on one screen of the liquid crystal display panel 12, so that a so-called "tearing effect" noise may be generated. For example, the speed at which data is transferred from the system 11 to the GRAM (hereinafter referred to as GRAM WRITE speed) is the speed at which data is read from the GRAM and displayed on the liquid crystal display panel 12 (hereinafter referred to as "LCD"). In a condition slower than the "display speed", the tearing effect appears when the GRAM WRITE start time is faster than the start time of the LCD display. In FIG. 4, a thick dotted line indicates a GRAM that causes a tearing effect at the actual LCD display speed of the currently applied liquid crystal module. It is WRITE speed, and the thin dotted line is the LCD display speed assuming that the LCD display start time exists when the delay time of 1ms is delayed from the beginning of GRAM WRITE and the LCD display speed is the slowest within one frame period. Indicates the time at which appears.

In order to prevent this tearing effect and maintain the display quality satisfactorily, it is necessary to find an optimal GRAM WRITE speed at which no tearing effect appears compared to the LCD display speed.

Accordingly, it is an object of the present invention to provide a liquid crystal display device and a driving method thereof which maintain good display quality without a tearing effect.

In order to achieve the above object, the liquid crystal display device according to the first embodiment of the present invention comprises a liquid crystal display panel; A driving circuit for driving the liquid crystal display panel; A graphics memory in which digital video data is stored; A timing controller for supplying digital video data from the graphic memory to the driving circuit and controlling the driving circuit; And a system for supplying the digital video data to the graphics memory at a data transmission rate of 4.5Mhz to 5.53Mhz and a synchronization signal to the timing controller.

The timing controller controls the driving circuit so that a time point at which data is displayed on the liquid crystal display panel is earlier than a start point of data transmission of the system.

A liquid crystal display device according to a second embodiment of the present invention includes a liquid crystal display panel; A driving circuit for driving the liquid crystal display panel; A graphics memory in which digital video data is stored; A timing controller for supplying digital video data from the graphic memory to the driving circuit and controlling the driving circuit; And a system for supplying the digital video data to the graphics memory at a data transfer rate between 5.53Mhz and 30Mhz and for supplying a synchronization signal to the timing controller.

The timing controller controls the driving circuit so that a time point at which data starts to be displayed on the liquid crystal display panel is earlier than a start point of data transmission of the system, and immediately after all data for one frame are displayed on the liquid crystal display panel. The data transmission speed of the system is determined by using one of a frame end signal generated from a driving circuit and a synchronization signal from the system. The time difference between them is variable.

A method of driving a liquid crystal display device according to a first embodiment of the present invention includes the steps of: starting to display data on the liquid crystal display panel under the control of the timing controller; And supplying the digital video data to the graphic memory at a data transmission rate of 4.5 MHz to 5.53 MHz in the system after data starts to be displayed on the liquid crystal display panel.

A method of driving a liquid crystal display according to a second embodiment of the present invention includes the steps of: starting to display data on the liquid crystal display panel under the control of the timing controller; And supplying the digital video data to the graphics memory at a data transmission rate of 5.53 MHz to 30 MHz in the system after data starts to be displayed on the liquid crystal display panel. The timing controller determines the data transmission rate of the system by using any one of a frame end signal generated from the driving circuit and a synchronization signal from the system immediately after all data for one frame is displayed on the liquid crystal display panel. The time difference between the time point at which data starts to be displayed on the liquid crystal display panel and the time point at which data transmission starts in the system is varied.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 14.

5 shows a liquid crystal display device according to a first embodiment of the present invention.

Referring to FIG. 5, the liquid crystal display according to the first embodiment of the present invention includes a system 51 and a liquid crystal module 50 for displaying digital video data from the system 51.

The system 51 includes a high frequency processor, a communication modem, a DMB module, etc. to control CDMA or PCS bidirectional communication, and to receive a DMB signal and to receive video data from a mobile communication channel or a DMB received signal. Is converted to digital and supplied to the GRAM 52 via the data bus. The system 51 supplies digital video data to the GRAM 52 at a relatively slow GRAM WRITE speed of 4.5 Mhz to 5.53 Mhz.

The liquid crystal module 50 includes a GRAM 52, a timing controller 53, a data drive IC 54, a gate drive IC 55, and a liquid crystal display panel 56.

The GRMA 52 stores digital video data from the system 51 and supplies the stored digital video data RGB to the timing controller 53 under the control of the timing controller 53.

The timing controller 53 stores the N stored in the GRAM 52 before the digital video data RGB is supplied from the system 51 to the GRAM 52 so that a tearing effect does not appear when the GRAM WRITE speed is slow. A positive integer) is started to be supplied to the data drive IC 54 of the digital video data RGB of the th frame to display the data on the liquid crystal display panel 56. While the image of the Nth frame is displayed on the liquid crystal display panel 56 under the control of the timing controller 53, the system 51 starts to supply the N + 1th data to the GRAM 52. Detailed description thereof will be provided later. In addition, the timing controller 53 controls the operation timing of the data drive IC 54 and the gate drive IC 55 using the timing signals Vsync, Hsync, and DE supplied from the system 51. Generate (DDC, GDC).

The data drive IC 54 latches the digital video data RGB under the control of the timing controller 53 and includes the shift register, latch, digital-to-analog converter, and output buffer to positively / signal the digital video data RGB. It converts into a negative analog gamma compensation voltage to generate a positive / negative data voltage.

The gate drive IC 55 sequentially outputs scan pulses synchronized with the data voltage, including a shift register, a level shifter for converting the output signal of the shift register into a swing width suitable for driving the liquid crystal cell, and an output buffer.

In the liquid crystal display panel 56, liquid crystal molecules are injected between two glass substrates. The m data lines D1 to Dm and the n gate lines G1 to Gn formed on the lower glass substrate of the liquid crystal display panel 56 cross each other. Thin film transistors (“TFTs”) are connected to intersections of the data lines D1 to Dm and the gate lines G1 to Gn. The TFT is a switching element that supplies a data voltage from the data lines D1 to Dm to the pixel electrode by conducting a current path between the data lines D1 to Dm and the pixel electrodes in response to the scan pulse. The source electrodes of the TFT are connected to the data lines D1 to Dm, and the drain electrode is connected to the pixel electrode of the liquid crystal cell. The gate electrode of the TFT is connected to the gate lines G1 to Gn. Storage capacitors are formed in each of the liquid crystal cells of the liquid crystal display panel 56. The storage capacitor is formed by the gate lines G1 to Gn and the pixel electrode overlapping each other with a dielectric interposed therebetween. This storage capacitor keeps the voltage of the liquid crystal cell constant. A black matrix, a color filter, and a common electrode (not shown) are formed on the upper glass substrate of the liquid crystal display panel 56. The common electrode faces the pixel electrode with the liquid crystal layer interposed therebetween, and the common electrode is supplied. On the other hand, the common electrode is formed on the upper glass substrate in the vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode In the horizontal electric field driving method, the pixel electrode is formed on the lower glass substrate together with the pixel electrode. On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 56, a polarizing plate having an optical axis orthogonal to each other is attached, and an alignment film for setting the pretilt angle of the liquid crystal is formed on an inner side of the liquid crystal display panel 56 in contact with the liquid crystal.

The liquid crystal display according to the first embodiment of the present invention prevents the tearing effect by making the LCD display start faster than the start of the GRAM WRITE when the GRAM WRITE speed of the system is about 4.5Mhz ~ 5.53Mhz. This first embodiment of the present invention is derived based on the following experimental results.

The experiment was conducted under the following assumptions.

(1) The data write speed of the GRAM 52 is faster than the data transfer speed of the system. Generally, the speed of the data drive IC 54 is 20Mhz-30Mhz.

(2) The start point of data transfer of the system 51, the start point of WRITE of the GRAM 52, and the start point of LCD DISPLAY are not all the same.

(3) The data write start time of the system 51 is synchronized with the synchronization signal FLM (Vsyn_Out Signal) immediately after one frame period in the data drive IC 54 of the liquid crystal display panel.

(4) Assume that one frame data writing time of the system 51 + one frame image display time of the liquid crystal panel ≤ 16. 7 ms. 16.7 ms is one frame period in the NTSC standard. For reference, even if the image is displayed in terrestrial DMB CIF 30Hz or satellite DMB QVGA 15 frames, one frame of image should actually be displayed within 16.7 ms. This is because image display for one frame is performed and a blank period exists. The blank period is a non-display period including a back porch (BP), a vertical sync width (VWW), and a front porch (FP) in FIG. 6.

(5) Back Porch + Front Porch in the back porch (BP) + front porch (Front) of the vertical synchronization signal (Vsync) ≤ 16 line display time (or 16 horizontal periods (16 Hsync)) ) Time can be adjusted within 4ms.

(6) The RC oscillator (RC OSC) error of the timing controller 53 is assumed to be 10%.

A phenomenon in which a tearing effect appears will be described on the assumption that the system 51 uses a "Qualcomm" MSM chip and that the data bus speed between the MSM chip and the GRAM 52 is about 10 Mhz (0.1 µs). If the resolution of the liquid crystal display panel 56 is QVGA (240 × 320), the GRAM write time of the system 51 that writes one frame of data to the GRAM 52 is 7.68 ms (0.1 μs ×) as shown in FIG. 240 × 320). In contrast, the LCD display time for reading data from the GRAM 52 and displaying data for one frame on the liquid crystal display panel is approximately 11 ms.

When the maximum variable time of the vertical back porch period BP is 4 ms, the maximum horizontal line number of the liquid crystal display panel 56 that can be displayed in the vertical back porch period is x x 240 x 0.1 μs = 4 ms, as shown in FIG. x = 166.7 lines. Generally, in the liquid crystal display, the variable back time of the vertical back porch period BP is 16 lines or less. If the variable time of the back porch period BP is allowed in this manner, a system having a relatively low data writing speed of the GRAM 52 can be used. For example, if the GRAM WRITE start time is earlier than the LCD DISPLAY start time, the minimum speed of the GRAM WRITE of the system 51 without a tiering effect as shown below is 5.53Mhz.

The denominator of 13.9 ms is the minimum time where the GRAM WRITE speed of the system does not actually overlap with the image for one frame displayed on the liquid crystal display panel 56 as shown in FIG.

If the GRAM WRITE speed of the system 51 is lower than 5.53Mhz, before the GRAM WRITE and the LCD display time of the liquid crystal display panel 56 for one frame of data as shown in Figs. Overlapping, the tearing effect is visible.

As a result, when the GRAM WRITE start time of the system 51 is earlier than the LCD DISPLAY start time, the GRAM WRITE speed of the system 51, which may have a tearing effect, is 4.5Mhz to 5.53Mhz as follows.

이고, 이는 실험을 통해 210 번째 수평라인에서 티어링 이펙트가 나타났다는 사실과도 부합되 었다. When the GRAM WRITE speed of the system 51 is 4.5 MHz and the GRAM WRITE start time of the system 51 is 4ms faster than the start time of the LCD display, the position where the tearing effect appears in FIG.

This coincided with the fact that the experiment showed a tearing effect on the 210th horizontal line.

Accordingly, the liquid crystal display according to the first embodiment of the present invention starts LCD display as shown in FIG. 12 so that a tearing effect does not occur when the GRAM WRITE speed of the system 51 is lowered to 4.5Mhz to 5.53Mhz as shown in FIG. 12. The control point is controlled to be earlier than the GRAM WRITE start point of the system 51. In the example shown in Fig. 12, the LCD DISPLAY start time is 4 ms than the GRAM WRITE start time of the system 51. In this case, the curve of the LCD DISPLAY displaying one frame of image and the GRAM WRITE speed curve of the system do not cross each other. Therefore, no tiering effect appears. In the liquid crystal display according to the first exemplary embodiment of the present invention, the LCD display start time is illustrated as 4 ms than the GRAM WRITE start time of the system 51 as shown in FIG. 12, but the time between them is as shown in FIG. 12. The tearing effect does not appear when the display speed is approximately 3ms to 5ms.

13 shows a liquid crystal display according to a second embodiment of the present invention.

Referring to FIG. 13, the liquid crystal display according to the second exemplary embodiment of the present invention includes a system 121 and a liquid crystal module 120 for displaying digital video data from the system 121.

The system 121 includes a high frequency processor, a communication modem, a DMB module, and the like to control CDMA or PCS bidirectional communication, and to receive a DMB signal and to receive video data from a mobile communication channel or a DMB received signal. Is converted to digital and supplied to the GRAM 52 via the data bus. The system 51 supplies digital video data to the GRAM 122 at a fast GRAM WRITE speed of 5.53 MHz or higher.

The liquid crystal module 120 includes a GRAM 122, a timing controller 123, a data drive IC 124, a gate drive IC 125, a liquid crystal display panel 126, and a system transmission speed controller 127. Since the data drive IC 124, the gate drive IC 125, and the liquid crystal display panel 126 are substantially the same as the corresponding configuration of the first embodiment, detailed description thereof will be omitted.

The data drive IC 124 latches the digital video data RGB under control of the timing controller 123 and includes a shift register, a latch, a digital-to-analog converter, and an output buffer to positively / signal the digital video data RGB. It converts into a negative analog gamma compensation voltage to generate a positive / negative data voltage.

The GRMA 122 stores the digital video data input from the system 121 at a high transmission speed of 5.53 MHz or higher and supplies the digital video data RGB stored under the control of the timing controller 123 to the timing controller 123.

The timing controller 123 reads the data stored in the GRAM 122 prior to the start point of the GRAM WRITE of the system 121 in which the system 121 starts to transmit one frame of data as in the first embodiment described above. The GRAM 122 and the driving circuits 123 and 124 are controlled to start displaying one frame of image on the liquid crystal display panel 126.

In addition, the timing controller 123 quickly controls the start point of the LCD display prior to the start point of the GRAM WRITE of the system 121, but is based on the timing signals Vsync, Hsync, and DE received from the system 121. GRAM WRITE speed, that is, the data transfer speed of the system. When the GRAM WRITE speed of the system 121 is 5.53Mhz or more, the timing controller 123 controls the system transmission speed control unit 127 so that the faster the GRAM WRITE speed of the system 121 is, the LCD display starts and the GRAM WRITE of the system. Increase the time difference between start points.

Alternatively, the timing controller 123 counts the period of the frame end signal FLM input from the data drive IC 124 immediately after all of the data for one frame is displayed on the liquid crystal display panel 126 so that the system ( GRAM WRITE speed of 121), that is, the data transfer speed of the system can be determined. To this end, the data drive IC 124 supplies the frame end signal FLM to the timing controller immediately after supplying all of the data voltages for one frame to the data lines D1 to Dm. When the GRAM WRITE speed of the system 121 is determined to be 5.53Mhz or more based on the frame end signal FLM from the data drive IC 124, the timing controller 123 controls the system transmission control unit 127 to control the system. The faster the GRAM WRITE speed of (121), the larger the time difference between the LCD display start time and the system's GRAM WRITE start time.

The system transmission speed control unit 127 supplies data indicating the start point of transmission of one frame of data to the central processing unit or the data transmission control circuit of the system 121 under the control of the timing controller 123, and thereby the system 121 Controls when the GRAM WRITE starts. The period between the LCD DISPLAY start time and the GRAM WRITE start time of the system 121 is varied within the allowable time range within the blank period including the back porch period BP of the vertical synchronization signal.

In the liquid crystal display according to the second exemplary embodiment of the present invention, when the start point of the LCD display is faster than the start point of the system's GRAM WRITE, when the GRAM WRITE speed of the system 121 is faster than 5.53Mhz, it is tiered as shown in the arrow of FIG. 12. If the GRAM WRITE speed of the system 121 is 5.53Mhz or more because the effect may appear, the start point of the LCD display is controlled faster than the start point of the GRAM WRITE of the system 121, but as shown in FIG. The delay time between the start of GRAM WRITE in 121) is longer than 4ms. According to the second exemplary embodiment of the present invention, when the GRAM WRITE of the system 121 is 10 Mhz as shown in FIG. 12, the LCD 121 displays a time point after a delay time of approximately 4.0 ms to 4.5 ms from the start of the LCD display. When the GRAM WRITE of the system 121 is 20 Mhz, the GRAM WRITE is controlled at the start time and the time after the delay time between approximately 7.5 ms and 8.0 ms from the LCD display start time is controlled as the GRAM WRITE start time. In the liquid crystal display according to the second exemplary embodiment of the present invention, when the GRAM WRITE of the system 121 is 30 Mhz as shown in FIG. 12, the system 121 displays a time point after a delay time between about 9.0 ms and 9.5 ms from the start of LCD display. Control at the start of GRAM WRITE.

In the second embodiment of the present invention, the system transmission rate controller 127 may be embedded in the timing controller 127. In this case, the start of data transfer of the system 121 is directly controlled by the timing controller 127.

As described above, the liquid crystal display and the driving method thereof according to the embodiment of the present invention to prevent the tearing effect by making the start of the LCD display faster than the start of the GRAM WRITE of the system when the GRAM WRITE speed of the system is relatively low, When the system's GRAM WRITE speed is high, the timing difference between the start of the LCD display and the system's GRAM WRITE can be increased to prevent the tearing effect.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (12)

A liquid crystal display panel; A driving circuit for driving the liquid crystal display panel; A graphics memory in which digital video data is stored; A timing controller for supplying digital video data from the graphic memory to the driving circuit and controlling the driving circuit; And A system for supplying the digital video data to the graphics memory at a data transmission rate of 4.5Mhz to 5.53Mhz and a synchronization signal to the timing controller; And the timing controller controls the driving circuit so that a time at which data starts to be displayed on the liquid crystal display panel is earlier than a start point of data transmission of the system. The method of claim 1, And a time point at which data starts to be displayed on the liquid crystal display panel is 3ms to 5ms ahead of a data transmission start point of the system. The method of claim 2, And a time point at which data starts to be displayed on the liquid crystal display panel is about 4 ms ahead of a start point of data transmission of the system. A liquid crystal display panel; A driving circuit for driving the liquid crystal display panel; A graphics memory in which digital video data is stored; A timing controller for supplying digital video data from the graphic memory to the driving circuit and controlling the driving circuit; And A system for supplying said digital video data to said graphics memory at a data transfer rate between 5.53 MHz and 30 MHz and a synchronization signal to said timing controller; The timing controller controls the driving circuit so that a time point at which data starts to be displayed on the liquid crystal display panel is earlier than a start point of data transmission of the system, and immediately after all data for one frame are displayed on the liquid crystal display panel. The data transmission speed of the system is determined by using one of a frame end signal generated from a driving circuit and a synchronization signal from the system. And a time difference between the liquid crystal display devices. 5. The method of claim 4, And a time difference between a time point at which data is displayed on the liquid crystal display panel and a time point at which data transmission starts in the system varies between 4 ms and 9.5 ms. 5. The method of claim 4, And the faster the data transfer rate of the system, the greater the time difference between the time point at which data starts to be displayed on the liquid crystal display panel and the time point at which the system starts transmitting data. A liquid crystal display panel, a driving circuit for driving the liquid crystal display panel, a graphic memory storing digital video data, a timing controller for supplying digital video data from the graphic memory to the driving circuit and controlling the driving circuit; A driving method of a liquid crystal display device comprising a system for supplying digital video data to the graphic memory and a synchronization signal to the timing controller. Starting to display data on the liquid crystal display panel under the control of the timing controller; And Supplying the digital video data to the graphic memory at a data transfer rate of 4.5 MHz to 5.53 MHz in the system after data is displayed on the LCD panel. The method of claim 7, wherein And a time point at which data starts to be displayed on the liquid crystal display panel is 3ms to 5ms ahead of the data transmission start point of the system. 9. The method of claim 8, And a time point at which data starts to be displayed on the liquid crystal display panel is about 4 ms ahead of the start point of data transmission of the system. A liquid crystal display panel, a driving circuit for driving the liquid crystal display panel, a graphic memory storing digital video data, a timing controller for supplying digital video data from the graphic memory to the driving circuit and controlling the driving circuit; A driving method of a liquid crystal display device comprising a system for supplying digital video data to the graphic memory and a synchronization signal to the timing controller. Starting to display data on the liquid crystal display panel under the control of the timing controller; And Supplying the digital video data to the graphics memory at a data transfer rate between 5.53 MHz and 30 MHz in the system after data begins to be displayed on the liquid crystal display panel; The timing controller determines the data transmission rate of the system by using any one of a frame end signal generated from the driving circuit and a synchronization signal from the system immediately after all data for one frame is displayed on the liquid crystal display panel. And a time difference between a time point at which data begins to be displayed on the liquid crystal display panel and a time point at which data transmission starts in the system. 11. The method of claim 10, And a time difference between a time point at which data begins to be displayed on the liquid crystal display panel and a time point at which data transmission starts in the system is varied between 4 ms and 9.5 ms. The method of claim 11, And the faster the data transfer rate of the system, the greater the time difference between the time point at which data starts to be displayed on the liquid crystal display panel and the start time point of data transfer of the system.

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