KR101313690B1 - Method for fabricating bonding structure of semiconductor device - Google Patents

Abstract

The present invention relates to a method for forming a bonding structure of a semiconductor device, and when forming a bonding structure with a metal plate and a filler, without forming an antioxidant layer and a wire contact layer on the top of the metal plate, the barrier metal layer and the metal seed on the bottom of the filler By not forming a layer, the contact resistance can be lowered because the metal plate and the filler can be directly contacted and formed of the same material while simplifying the process, and the metal is removed when the exposed area of the barrier metal layer formed on the lower side of the metal plate is removed. By performing a removal process on the exposed area of the barrier metal layer in a state where a protective film is formed on the sidewall of the plate, there is an advantage of preventing further oxidation of the metal plate while preventing undercut phenomenon of the metal plate.

Description

Bonding Structure Formation Method of Semiconductor Device {METHOD FOR FABRICATING BONDING STRUCTURE OF SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a bonding structure of a semiconductor device, and more particularly, to forming a thick metal plate on a passivation film for forming a bond pad on an active circuit. The present invention relates to a method of forming a bonding structure of a semiconductor device to which an active circuit or circuit under pad (CUP) technology is applied.

As is well known, a semiconductor integrated circuit is enclosed in a package including a plurality of externally disposed pins or other conductive elements for connecting a chip packaged to an electronic component of the semiconductor element. In order to connect the integrated circuits to the package pins, the topmost metal wiring of the chip interconnect system comprises a plurality of bond pads for receiving conductive devices (bond wires, solder bumps or solder balls) for connecting the package pins and the integrated circuits. ). That is, the bond pad of the uppermost wiring is formed, and a bond wire or a solder bump is connected to the bond pad.

In the case of power devices, a BOAC that forms a thick metal plate on a passivation film that forms a bond pad on top of the active circuit to reduce metal routing resistance, contact resistance and die size, or CUP technology is used. Moreover, although it is common to connect a bond wire to the upper part of this metal plate, you may form a pillar in the upper part of this metal plate, and may mutually connect.

In the flip chip structure, a conductive bump is formed on a bond pad of a semiconductor device, and the conductive bump is connected to a land of a substrate to reduce the size of the semiconductor device. However, in such a flip chip structure, since the volume of the conductive bump itself is large and limited by the spacing of the bond pads, in order to solve this problem, a structure using a metal filler is vertically formed on the bond pads of the semiconductor device.

1A to 1N are cross-sectional views of a semiconductor device for explaining a method of forming a bonding structure with a metal plate and a filler according to the prior art. The process of forming the bonding structure with reference to this is as follows.

First, as shown in FIG. 1A, the uppermost metal wiring 13 is formed on the semiconductor substrate 11, and the passivation film 15 is formed on the semiconductor substrate 11 on which the metal wiring 13 is formed. The passivation film 15 is patterned to expose a portion of the surface of (13) to form a bond pad.

As shown in FIG. 1B, a barrier metal layer 17 is formed on the exposed metal wiring 13 and the passivation layer 15, and a metal seed layer 19 is sputtered on the barrier metal layer 17. To form. Here, the metal seed layer 19 is usually formed of copper (Cu).

As illustrated in FIG. 1C, a photoresist pattern 21 defining a metal plate formation region is formed on the metal seed layer 19.

As shown in FIG. 1D, the metal plate 23 is formed on the metal plate forming region on the metal seed layer 19 by electroplating, and the anti-oxidation layer 25 and the wire contact layer 27 are formed on the metal plate 23. Is laminated by electroplating method. Here, the metal plate 23 is usually formed of copper (Cu), the anti-oxidation layer 25 is formed of nickel (Ni), and the wire contact layer 27 is formed of gold (Au).

The remaining photoresist pattern 21 is removed as shown in FIG. 1E.

As shown in FIG. 1F, the barrier metal layer 17 and the metal seed layer 19 exposed on the passivation layer 15 are removed. In this case, the wet plate is generally used, and the metal plate 23 is affected, so that an undercut phenomenon occurs in which sidewall portions are etched together.

An insulating film 31 is formed on the semiconductor substrate 11 including the wire contact layer 27 to surround the metal plate 23 as shown in FIG. 1G, and the insulating film 31 is patterned to contact the wire in the filler forming region. Layer 27 is open to expose.

As shown in FIG. 1H, the barrier metal layer 33 is formed on the insulating layer 31, and the metal seed layer 35 is formed on the barrier metal layer 33. Here, the metal seed layer 35 is usually formed of copper (Cu) using a sputtering method.

As shown in FIG. 1I, a photoresist pattern 37 defining a filler formation region is formed on the metal seed layer 35.

As shown in FIG. 1J, the filler 39 is formed in the metal plate forming region on the metal seed layer 35, and the solder cap 41 is formed on the pillar 39. Here, the filler 39 is usually formed of copper (Cu), and the solder cap 41 is formed of an alloy of tin and silver (Sn-Ag).

The photosensitive film pattern 37 is removed as shown in FIG. 1K.

As illustrated in FIG. 1L, the metal seed layer 35 exposed on the insulating layer 31 is removed by a wet etching method.

As illustrated in FIG. 1M, the barrier metal layer 33 exposed on the insulating layer 31 is removed by a wet etching method.

The reflow heat treatment is applied as shown in FIG. 1N to make the solder cap 41 hemispherical.

According to the method of forming a bonding structure according to the related art as described above, it can be seen that an oxide layer and a wire contact layer are formed on the upper portion of the metal plate and a barrier metal layer and a metal seed layer are formed on the lower portion of the filler. The anti-oxidation layer prevents oxidation of the metal plate, the wire contact layer reduces contact resistance with the wire, the barrier metal layer prevents corrosion, and the metal seed layer is necessary for the growth of copper when forming the filler. Do. However, they cause long cycle times and increase process costs, and increase contact resistance at the connection contact between the metal plate and the filler.

In addition, when the barrier metal layer and the metal seed layer exposed on the upper portion of the passivation film protecting the semiconductor substrate are removed by wet etching, an undercut phenomenon occurs in which sidewall portions of the filler copper are etched together. For this reason, there was a problem that it is difficult to accurately control the line width of the filler (copper), the copper exposed to the air had a problem that causes oxidation to proceed quickly and continuously to increase the resistance.

Korean Patent Registration No. 10-0896841, published May 12, 2009.

The present invention has been proposed to solve the problems of the prior art as described above, and when forming a bonding structure with a metal plate and a filler, a barrier at the bottom of the filler without forming an antioxidant layer and a wire contact layer on the top of the metal plate. By not forming the metal layer and the metal seed layer, there is provided a method of forming a bonding structure of a semiconductor device that simplifies the process and lowers the contact resistance of the metal plate and the filler.

In addition, according to the present invention, when the exposed area of the barrier metal layer formed on the lower side of the metal plate is removed, the undercut phenomenon of the metal plate is removed by performing the removal process on the exposed area of the barrier metal layer in a state where a protective film is formed on the sidewall of the metal plate. It provides a method of forming a bonding structure of a semiconductor device while preventing the further oxidation of the metal plate.

In a method of forming a bonding structure of a semiconductor device as a first aspect of the present invention, a partial region of the metal seed layer is formed on a barrier metal layer and a metal seed layer stacked on a passivation film that opens a bond pad formed on an upper surface of a semiconductor substrate. Forming a metal plate exposing the metal plate; forming a pattern film having an open filler forming region on an upper surface of the metal plate and the metal seed layer on which the natural oxide film is formed; The method may include removing the filler, forming a filler in the filler forming region, and removing the pattern layer.

Here, removing the exposed portion of the metal seed layer by removing the pattern layer, forming a protective film on the sidewalls of the metal plate and the filler, and the barrier metal layer by removing the exposed portion of the metal seed layer The method may further include removing the exposed portion of the.

In the removing of the natural oxide layer, the natural oxide layer may be removed by plasma etching or wet etching.

In the forming of the passivation layer, a compound layer including the same metal component as the metal plate may be formed as the passivation layer.

The forming of the passivation layer may be performed by performing plasma treatment on the sidewall of the metal plate using a gas containing nitrogen and hydrogen or an ammonia-based gas to form the compound layer including nitrogen.

In the forming of the protective film, the plasma treatment may be performed at a temperature condition of 100 ° C to 350 ° C or a temperature condition of -50 ° C to 50 ° C.

According to a second aspect of the present invention, there is provided a method of forming a bonding structure of a semiconductor device, the method comprising: opening a bond pad by patterning a passivation film formed on an upper surface of a semiconductor substrate, a barrier metal layer and a metal on the open bond pad and the passivation film; Stacking a seed layer, forming a pattern film that opens an upper portion of the metal seed layer in a specific pattern, and growing a metal in an open region of the metal seed layer by the pattern film to form a metal plate Removing the pattern layer, removing the exposed portion of the metal seed layer by removing the pattern layer, forming a protective film on the sidewall of the metal plate, and removing the exposed portion of the metal seed layer. Removing the exposed portion of the barrier metal layer by

Here, in the forming of the passivation layer, a compound layer including the same metal component as the metal plate may be formed as the passivation layer.

The forming of the passivation layer may be performed by performing plasma treatment on the sidewall of the metal plate using a gas containing nitrogen and hydrogen or an ammonia-based gas to form the compound layer including nitrogen.

In the forming of the protective film, the plasma treatment may be performed at a temperature condition of 100 ° C to 350 ° C or a temperature condition of -50 ° C to 50 ° C.

According to an embodiment of the present invention, when forming a bonding structure with a metal plate and a filler, an oxide layer and a wire contact layer are not formed on the top of the metal plate, and a barrier metal layer and a metal seed layer are not formed on the bottom of the filler. In addition, the contact resistance can be lowered because the metal plate and the filler can be directly contacted and formed of the same material while simplifying the process.

In addition, according to the present invention, when the exposed area of the barrier metal layer formed on the lower side of the metal plate is removed, the undercut phenomenon of the metal plate is removed by performing the removal process on the exposed area of the barrier metal layer in a state where a protective film is formed on the sidewall of the metal plate. Prevents further oxidation of the metal plate.

1A to 1N are cross-sectional views of a semiconductor device for explaining a method of forming a bonding structure with a metal plate and a filler according to the prior art.
2A to 2M are cross-sectional views of a semiconductor device for describing a method of forming a bonding structure with a metal plate and a pillar according to a first embodiment of the present invention.
3A to 3H are cross-sectional views of a semiconductor device for describing a method of forming a bonding structure with a metal plate and a pillar according to a second embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

2A to 2M are cross-sectional views of a semiconductor device for describing a method of forming a bonding structure with a metal plate and a pillar according to a first embodiment of the present invention. The process of forming the bonding structure with reference to this is as follows.

First, as shown in FIG. 2A, the uppermost metal wiring 103 is formed on the semiconductor substrate 101, and the passivation film 105 is formed on the semiconductor substrate 101 on which the metal wiring 103 is formed. The passivation film 105 is patterned to expose a portion of the surface of the 103 to form a bond pad. For example, the metal wire 103 may be formed of aluminum, the passivation film 105 may be deposited by chemical vapor deposition (CVD), and the passivation film 105 may be patterned using a photosensitive film pattern.

As shown in FIG. 2B, the barrier metal layer 107 is formed on the exposed metal wiring 103 and the passivation layer 105, and the metal seed layer 109 is formed on the barrier metal layer 107. For example, the barrier metal layer 110 may be formed of a single layer using any one of titanium (Ti), titanium nitride (TiN), a compound of titanium and tungsten (TiW), de-tanium (Ta), or de-tantalum nitride (TaN). The metal seed layer 109 may be formed of copper (Cu), gold (Au), tin (Sn), lead (Pb), silver (Ag), or bismuth. (Bi) can be formed of one or a plurality of alloys, and the barrier metal layer 107 and the metal seed layer 109 are deposited in-situ in a thickness of 1000 kPa to 5000 kPa using a sputtering method. can do.

As shown in FIG. 2C, a pattern film 111 defining a metal plate formation region is formed on the metal seed layer 109. For example, the pattern film 111 may form a photoresist pattern having a thickness of 15 μm to 20 μm.

As shown in FIG. 2D, the metal plate 113 is formed in the metal plate formation region on the metal seed layer 109. For example, the metal plate 113 may be formed by growing copper (Cu) to a thickness of 5 μm to 20 μm using an electrolytic plating method. Due to the electrolytic plating method, copper is grown only in the metal plate formation region from which the pattern film 111 is removed. The metal plate 113 may be formed of one or a plurality of alloys of copper (Cu), gold (Au), tin (Sn), lead (Pb), silver (Ag), and bismuth (Bi).

The remaining pattern film 111 is removed as shown in FIG. 2E.

As shown in FIG. 2F, a pattern film 117 defining a pillar formation region is formed on the semiconductor substrate 101 on which the metal plate 113 is formed. In this case, the natural oxide film 115 is formed on the exposed surface of the metal plate 113. For example, the pattern film 117 may form a photoresist pattern having a thickness of 100 μm to 120 μm.

As shown in FIG. 2G, the native oxide film 115 on the metal plate 113 exposed to the filler forming region opened by the pattern film 117 is removed. For example, the native oxide film 115 may be removed by plasma etching or wet etching using argon gas.

As shown in FIG. 2H, the filler 119 and the solder cap 121 are formed in-situ on the metal plate 113 in the filler forming region from which the natural oxide film 115 is removed. For example, the filler 119 and the solder cap 121 may be grown by electroplating, and the filler 119 may be formed of copper (Cu), gold (Au), tin (Sn), lead (Pb), and silver. One or a plurality of alloys of (Ag) and bismuth (Bi) may be formed to a thickness of 50 μm to 100 μm, and the solder cap 121 may be formed of an alloy of tin and silver (Sn-Ag) or the like from 10 μm to 50 μm. It can be formed in the thickness of. Here, the filler 119 and the solder cap 121 may be formed because the natural oxide film 115 exposed in the previous process is removed, and the metal plate 113 and the filler 119 are in direct contact with each other. Since the contact resistance can be reduced, the contact resistance can be reduced.

The remaining pattern film 117 is removed as shown in FIG. 2I. In this case, the natural oxide film 115 exposed on the surface of the metal plate 113 may be removed together. However, the process of removing the exposed natural oxide film 115 may not be performed.

As illustrated in FIG. 2J, the metal seed layer 109 exposed on the passivation layer 105 is removed. For example, wet etching may be performed to remove the exposed metal seed layer 109.

A protective film 123 is formed on the sidewalls of the metal plate 113 and the filler 119 as shown in FIG. 2K. For example, a plasma treatment is performed on the sidewalls of the metal plate 113 and the filler 119 using a gas containing nitrogen and hydrogen or an ammonia-based gas to form the protective layer 123 with a compound layer containing nitrogen (CuxNy, etc.). It can be formed as. That is, the compound layer including the same metal component as the metal plate 113 is formed as the protective film 123. At this time, the plasma treatment may be performed at a temperature condition of 100 ℃ to 350 ℃. Alternatively, the plasma treatment may be performed at a low temperature of -50 ° C to 50 ° C in order to prevent the occurrence of defects.

As shown in FIG. 2L, the barrier metal layer 107 exposed on the passivation layer 105 is removed. For example, wet etching may be performed to remove the exposed barrier metal layer 107. At this time, the protective film 123 prevents the undercut phenomenon from occurring on the side of the metal plate 113, and the oxidation of the metal plate 113 and the filler 119 is prevented by the protective film 123.

As shown in FIG. 2M, the reflow heat treatment process is performed to deform the solder cap 121 into a hemispherical shape. For example, the reflow heat treatment may be performed at a temperature range of 156 ° C to 400 ° C. Subsequently, subsequent processes such as back grind and package may be performed.

3A to 3H are cross-sectional views of a semiconductor device for describing a method of forming a bonding structure with a metal plate according to a second embodiment of the present invention. The process of forming the bonding structure with reference to this is as follows.

First, as shown in FIG. 3A, the uppermost metal wiring 103 is formed on the semiconductor substrate 101, and the passivation film 105 is formed on the semiconductor substrate 101 on which the metal wiring 103 is formed. The passivation film 105 is patterned to expose a portion of the surface of the 103 to form a bond pad. For example, the metal wire 103 may be formed of aluminum, the passivation film 105 may be deposited by chemical vapor deposition (CVD), and the passivation film 105 may be patterned using a photosensitive film pattern.

As shown in FIG. 3B, a barrier metal layer 107 is formed on the exposed metal interconnect 103 and the passivation layer 105, and a metal seed layer 109 is formed on the barrier metal layer 107. For example, the barrier metal layer 110 may be formed of a single layer using any one of titanium (Ti), titanium nitride (TiN), a compound of titanium and tungsten (TiW), de-tanium (Ta), or de-tantalum nitride (TaN). The metal seed layer 109 may be formed of copper (Cu), gold (Au), tin (Sn), lead (Pb), silver (Ag), or bismuth. (Bi) may be formed of one or a plurality of alloys, and the barrier metal layer 107 and the metal seed layer 109 may be deposited in-situ in a thickness of 1000 kPa to 5000 kPa using a sputtering method. .

As shown in FIG. 3C, a pattern film 111 defining a metal plate formation region is formed on the metal seed layer 109. For example, the pattern film 111 may form a photoresist pattern having a thickness of 15 μm to 20 μm.

As shown in FIG. 3D, the metal plate 113 is formed in the metal plate formation region on the metal seed layer 109, and the antioxidant layer 201 and the wire contact layer 203 are stacked on the metal plate 113. For example, the metal plate 113 may be formed by growing copper (Cu) to a thickness of 5 μm to 20 μm using an electrolytic plating method. Due to the electrolytic plating method, copper is grown only in the metal plate formation region from which the pattern film 111 is removed. The metal plate 113 may be formed of one or a plurality of alloys of copper (Cu), gold (Au), tin (Sn), lead (Pb), silver (Ag), and bismuth (Bi). The antioxidant layer 201 may be formed of nickel (Ni) or the like, and the wire contact layer 203 may be formed of gold (Au) or the like.

The pattern film 111 is removed as shown in FIG. 3E.

As shown in FIG. 3F, the metal seed layer 109 exposed on the passivation layer 105 is removed. For example, wet etching may be performed to remove the exposed metal seed layer 109.

A protective film 205 is formed on the sidewall of the metal plate 113 as shown in FIG. 3G. For example, the protective layer 205 may be formed of a compound layer containing nitrogen (CuxNy, etc.) by performing plasma treatment on the sidewall of the metal plate 113 using a gas containing nitrogen and hydrogen or an ammonia-based gas. . That is, the compound layer containing the same metal component as the metal plate 113 is formed as the protective film 205. At this time, the plasma treatment may be performed at a temperature condition of 100 ℃ to 350 ℃. Alternatively, the plasma treatment may be performed at a low temperature of -50 ° C to 50 ° C in order to prevent the occurrence of defects.

As shown in FIG. 3H, the barrier metal layer 107 exposed on the passivation layer 105 is removed. For example, wet etching may be performed to remove the exposed barrier metal layer 107. At this time, the protective film 205 prevents the undercut phenomenon from occurring in the metal plate 113, and oxidation of the metal plate 113 is prevented by the protective film 205.

The above description is merely illustrative of the technical idea of the present invention, and those skilled in the art to which the present invention pertains may make various modifications and variations without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

101 semiconductor substrate 103 metal wiring
105: passivation film 107: barrier metal layer
109: metal seed layer 111, 117: pattern film
113: metal plate 115: natural oxide film
119: filler 121: solder cap
123 and 205: protective film 201: antioxidant film
203: wire contact layer

Claims (10)

Forming a metal plate exposing a portion of the metal seed layer on the barrier metal layer and the metal seed layer stacked on the passivation film to open the bond pad formed on the upper surface of the semiconductor substrate;
Forming a pattern film having an open filler forming region on an upper surface of the metal plate and the metal seed layer on which a natural oxide film is formed;
Removing the natural oxide film of the filler forming region;
Forming a filler in the filler forming region;
Removing the pattern layer
Method for forming a bonding structure of a semiconductor device. The method of claim 1,
Removing the exposed portion of the metal seed layer by removing the pattern film;
Forming a protective film on sidewalls of the metal plate and the filler;
Removing the exposed portion of the barrier metal layer by removing the exposed portion of the metal seed layer.
Method for forming a bonding structure of a semiconductor device. 3. The method according to claim 1 or 2,
The removing of the natural oxide layer may include removing the natural oxide layer by plasma etching or wet etching.
Method for forming a bonding structure of a semiconductor device. 3. The method of claim 2,
The forming of the passivation layer may include forming a compound layer including the same metal component as the metal plate as the passivation layer.
Method for forming a bonding structure of a semiconductor device. 5. The method of claim 4,
The forming of the passivation layer may include performing a plasma treatment on the sidewall of the metal plate using a gas containing nitrogen and hydrogen or an ammonia-based gas to form the compound layer containing nitrogen.
Method for forming a bonding structure of a semiconductor device. The method of claim 5, wherein
The forming of the protective film may be performed by performing the plasma treatment at a temperature condition of 100 ° C. to 350 ° C. or a temperature condition of −50 ° C. to 50 ° C.
Method for forming a bonding structure of a semiconductor device. Patterning the passivation film formed on the upper surface of the semiconductor substrate to open the bond pads;
Stacking a barrier metal layer and a metal seed layer on the open bond pad and the passivation film;
Forming a pattern film that opens an upper portion of the metal seed layer in a specific pattern;
Forming a metal plate by growing a metal in an open region of the metal seed layer by the pattern layer;
Removing the pattern layer;
Removing the exposed portion of the metal seed layer by removing the pattern film;
Forming a protective film on sidewalls of the metal plate;
Removing the exposed portion of the barrier metal layer by removing the exposed portion of the metal seed layer.
Method for forming a bonding structure of a semiconductor device. The method of claim 7, wherein
The forming of the passivation layer may include forming a compound layer including the same metal component as the metal plate as the passivation layer.
Method for forming a bonding structure of a semiconductor device. The method of claim 8,
The forming of the passivation layer may include performing a plasma treatment on the sidewall of the metal plate using a gas containing nitrogen and hydrogen or an ammonia-based gas to form the compound layer containing nitrogen.
Method for forming a bonding structure of a semiconductor device. The method of claim 9,
The forming of the protective film may be performed by performing the plasma treatment at a temperature condition of 100 ° C. to 350 ° C. or a temperature condition of −50 ° C. to 50 ° C.
Method for forming a bonding structure of a semiconductor device.

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