KR101275957B1 - Thin Film Transistor Array Substrate And Method For Fabricating Thereof - Google Patents

Abstract

The present invention relates to a thin film transistor array substrate capable of preventing malfunction and leakage current of a thin film transistor and a method of manufacturing the same.

To this end, the thin film transistor array substrate according to the present invention includes a gate line and a data line crossing each other with a gate insulating film therebetween; A thin film transistor formed at an intersection of the gate line and the data line; A pixel electrode connected to the thin film transistor; A protective film formed to cover the pixel electrode; And a common electrode formed on the passivation layer to form an electric field with the pixel electrode, wherein the common electrode includes a plurality of slits in a region overlapping the pixel electrode and is not overlapped with the thin film transistor.

Description

Thin Film Transistor Array Substrate and Method for Manufacturing the Same {Thin Film Transistor Array Substrate And Method For Fabricating Thereof}

1 is a plan view showing a conventional thin film transistor array substrate.

FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1;

3 is a plan view illustrating a thin film transistor array substrate according to an embodiment of the present invention.

4 is a cross-sectional view taken along the line II-II 'of FIG. 3;

5A through 5F are cross-sectional views illustrating a process of manufacturing the thin film transistor array substrate illustrated in FIG. 4.

6 is a plan view illustrating a thin film transistor array substrate according to still another embodiment of the present invention.

7A and 7B are cross-sectional views illustrating a manufacturing process of the thin film transistor array substrate illustrated in FIG. 6.

Description of the Related Art

2, 102: gate line 4, 104: data line

6, 106 thin film transistor 8, 108 gate electrode

10, 110: source electrode 12, 112: drain electrode

14, 114: active layer 16, 116: pixel electrode

20, 120: storage capacitor 126: gate pad portion

134: data pad portion 44,144: gate insulating film

48, 148: ohmic contact layer 14,114: active layer

49,149: Semiconductor Pattern

The present invention relates to a liquid crystal display device, and more particularly, to a thin film transistor array substrate capable of preventing malfunction and leakage current of a thin film transistor, and a method of manufacturing the same.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. Such liquid crystal displays are roughly classified into a vertical electric field application type and a horizontal electric field application type according to the direction of the electric field for driving the liquid crystal.

In the vertical field applying liquid crystal display, a liquid crystal of TN (Twisted Nemastic) mode is driven by a vertical electric field formed between a pixel electrode and a common electrode disposed to face the upper and lower substrates. The vertical field application type liquid crystal display device has an advantage of having a large aperture ratio while having a narrow viewing angle of about 90 degrees.

In a horizontal field application liquid crystal display, a liquid crystal in an in-plane switch (hereinafter referred to as IPS) mode is driven by a horizontal electric field between a pixel electrode and a common electrode arranged side by side on a lower substrate. Such a horizontal field application liquid crystal display has an advantage that a viewing angle is about 160 degrees.

On the other hand, in the vertical field applying liquid crystal display device, the common electrode is formed entirely on the color filter array substrate, whereas in the horizontal field applying liquid crystal display device, since the common electrode has to form a pixel electrode and a horizontal electric field, they are formed in a line shape. As a result, in order to minimize the line resistance as the line resistance in the common electrode increases, a thin film transistor array substrate having a structure in which the common electrode is also located in a region excluding the pixel region as shown in FIGS. 1 and 2 has been proposed. . FIG. 2 is a cross-sectional view taken along line II ′ of the thin film transistor array substrate of FIG. 1. FIG.

The thin film transistor array substrate shown in FIGS. 1 and 2 includes a gate line 2 and a data line 4 intersecting each other with a gate insulating film 44 interposed on the lower substrate 42, and a thin film formed at each intersection thereof. The transistor 6, the pixel electrode 16 formed in the cell region provided in the intersection structure, and the storage capacitor 20 formed in the overlapping part of the pixel electrode 16 and the front gate line 2 are formed. A common electrode 18 is formed to form a potential difference with the pixel electrode 16.

The gate line 2 and the data line 4 are formed to cross each other to define a pixel region in which an electric field is formed between the pixel electrode 16 and the common electrode 18.

The thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, a drain electrode 12 connected to the pixel electrode 16, and And an active layer 14 overlapping the gate electrode 8 and forming a channel between the source electrode 10 and the drain electrode 12. An ohmic contact layer 48 for ohmic contact with the source electrode 10 and the drain electrode 12 is further formed on the active layer 14. Hereinafter, the active layer 14 and the ohmic contact layer 48 are referred to as a semiconductor pattern 49.

The thin film transistor 6 keeps the pixel voltage signal supplied to the data line 4 charged in the pixel electrode 16 in response to the gate signal supplied to the gate line 2.

The pixel electrode 16 is positioned between the passivation layer 50 and the gate insulating layer 44 and is in contact with the drain electrode 12 of the thin film transistor 6. Here, a part of the pixel electrode 16 is in contact with the drain electrode 12 under the drain electrode 12. The pixel electrode 16 generates a potential difference from the common electrode 18 by the charged pixel voltage. This potential difference causes the liquid crystal to rotate by dielectric anisotropy and transmits light incident from the light source via the pixel electrode 16 toward the upper substrate.

The storage capacitor 20 includes a front gate line 2 and a pixel electrode 16 overlapping the gate line 2 with the gate insulating layer 44 interposed therebetween. The storage capacitor 20 allows the pixel voltage charged in the pixel electrode 16 to be stably maintained until the next pixel voltage is charged.

The common electrode 18 has a plurality of slits S formed on the passivation layer 50 and overlapping the pixel electrode 16. The common electrode 18 positioned in the region overlapping the pixel electrode 16 forms an electric field with the pixel electrode 16 to control the liquidity of the liquid crystal.

As described above, the thin film transistor array substrate illustrated in FIGS. 1 and 2 may be formed in a region not overlapped with the pixel electrode 16 by forming the common electrode 18 on the passivation layer 50. Accordingly, as the area of the common electrode 18 can be maximized, the resistance in the common electrode 18 can be minimized.

However, as shown in FIGS. 1 and 2, the common electrode 18 is also positioned on the thin film transistor 6, causing the thin film transistor 6 to malfunction.

That is, although the thin film transistor 6 should be turned on only by the gate voltage supplied to the gate electrode 8 during the scanning period, the thin film transistor 6 is turned on even in the non-scanning period due to the reference voltage supplied to the common electrode 8. Things happen. As a result, a leakage current is generated to prevent the pixel voltage charged in the storage capacitor 20 from being normally maintained, thereby causing a problem of deterioration of display quality.

Accordingly, it is an object of the present invention to provide a thin film transistor array substrate and a method of manufacturing the same, which can prevent degradation of display quality by preventing malfunction and leakage current of the thin film transistor.

In order to achieve the above object, a thin film transistor array substrate according to an embodiment of the present invention includes a gate line and a data line crossing each other with a gate insulating film therebetween; A thin film transistor formed at an intersection of the gate line and the data line; A pixel electrode connected to the thin film transistor; A protective film formed to cover the pixel electrode; A common electrode is formed on the passivation layer to form an electric field with the pixel electrode. The common electrode includes a plurality of slits in a region overlapping the pixel electrode and is not overlapped with the thin film transistor.

The thin film transistor may include a gate electrode connected to the gate line; A source electrode connected to the data line; A drain electrode facing the source electrode; And a semiconductor pattern forming a channel between the source electrode and the drain electrode.

The pixel electrode is in contact with the drain electrode under the drain electrode.

The pixel electrode is in contact with the drain electrode on the drain electrode.

A gate pad portion for supplying a gate voltage to the gate line, the gate pad portion having a gate pad lower electrode connected to the gate line; And a gate pad upper electrode contacting the gate pad lower electrode through a first contact hole penetrating the passivation layer and the gate insulating layer.

A data pad unit for supplying a data voltage to the data line, the data pad unit comprising: a data pad lower electrode connected to the data line; And a data pad upper electrode contacting the data pad lower electrode through a second contact hole penetrating the passivation layer.

The semiconductor pattern is positioned under the data line, source electrode, drain electrode, and data pad lower electrode, respectively.

The pixel electrode partially overlaps the gate line with the gate insulating layer interposed therebetween to form a storage capacitor.

A method of manufacturing a thin film transistor array substrate according to the present invention includes forming a gate electrode, a gate line connected to the gate electrode, and the gate line of a thin film transistor on a substrate; Forming a data line crossing the gate line, a thin film transistor connected to the data line, and a pixel electrode connected to the thin film transistor with a gate insulating film interposed therebetween; Forming a protective film covering the pixel electrode; A region on the passivation layer and overlapping the pixel electrode includes a plurality of slits and forms a common electrode that is not overlapped with the thin film transistor.

The forming of the data line, the thin film transistor, and the pixel electrode may include forming the pixel electrode on the gate insulating layer; Forming a semiconductor pattern of the thin film transistor; And forming the data line, the source electrode in contact with the data line, and the drain electrode in contact with the pixel electrode.

The forming of the data line, the thin film transistor, and the pixel electrode may include forming a source drain pattern including the data line, a source electrode and a drain electrode of the thin film transistor, and forming a semiconductor pattern under the source drain pattern. Making a step; Forming a pixel electrode in contact with the drain electrode.

And forming a gate pad portion for supplying a gate voltage to the gate line, wherein the gate pad portion is formed at the same time as the gate pad lower electrode and the common electrode and penetrates the passivation layer and the gate insulating layer. And a gate pad upper electrode contacting the gate pad lower electrode through a first contact hole.

And forming a data pad unit for supplying a data voltage to the data line, the data pad lower electrode formed at the same time as the data line and the second contact hole formed at the same time as the common electrode and passing through the passivation layer. And a data pad upper electrode in contact with the data pad lower electrode.

Other objects and advantages of the present invention will become apparent from the following description of preferred embodiments of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 3 to 7B.

3 is a plan view illustrating a thin film transistor array substrate according to an exemplary embodiment of the present invention, and FIG. 4 is a cross-sectional view taken along line II-II 'of FIG. 3.

The thin film transistor array substrate illustrated in FIGS. 3 and 4 includes a gate line 102 and a data line 104 formed to intersect on a lower substrate 142 with a gate insulating layer 144 therebetween, and a thin film formed at each intersection thereof. A transistor 106, a pixel electrode 116 formed in a cell region provided in an intersecting structure thereof, a storage capacitor 120 formed at an overlapping portion of the pixel electrode 116 and the front gate line 102, and a gate line 102; ), And a gate pad portion 126 connected to the () and a data pad portion 134 connected to the data line 104.

The thin film transistor 106 includes a gate electrode 108 connected to the gate line 102, a source electrode 110 connected to the data line 104, and a drain electrode 112 connected to the pixel electrode 116. And an active layer 114 overlapping the gate electrode 108 and forming a channel between the source electrode 110 and the drain electrode 112. An ohmic contact layer 148 for ohmic contact with the source electrode 110 and the drain electrode 112 is further formed on the active layer 114. Hereinafter, the active layer 114 and the ohmic contact layer 148 are referred to as a semiconductor pattern 149.

The thin film transistor 106 keeps the pixel voltage signal supplied to the data line 104 charged to the pixel electrode 116 in response to the gate signal supplied to the gate line 102.

The pixel electrode 116 is positioned between the passivation layer 150 and the gate insulating layer 144 and is in contact with the drain electrode 112 of the thin film transistor 106. Here, a part of the pixel electrode 116 is in contact with the drain electrode 112 under the drain electrode 112. The pixel electrode 116 generates a potential difference from the common electrode 118 by the charged pixel voltage. This potential difference causes the liquid crystal to rotate by dielectric anisotropy and transmits light incident from the light source via the pixel electrode 116 toward the upper substrate.

The storage capacitor 120 includes a front gate line 102 and a pixel electrode 116 overlapping the gate line 102 and the gate insulating layer 144 therebetween. The storage capacitor 120 keeps the pixel voltage charged in the pixel electrode 116 stable until the next pixel voltage is charged.

The gate pad portion 126 is formed through the gate pad lower electrode 128 extending from the gate line 102, and the gate pad lower electrode through the first contact hole 130 penetrating the gate insulating layer 144 and the passivation layer 150. And a gate pad upper electrode 132 connected to 128.

The data pad unit 134 is connected to the data pad lower electrode 136 through the data pad lower electrode 136 extending from the data line 104 and the second contact hole 138 penetrating the passivation layer 150. The data pad upper electrode 140 is formed.

The common electrode 118 is disposed on the passivation layer 150 and includes a plurality of slits S in an area overlapping the pixel electrode 116. At the same time, the common electrode 118 is formed so as not to overlap the thin film transistor 106. That is, since the common electrode 118 is formed to be removed from the region overlapping the thin film transistor 106, the region P1 in which the common electrode 118 is not positioned is present on the thin film transistor 106. Accordingly, the distance between the active layer 114 and the common electrode 118 of the thin film transistor 106 can be sufficiently spaced apart so that the active layer 114 is not activated by the reference voltage at the common electrode 118. As a result, malfunction of the thin film transistor 106 can be prevented so that no leakage current can be generated, thereby preventing the display quality from deteriorating.

5A to 5F illustrate a method of manufacturing the thin film transistor substrate of FIG. 4 step by step.

Referring to FIG. 5A, gate patterns are formed on the lower substrate 142.

The gate metal layer is formed on the lower substrate 142 through a deposition method such as a sputtering method. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a mask to form gate patterns including the gate line 102, the gate electrode 108, and the gate pad lower electrode 128. As the gate metal, chromium (Cr), molybdenum (Mo), aluminum-based metal, etc. are used in a single layer or a double layer structure.

Referring to FIG. 5B, a gate insulating layer 144 and a pixel electrode 116 are formed on the lower substrate 142 on which the gate patterns are formed.

The gate insulating layer 144 is formed on the lower substrate 142 on which the gate patterns are formed by depositing an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) through a deposition method such as PECVD.

After the gate insulating layer 144 is formed, the transparent electrode material is deposited on the entire surface by a deposition method such as sputtering. Subsequently, the pixel electrode 116 is formed by patterning the transparent electrode material through a photolithography process and an etching process using a mask. The pixel electrode 116 partially overlaps the gate line 102 with the gate insulating layer 144 therebetween to form the storage capacitor 120.

As the transparent electrode material, indium tin oxide (ITO), tin oxide (TO), or indium zinc oxide (IZO) is used.

Referring to FIG. 5C, a semiconductor pattern 149 including an active layer 114 and an ohmic contact layer 148 is formed on the gate insulating layer 144 on which the pixel electrode 116 is formed.

An amorphous silicon layer and an n + amorphous silicon layer are sequentially formed on the gate insulating layer 144. Subsequently, the amorphous silicon layer and the n + amorphous silicon layer are patterned by a photolithography process and an etching process using a mask to form a semiconductor pattern 149 including the active layer 114 and the ohmic contact layer 148. The pixel electrode 116 and the semiconductor pattern 149 may partially overlap or contact each other.

5B and 5C, the semiconductor pattern 149 is formed after the pixel electrode 116 is formed. However, the semiconductor pattern 149 may be formed first, and then the pixel electrode 116 may be formed.

Referring to FIG. 5D, a source drain pattern is formed on the gate insulating layer 144 on which the semiconductor pattern 149 is formed.

A source / drain metal layer is formed on the gate insulating layer 144 on which the semiconductor pattern 149 is formed through a deposition method such as sputtering.

The photoresist pattern is formed on the source / drain metal layer by a photolithography process using a mask, and the source / drain metal layer is patterned by a wet etching process using the photoresist pattern, thereby forming the data line 104, the source electrode 110, and the source thereof. Source / drain patterns including the electrode 110, the drain electrode 112, and the data pad lower electrode 136 are formed. At the same time, the ohmic contact layer 148 of the channel region is exposed to the outside. Thereafter, an etching process is further performed to remove the exposed ohmic contact layer 148 to expose the active layer 114 of the channel region. As a result, the thin film transistor 106 is completed.

As the source / drain metal, molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy), copper (Cu), aluminum-based metal and the like are used.

Referring to FIG. 5E, the passivation layer 150 including the first and second contact holes 130 and 138 is formed on the gate insulating layer 44 on which the source / drain patterns are formed.

The passivation layer 150 is entirely formed on the gate insulating layer 144 on which the source / drain patterns are formed by a deposition method such as PECVD. The passivation layer 150 is patterned by a photolithography process and an etching process using a mask to form first and second contact holes 130 and 138. The first contact hole 130 passes through the passivation layer 150 and the gate insulating layer 144 to expose the gate pad lower electrode 128. The second contact hole 138 penetrates the passivation layer 150 to expose the data pad lower electrode 136.

As the material of the protective film 150, an inorganic insulating material such as the gate insulating film 144, an acryl based organic compound having a small dielectric constant, or an organic insulating material such as BCB or PFCB is used.

Referring to FIG. 5F, a transparent electrode pattern including the common electrode 118 is formed on the passivation layer 50.

The transparent electrode material is entirely deposited on the passivation layer 50 by a deposition method such as sputtering. Subsequently, the transparent electrode material is etched through a photolithography process and an etching process using a mask to form transparent electrode patterns including the common electrode 118, the gate pad upper electrode 132, and the data pad upper electrode 140. . The common electrode 118 is formed with a plurality of slits S in an area overlapping the pixel electrode 116. At the same time, as the transparent electrode material is formed to be removed from the region overlapping the thin film transistor 106, a region P1 in which the common electrode 118 is not positioned is present on the thin film transistor 106.

The gate pad upper electrode 132 is electrically connected to the gate pad lower electrode 128 through the first contact hole 130. The data pad upper electrode 140 is electrically connected to the data pad lower electrode 136 through the second contact hole 138. As the transparent electrode material, indium tin oxide (ITO), tin oxide (TO), or indium zinc oxide (IZO) is used.

6 is a cross-sectional view illustrating a thin film transistor array substrate according to still another embodiment of the present invention.

In the thin film transistor array substrate illustrated in FIG. 6, a source drain pattern (data line, source electrode, drain electrode, etc.) and a semiconductor pattern 149 are formed by one mask process. Therefore, the source drain pattern and the semiconductor pattern 149 are positioned to overlap each other. That is, the semiconductor pattern 149 is disposed under the data pad lower electrode 136, the data line 104, the source electrode 110, and the drain electrode 112, respectively. The pixel electrode 116 is in contact with the drain electrode 112 on the drain electrode 112.

Except for these structural differences, the thin film transistor array substrate illustrated in FIG. 6 has the same structure and function as the thin film transistor array substrate illustrated in FIGS. 3 and 4. Accordingly, the thin film transistor array substrate illustrated in FIG. 6 may prevent the thin film transistor 106 and the common electrode 118 from being overlapped, thereby preventing malfunction and leakage current of the thin film transistor.

Furthermore, the semiconductor pattern 149 and the source / drain pattern in the thin film transistor array substrate illustrated in FIG. 6 may be simultaneously formed by one mask process using a halftone mask or a semi-transmissive mask.

Hereinafter, a manufacturing process of the thin film transistor array substrate illustrated in FIG. 6 will be described with reference to FIGS. 7A and 7B.

First, after the gate pattern is formed by the same method as in FIG. 5A, the gate insulating layer 144 is formed. An amorphous silicon layer, an n + amorphous silicon layer, and a source / drain metal layer are sequentially formed on the gate insulating layer 144.

A photoresist pattern is formed on the source / drain metal layer by a photolithography process using a halftone mask or a semi-transmissive mask. Accordingly, the photoresist pattern of the channel region of the thin film transistor has a height lower than that of other source / drain pattern portions.

Subsequently, the source / drain metal layer is patterned by a wet etching process using a photoresist pattern, so that the data line 104, the source electrode 110, the drain electrode 112 integrated with the source electrode 110, and the data pad lower electrode ( Source / drain patterns comprising 136 are formed.

Then, the n + amorphous silicon layer and the amorphous silicon layer are simultaneously patterned by a dry etching process using the same photoresist pattern to form the ohmic contact layer 148 and the active layer 114.

The source / drain pattern of the channel portion and the ohmic contact layer 148 are etched by a dry etching process after the photoresist pattern having a relatively low height in the channel portion is removed by an ashing process. Accordingly, when the active layer 114 of the channel region is exposed and the active layer 114 is not activated, the source electrode 110 and the drain electrode 112 are electrically separated.

Accordingly, as shown in FIG. 7A, both the source / drain pattern and the semiconductor pattern may be formed.

Subsequently, after the transparent electrode material is deposited on the entire surface, the transparent electrode material is patterned through a photolithography process and an etching process using a mask to form a pixel electrode 116 contacting the drain electrode 112. The pixel electrode 116 is in direct contact with the top surface of the drain electrode 112.

Subsequently, as the forming process is performed in the same process as that of FIGS. 5E and 5F, the passivation layer 150 and the common electrode 118 are formed.

As a result, the thin film transistor array substrate shown in FIG. 6 can be simplified compared with the thin film transistor array substrate shown in FIGS. 3 and 4.

As described above, in the thin film transistor array substrate and the method of manufacturing the same, a plurality of slits are formed in a region in which the common electrode is disposed on the passivation layer and overlaps the pixel electrode. At the same time, the common electrode is formed so as not to overlap with the thin film transistor. Accordingly, the active layer of the thin film transistor is not activated by the reference voltage at the common electrode, thereby preventing malfunction and leakage current of the thin film transistor. As a result, the degradation of display quality can be prevented.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (13)

A gate line and a data line crossing each other with the gate insulating film interposed therebetween; A thin film transistor formed at an intersection of the gate line and the data line; A pixel electrode connected to the thin film transistor; A protective film formed to cover the pixel electrode; A common electrode formed on the passivation layer and forming an electric field with the pixel electrode; The common electrode may include a plurality of slits in a region overlapping the pixel electrode and may be non-overlapping with the thin film transistor. The method of claim 1, The thin film transistor A gate electrode connected to the gate line; A source electrode connected to the data line; A drain electrode facing the source electrode; And a semiconductor pattern forming a channel between the source electrode and the drain electrode. The method of claim 2, The pixel electrode is in contact with the drain electrode under the drain electrode. The method of claim 2, The pixel electrode is in contact with the drain electrode on the drain electrode. The method of claim 1, A gate pad unit is further provided to supply a gate voltage to the gate line. The gate pad part A gate pad lower electrode connected to the gate line; And a gate pad upper electrode contacting the gate pad lower electrode through a first contact hole passing through the passivation layer and the gate insulating layer. The method of claim 2, And a data pad unit for supplying a data voltage to the data line. The data pad unit A data pad lower electrode connected to the data line; And a data pad upper electrode contacting the data pad lower electrode through a second contact hole penetrating through the passivation layer. The method of claim 6, And the semiconductor pattern is disposed under the data line, the source electrode, the drain electrode, and the data pad lower electrode, respectively. The method of claim 1, And the pixel electrode partially overlaps the gate line with the gate insulating layer interposed therebetween to form a storage capacitor. Forming a gate electrode, a gate line connected to the gate electrode, and the gate line of the thin film transistor on a substrate; Forming a data line crossing the gate line, a thin film transistor connected to the data line, and a pixel electrode connected to the thin film transistor with a gate insulating film interposed therebetween; Forming a protective film covering the pixel electrode; And forming a common electrode on the passivation layer and overlapping the pixel electrode, the common electrode including a plurality of slits and non-overlapping with the thin film transistor. The method of claim 9, Forming the data line, the thin film transistor and the pixel electrode, Forming the pixel electrode on the gate insulating film; Forming a semiconductor pattern of the thin film transistor; Forming a data line, a source electrode in contact with the data line, and a drain electrode in contact with the pixel electrode. The method of claim 9, Forming the data line, the thin film transistor and the pixel electrode Forming a source drain pattern including the data line, the source electrode and the drain electrode of the thin film transistor, and forming a semiconductor pattern under the source drain pattern; And forming a pixel electrode in contact with the drain electrode. The method of claim 9, Forming a gate pad part supplying a gate voltage to the gate line; The gate pad part A gate pad lower electrode formed simultaneously with the gate line and a gate pad upper electrode formed simultaneously with the common electrode and contacting the gate pad lower electrode through a first contact hole penetrating through the passivation layer and the gate insulating layer; A method of manufacturing a thin film transistor array substrate. The method of claim 9, Forming a data pad part to supply a data voltage to the data line; And a data pad upper electrode formed at the same time as the data line and a data pad upper electrode formed at the same time as the common electrode and contacting the data pad lower electrode through a second contact hole penetrating through the passivation layer. Method of manufacturing a transistor array substrate.

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