KR101273143B1 - Method and device for manufacturing field-effect transistor - Google Patents

Abstract

Provided are a method for manufacturing a field effect transistor and an apparatus for manufacturing the same that can protect an active layer from an etchant without being exposed to an atmospheric atmosphere.
In the method for manufacturing a field effect transistor according to one embodiment of the present invention, an active layer 15 (IGZO film 15F) having an In—Ga—Zn—O based composition is formed on a substrate 10 by a sputtering method. And a step of forming a stopper layer 16 (stopper layer forming film 16F) on the active layer that protects the active layer from an etchant with respect to the active layer by a sputtering method, and the stopper layer. Etching the active layer as a mask. By forming the stopper layer by the sputtering method, it is possible to form the stopper layer after the active layer is formed without exposing the active layer to the atmosphere. Thereby, deterioration of the film quality resulting from adhesion of moisture or impurities in the air to the surface of the active layer can be prevented.

Description

FIELD OF THE INVENTION AND METHOD FOR MANUFACTURING A Field Effect Transistor

The present invention relates to a method and apparatus for manufacturing a field effect transistor having an active layer formed of InGaZnO-based semiconductor oxide.

In recent years, active matrix liquid crystal displays have been widely used. The active matrix liquid crystal display includes a field effect type thin film transistor (TFT) as a switching element for each pixel.

As the thin film transistors, there are known polysilicon thin film transistors in which the active layer is made of polysilicon, and amorphous silicon thin film transistors in which the active layer is made of amorphous silicon.

Amorphous silicon type thin film transistors have an advantage that they can be formed uniformly on a substrate having a relatively large area because the active layer is easier to manufacture than polysilicon thin film transistors.

On the other hand, development of a transparent amorphous oxide thin film is progressing as an active layer material which can implement | achieve higher mobility of carriers (electrons, holes) than amorphous silicon. For example, Patent Document 1 describes a field effect transistor using a homolog gas compound InMO ₃ (ZnO) _m (M = In, Fe, Ga or Al, m = 1 or more and an integer less than 50) as an active layer. In addition, Patent Document 2 describes a method for manufacturing a field effect transistor in which a target material composed of a polycrystalline sintered body having an InGaO ₃ (ZnO) ₄ composition is formed to form an In-Ga-Zn-O-based active layer. have.

In an amorphous silicon type thin film transistor, an active layer made of amorphous silicon is formed by CVD. On the other hand, since the In-Ga-Zn-O-based active layer cannot be formed by the CVD method, it is necessary to form the film by the sputtering method. In-Ga-Zn-O-based thin films are soluble in acids and alkalis. For this reason, in the patterning process using an etchant (etching liquid), it is necessary to form a protective layer for protecting the In—Ga—Zn—O thin film from the etchant. At the time of pattern etching of a thin film, the resist mask comprised from the photosensitive resin is used widely widely.

Patent Document 1: Japanese Patent Laid-Open No. 2004-103957 (paragraph [0010]) Patent Document 2: Japanese Patent Application Laid-Open No. 2006-165527 (paragraphs [0103] to [0119])

However, the resist mask is usually formed under an atmospheric atmosphere. For this reason, when the said protective layer is comprised by a resist mask, an active layer is exposed to an atmospheric atmosphere after formation of an active layer. For this reason, since moisture and impurities in the air adhere to the surface of the active layer, the film quality of the active layer may be damaged. In addition, a large amount of time is required to form the protective layer, which may cause a decrease in productivity.

In view of the above circumstances, an object of the present invention is to provide a method for manufacturing a field effect transistor and an apparatus for producing the field effect transistor which can protect an active layer from an etchant without being exposed to an atmospheric atmosphere.

The manufacturing method of the field effect transistor which concerns on one form of this invention includes the process of forming the active layer which has In-Ga-Zn-O type composition on a base material by the sputtering method. On the active layer, a stopper layer which protects the active layer from an etchant with respect to the active layer is formed by the sputtering method. The active layer is etched using the stopper layer as a mask.

The manufacturing apparatus of the field effect transistor which concerns on one form of this invention is a manufacturing apparatus of the field effect transistor for forming an active layer and the stopper layer which protects the said active layer from the etchant with respect to the said active layer on a base material, respectively. Related to. The manufacturing apparatus includes a first film forming chamber and a second film forming chamber. The first deposition chamber includes a first sputtering cathode for depositing the active layer having an In—Ga—Zn—O based composition on the substrate. The second film forming chamber includes a second sputtering cathode for forming the stopper layer formed of a silicon oxide film or a silicon nitride film on the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS It is main sectional drawing of each process explaining the manufacturing method of the field effect transistor which concerns on 1st Embodiment of this invention.
2 is an essential part cross sectional view of each step for explaining a method for manufacturing a field effect transistor according to the first embodiment of the present invention.
3 is an essential part cross sectional view of each step for explaining a method for manufacturing a field effect transistor according to the first embodiment of the present invention.
4 is an essential part cross sectional view of each step for explaining a method for manufacturing a field effect transistor according to the first embodiment of the present invention.
5 is an essential part cross sectional view of each step illustrating a method for manufacturing a field effect transistor according to the first embodiment of the present invention.
6 is a schematic configuration diagram of an apparatus for manufacturing a field effect transistor according to the first embodiment of the present invention.
7 is a schematic cross-sectional view showing the configuration of a field effect transistor according to a second embodiment of the present invention.
8 is a schematic configuration diagram of an apparatus for manufacturing a field effect transistor according to a second embodiment of the present invention.
9 is a schematic cross-sectional view showing the configuration of a field effect transistor according to a third embodiment of the present invention.
10 is a schematic configuration diagram of an apparatus for manufacturing a field effect transistor according to a third embodiment of the present invention.
11 is a schematic configuration diagram of an apparatus for manufacturing a field effect transistor according to a fourth embodiment of the present invention.

The manufacturing method of the field effect transistor which concerns on one Embodiment of this invention includes the process of forming the active layer which has In-Ga-Zn-O type composition on a base material by the sputtering method. On the active layer, a stopper layer for protecting the active layer from an etchant with respect to the active layer is formed by the sputtering method. The active layer is etched using the stopper layer as a mask.

In the method for manufacturing a field effect transistor, a stopper layer is formed by a sputtering method. This makes it possible to form a stopper layer after the active layer is formed without exposing the active layer to the atmosphere, so that deterioration of the film quality due to adhesion of moisture or impurities in the air to the surface of the active layer can be prevented. In addition, since the stopper layer can be continuously formed after the formation of the active layer, the process time required for the formation of the stopper layer can be shortened, and the productivity can be improved.

The base material is typically a glass substrate. The size of the substrate is not particularly limited.

The active layer may be formed by a reactive sputtering method with an oxidizing gas (for example, O ₂ , O ₃ , H ₂ O, or the like). A sputtering target for forming an In-Ga-Zn-O thin film may be used with a single target of In-Ga-Zn-O, and may be combined with an In ₂ O ₃ target, a Ga ₂ O ₃ target, and a ZnO target. The same plurality of targets may be used. In the sputtering film formation in an oxygen atmosphere, the oxygen concentration in the film can be easily controlled by controlling the partial pressure (flow rate) of oxygen to be introduced.

After forming the said active layer, the said stopper layer may be formed into a film continuously in the film formation chamber of the said active layer.

As a result, the formation of the stopper layer can be performed without carrying out the substrate from the film formation chamber of the active layer, whereby the productivity can be further improved. In this case, apart from the sputtering target for forming the active layer, the sputtering target for forming the stopper layer is disposed in the film forming chamber. In addition, each sputtering target can be used separately for every film-forming process.

The step of forming the stopper layer includes a step of forming a first insulating film composed of a silicon oxide film or a silicon nitride film on the active layer by a sputtering method, and a second composed of a metal oxide film on the first insulating film. The process of forming an insulating film by the sputtering method may be included.

Alternatively, the step of forming the stopper layer includes a step of forming a first insulating film made of a metal oxide film on the active layer by a sputtering method, and a silicon oxide film or a silicon nitride film formed on the first insulating film. The process of forming a 2nd insulating film by the sputtering method may be included.

Thus, by making a stopper layer a multilayer film, the various functions calculated | required as a stopper layer can be ensured. In the above example, the first insulating film has a function of securing a predetermined electrical insulating property, and the second insulating film has a function of securing a predetermined barrier property.

The first insulating film and the second insulating film may be continuously formed in the same chamber.

By continuously forming the first and second insulating films, the stopper layer can be formed into a single film in one chamber, and the productivity can be improved. In this case, a sputtering target for forming the first insulating film and a sputtering target for forming the second insulating film are disposed in the chamber. In addition, each sputtering target can be used separately for every film-forming process.

After forming the said active layer, the said stopper layer may be formed into a film continuously in the film formation chamber of the said active layer.

This makes it possible to form the stopper layer without carrying the substrate out of the active layer film formation chamber, so that the productivity can be further improved.

The substrate includes a gate electrode, and before forming the active layer, a gate insulating film may be further formed to cover the gate electrode.

Thereby, a bottom gate type field effect transistor can be manufactured. The gate electrode may be an electrode film formed on the substrate, and the substrate itself may be constituted by the gate electrode.

The gate insulating film may be formed by a sputtering method.

Thereby, the gate insulating film, the active layer, and the stopper layer can be formed into a film continuously in a vacuum atmosphere.

The step of forming the gate insulating film includes a step of forming a first gate insulating film composed of a metal oxide film on the gate electrode by a sputtering method, and a silicon oxide film or silicon nitride film on the first gate insulating film. It may include a step of forming the second gate insulating film to be formed by a sputtering method.

Alternatively, the step of forming the gate insulating film includes a step of forming a first gate insulating film made of a silicon oxide film or a silicon nitride film on the gate electrode, and a second oxide film made of a metal oxide film on the first gate insulating film. The process of forming a gate insulating film may be included.

By forming the gate insulating film in this manner, various functions required as the gate insulating film can be ensured. In the above example, the first insulating film has a function of securing a predetermined barrier property, and the second insulating film has a function of securing a predetermined electrical insulation property.

A protective film may be formed to cover the active layer, and a source electrode and a drain electrode may be formed to contact the active layer. The protective film can be formed by a sputtering method.

The manufacturing apparatus of the field effect transistor which concerns on one Embodiment of this invention manufactures the field effect transistor for forming an active layer and the stopper layer which protects the said active layer from the etchant with respect to the said active layer on a base material, respectively. Associated with the device. The manufacturing apparatus includes a first film forming chamber and a second film forming chamber. The first deposition chamber includes a first sputtering cathode for depositing the active layer having an In—Ga—Zn—O based composition on the substrate. The second film forming chamber includes a second sputtering cathode for forming the stopper layer formed of a silicon oxide film or a silicon nitride film on the substrate.

In the apparatus for manufacturing a field effect transistor, an active layer having an In—Ga—Zn—O-based composition is formed in a first film forming chamber by sputtering, and a stopper layer composed of a silicon oxide film or a silicon nitride film is formed in the second film forming chamber. It is made to form into a film by the sputtering method. This makes it possible to form a stopper layer after the active layer is formed without exposing the active layer to the atmosphere, so that deterioration of the film quality due to adhesion of moisture or impurities in the air to the surface of the active layer can be prevented. In addition, since the stopper layer can be continuously formed after the formation of the active layer, the process time required for the formation of the stopper layer can be shortened and the productivity can be improved.

The first deposition chamber and the second deposition chamber may be configured as a common deposition chamber.

This makes it possible to continuously form the active layer and the stopper layer in the same chamber.

The second sputtering cathode may have a first target material composed of silicon oxide or silicon nitride and a second target material composed of metal oxide.

This makes it possible to continuously form a stopper layer having a multilayer structure of a first insulating film composed of a silicon oxide film or a silicon nitride film and a second insulating film composed of a metal oxide film, thereby obtaining a stopper layer having a predetermined insulating property and barrier property. Can be.

The apparatus for manufacturing a field effect transistor may further include a third film forming chamber for forming a gate insulating film on the substrate.

This makes it possible to form the gate insulating film, the active layer and the stopper layer in the same device.

Alternatively, the field effect transistor manufacturing apparatus may further include a third film forming chamber including a third sputtering cathode for forming a gate insulating film on the substrate.

This makes it possible to form the gate insulating film, the active layer and the stopper layer in the same device.

The third sputtering cathode may include a third target material composed of a metal oxide and a fourth target material composed of silicon oxide or silicon nitride.

Thereby, for example, continuous film formation of a stopper layer having a multilayer structure of a first gate insulating film composed of a silicon oxide film or a silicon nitride film and a second gate insulating film composed of a metal oxide film is possible, and a gate having a predetermined insulating property and barrier property can be formed. An insulating film can be obtained.

The manufacturing apparatus may further include a transfer chamber capable of vacuum evacuation having a transfer robot for exchanging the substrate with respect to the first deposition chamber and the second deposition chamber. The first film forming chamber and the second film forming chamber are provided around the transport chamber. That is, the said manufacturing apparatus can be comprised as a cluster type film-forming apparatus.

The said manufacturing apparatus may further be equipped with the conveyance mechanism which conveys the said base material from the said 1st film-forming chamber to the said 2nd film-forming chamber. The first deposition chamber and the second deposition chamber are disposed adjacent to each other. That is, the said manufacturing apparatus can be comprised as an inline film-forming apparatus.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<1st embodiment>

1-5 is sectional drawing of the principal part of each process explaining the manufacturing method of the field effect transistor which concerns on 1st Embodiment of this invention. In this embodiment, a method of manufacturing a field effect transistor having a so-called bottom gate transistor structure will be described.

First, as shown in FIG. 1A, a gate electrode film 11F is formed on one surface of the substrate 10.

The base material 10 is a glass substrate typically. The gate electrode film 11F is typically composed of a metal single layer film or a metal multilayer film such as molybdenum, chromium or aluminum, and is formed by, for example, a sputtering method. The thickness of the gate electrode film 11F is not particularly limited and is, for example, 300 nm.

Next, as shown in Figs. 1B to 1D, a resist mask 12 for patterning the gate electrode film 11F into a predetermined shape is formed. This process is provided with the formation process (FIG. 1 (B)), the exposure process (FIG. 1 (C)), and the image development process (FIG. 1D) of the photoresist 12F.

The photoresist 12F is formed by applying a liquid photosensitive material onto the gate electrode film 11F and then drying it. A dry film resistor may be used as the photoresist 12F. The formed photoresist 12F is exposed through the mask 13 and then developed. As a result, the resist mask 12 is formed on the gate electrode film 11F.

Subsequently, as shown in Fig. 1E, the gate electrode film 11F is etched using the resist mask 12 as a mask. As a result, the gate electrode 11 is formed on the surface of the substrate 10.

The etching method of the gate electrode film 11F is not specifically limited, The weight etching method may be sufficient, and the dry etching method may be sufficient. After etching, the resist mask 12 is removed. Although the ashing process using the plasma of oxygen gas is applied to the removal method of the resist mask 12, it is not limited to this, The dissolution removal using a chemical liquid may be sufficient.

Next, as shown in FIG. 2A, the gate insulating film 14 is formed on the surface of the substrate 10 to cover the gate electrode 11.

The gate insulating film 14 is typically composed of an oxide film or a nitride film such as a silicon oxide film (SiO ₂ ) or a silicon nitride film (SiNx), and is formed by, for example, a CVD method or a sputtering method. The thickness of the gate electrode film 11F is not particularly limited and is, for example, 200 nm to 500 nm.

Subsequently, as shown in FIG. 2B, a thin film having an In—Ga—Zn—O based composition on the gate insulating film 14 (hereinafter, simply referred to as an “IGZO film”. 15F) and a stopper layer The formation film 16F is formed in order.

The IGZO film 15F and the stopper layer forming film 16F are formed by the sputtering method. The IGZO film 15F and the stopper layer forming film 16F can be formed continuously. In this case, the sputtering target for forming the IGZO film 15F and the sputtering target for forming the stopper layer forming film 16F may be arranged in the same sputtering chamber. By changing the target to be used, the IGZO film 15F and the stopper layer forming film 16F can be formed independently of each other.

The IGZO film 15F is formed in a state in which the substrate 10 is heated to a predetermined temperature. In this embodiment, the active layer 15 (IGZO film 15F) is formed by the reactive sputtering method in which a reactant with oxygen is deposited on the substrate 10 by sputtering a target in an oxygen gas atmosphere. The discharge type may be any one of DC discharge, AC discharge, and RF discharge. It is also possible to employ a magnetron discharge method in which a permanent magnet is arranged on the back side of the target.

The film thickness of each of the IGZO film 15F and the stopper layer forming film 16F is not particularly limited. For example, the film thickness of the IGZO film 15F is 50 nm to 200 nm, and the film thickness of the stopper layer forming film 16F is. It is 30 nm-300 nm.

The IGZO film 15F constitutes an active layer (carrier layer) 15 of the transistor. The stopper layer forming film 16F protects the channel region of the IGZO film from the etchant in a step of patterning a metal film constituting a source electrode and a drain electrode described later, and a step of etching away an unnecessary region of the IGZO film 15F. It functions as an etching protective layer. The stopper layer forming film 16F is made of SiO ₂ , for example.

Next, as shown in Figs. 2C and 2D, after forming the resist mask 27 for patterning the stopper layer forming film 16F into a predetermined shape, through this resist mask 27 The stopper layer forming film 16F is etched. As a result, a stopper layer 16 is formed between the gate insulating film 14 and the IGZO film 15F to face the gate electrode 11.

After the resist mask 27 is removed, as shown in FIG. 2E, the metal film 17F is formed so as to cover the IGZO film 15F and the stopper layer 16.

The metal film 17F is typically composed of a metal single layer film or a metal multilayer film such as molybdenum, chromium or aluminum, and is formed by, for example, a sputtering method. The thickness of the metal film 17F is not particularly limited, and is, for example, 100 nm to 500 nm.

Subsequently, as illustrated in FIGS. 3A and 3B, the metal film 17F is patterned.

The patterning step of the metal film 17F includes a step of forming the resist mask 18 (FIG. 3A) and an etching step of the metal film 17F (FIG. 3B). The register mask 18 has a mask pattern for opening the region immediately above the stopper layer 16 and the peripheral region of each transistor. After the formation of the resist mask 18, the metal film 17F is etched according to the weight etching method. As a result, the metal film 17F is separated into the source electrode 17S and the drain electrode 17D. In the following description, these source electrodes 17S and the drain electrodes 17D are collectively referred to as source / drain electrodes 17.

In the formation process of the source / drain electrode 17, the stopper layer 16 functions as an etching stopper layer of the metal film 17F. In other words, the stopper layer 16 has a function of protecting the IGZO film 15F from an etchant (such as phosphoric acetic acid) with respect to the metal film 17F. The stopper layer 16 is formed to cover a region (hereinafter referred to as a "channel region") located between the source electrode 17S and the drain electrode 17D of the IGZO film 15F. Therefore, the channel region of the IGZO film 15F is not affected by the etching process of the metal film 17F.

Next, as shown in FIGS. 3C and 3D, the IGZO thin film 15F is etched using the resist mask 18 as a mask.

The etching method is not particularly limited, and may be a weight etching method or a dry etching method. By the etching process of the IGZO film 15F, the IGZO film 15F is isolated on a device basis and an active layer 15 composed of the IGZO film 15F is formed.

At this time, the stopper layer 16 functions as an etching protective film of the IGZO film 15F located in the channel region. That is, the stopper layer 16 has a function of protecting the channel region directly below the stopper layer 16 from an etchant (for example, an oxalic acid system) with respect to the IGZO film 15F. As a result, the channel region of the active layer 15 is not affected by the etching process of the IGZO film 15F.

After patterning the IGZO film 15F, the resist mask 18 is removed from the source / drain electrodes 17 by an ashing process or the like (Fig. 3 (D)).

Next, as shown in FIG. 4A, a protective film is formed so as to cover the source / drain electrode 17, the stopper layer 16, the active layer 15, and the gate insulating film 14 on the surface of the substrate 10. (Passivation film 19) is formed.

The protective film 19 is for securing predetermined electrical and material characteristics by blocking the transistor element including the active layer 15 from the outside air. The protective film 19 is typically composed of an oxide film or a nitride film such as a silicon oxide film (SiO ₂ ) or a silicon nitride film (SiNx), and is formed by, for example, a CVD method or a sputtering method. The thickness of the protective film 19 is not specifically limited, For example, they are 200 nm-500 nm.

Subsequently, as shown in FIGS. 4B to 4D, a contact hole 19a connected to the source / drain electrode 17 is formed in the protective film 19. This step includes a step of forming the resist mask 20 on the protective film 19 (FIG. 4B) and a step of etching the protective film 19 exposed from the opening 20a of the register mask 20 ( Fig. 4C and a step of removing the register mask 20 (Fig. 4D) are provided.

Although the dry etching method is employ | adopted as the formation of the contact hole 19a, the weight etching method may be employ | adopted. In addition, although not shown, the contact hole in contact with the source electrode 17S is also formed at any position.

Next, as shown to Fig.5 (A)-(D), the transparent conductive film 21 which contacts the source / drain electrode 17 through the contact hole 19a is formed. This step includes a step of forming the transparent conductive film 21F (FIG. 5 (A)), a step of forming the register mask 22 on the transparent conductive film 21F (FIG. 5 (B)), and a register. The process of etching the transparent conductive film 21F which is not covered by the mask 22 (FIG. 5C), and the process of removing the resist mask 20 (FIG. 5D) are provided.

The transparent conductive film 21F is typically composed of an ITO film or an IZO film, and is formed by, for example, a sputtering method or a CVD method. Although the weight etching method is employ | adopted for the etching of the transparent conductive film 21F, it is not limited to this, The dry etching method may be employ | adopted.

After the transistor element 100 formed of the transparent conductive film 21 shown in FIG. 5D is subjected to an annealing step for the purpose of structure relaxation of the active layer 15. As a result, desired transistor characteristics are imparted to the active layer 15.

As described above, the field effect transistor (transistor element 100) is manufactured.

In this embodiment, the IGZO film 15F constituting the active layer 15 and the stopper layer forming film 16F constituting the stopper layer 16 are respectively formed by the sputtering method. This makes it possible to form the stopper layer 16 after the IGZO film 15F (active layer 15) is formed without exposing the IGZO film 15F to the atmosphere, and thus the atmosphere to the surface of the active layer 15. Deterioration of the film quality due to adhesion of moisture or impurities in the film can be prevented.

In addition, since the stopper layer 16 can be continuously formed after the formation of the active layer 15, the process time required for the formation of the stopper layer 16 can be shortened, and the productivity can be improved.

6A and 6B are schematic configuration diagrams of a vacuum processing apparatus for performing a part of the manufacturing process of the transistor element 100 (field effect transistor) described above.

The vacuum processing apparatus 201 shown to FIG. 6 (A) is a single wafer type | mold (cluster type) vacuum processing apparatus, and several process chambers 211-215 arrange | positioned around the conveyance chamber 210 and the conveyance chamber 210 are shown. ). The process chamber includes a load chamber 211, a heating chamber 212, a CVD chamber 213, a sputter chamber 214, and an unload chamber 215. Although not shown, the transfer chamber 210 is provided with a transfer robot for transferring the substrate 10 to each processing chamber, and the transfer robot moves the substrate 10 to each processing chamber in a direction indicated by an arrow in the drawing, for example. Return. Both the transfer chamber 210 and each processing chamber are maintained at a predetermined vacuum degree, and transfer of the base material 10 between the processing chambers 211 to 215 via the transfer chamber 210 is vacuum. It is supposed to be carried out in an atmosphere.

Typically, the base material 10 (refer FIG. 1 (F)) in which the gate electrode 11 was formed is carried in to the load chamber 211. The said transfer robot conveys the base material 10 from the load chamber 211 to the heating chamber 212. In the heating chamber 212, the substrate 10 is heated, and moisture or the like adhering to or adsorbed on the surface is removed. The base material 10 is conveyed to the CVD chamber 213 after heating, and the gate insulating film 14 is formed in the CVD chamber 213 (FIG. 2 (A)). After the formation of the gate insulating film 14, the substrate 10 is transferred to the sputter chamber 214, and the IGZO film 15F and the stopper layer forming film 16F are formed in the sputter chamber 214 (FIG. 2B). )). After formation of the stopper layer forming film 16F, the substrate 10 is conveyed to the unloading chamber 215 and carried out to the outside of the vacuum processing apparatus 201.

The spatter chamber 214 includes a sputtering cathode Tc containing a target material for forming the IGZO film 15F and a sputtering cathode Ts containing a target material for forming the stopper layer forming film 16F. The sputtering target for forming the IGZO film 15F may be a single target of In-Ga-Zn-O, and a plurality of targets such as an In ₂ O ₃ target, a Ga ₂ O ₃ target, and a ZnO target may be used. You may. As the sputtering target for forming the stopper layer forming film 16F, a target of silicon oxide or silicon nitride is used, but is not limited thereto.

The spatter chamber 214 has a gas introduction system for introducing an oxidizing gas into the room, and the IGZO film 15F and the stopper layer forming film 16F can be formed by a reactive sputtering method with the oxidizing gas. Do. By controlling the partial pressure (flow rate) of the gas to be introduced, the oxygen concentration in the film can be easily controlled. Examples of the gas introduced into the spatter chamber 214 include O ₂ , O ₃ , H ₂ O and the like, but the gas is not limited thereto.

The vacuum processing apparatus 202 shown in FIG. 6B is also comprised by the single wafer type | mold (cluster type) vacuum processing apparatus. In the vacuum processing apparatus 202, the sputter chamber can be divided into a sputter chamber 214A for forming the IGZO film 15F and a sputter chamber 214B for forming the stopper layer forming film 16F.

According to the vacuum processing apparatuses 201 and 202 of the above structure, after forming the IGZO film 15F, the stopper layer forming film 16F can be formed without exposing the IGZO film 15F to the atmosphere. Thereby, deterioration of the film quality resulting from adhesion of moisture or impurities in the air to the surface of the IGZO film 15F can be prevented. In addition, since the stopper layer forming film 16F can be formed continuously after the IGZO film 15F is formed, the process time required for forming the stopper layer forming film 16F can be shortened, thereby improving productivity. can do.

In addition, according to the vacuum processing apparatus 201, the stopper layer forming film 16F can be formed continuously in the film forming chamber of the IGZO film 15F. This makes it possible to form the stopper layer forming film 16F without carrying out the substrate 10 from the film forming chamber of the IGZO film 15F, so that the productivity can be further improved.

&Lt; Second Embodiment >

7 shows a second embodiment of the present invention. In addition, in the figure, the same code | symbol is attached | subjected about the part corresponding to 1st Embodiment mentioned above, and the detailed description is abbreviate | omitted.

The transistor element 101 of this embodiment is manufactured through the same process as in the first embodiment. The transistor element 101 shown has a multilayer structure of the stopper layer 16 having the first insulating film 16A and the second insulating film 16B. It is different.

The semiconductor layer containing zinc (Zn) has low resistance to acids and alkalis and is easily etched. Therefore, when the active layer 15 is formed, a stopper layer 16 for protecting the etchant from the channel region of the IGZO film 15F is formed. The stopper layer 16 functions not only as an etching mask of the IGZO film 15F but also as an insulating film for maintaining electrical insulation between the source electrode 17S and the drain electrode 17D on the upper layer side of the active layer 15. Also have.

However, the silicon oxide film constituting the stopper layer 16 may not sufficiently prevent the incorporation of impurities from the atmosphere. If impurities from the atmosphere are mixed in the active layer 15, the transistor characteristics are misaligned.

For this reason, in this embodiment, the stopper layer 16 has a two-layer structure of a first insulating film 16A composed of a silicon oxide film or a silicon nitride film and a second insulating film 16B composed of a metal oxide film formed thereon. It was set as. The desired electrical insulation is ensured by the first insulating film 16A, and the barrier property against the mixing of impurities from the atmosphere is secured by the second insulating film 16B.

As the second insulating film 16B, a highly insulating metal oxide having a high barrier property against mixing of impurities from the atmosphere is used. As the second insulating film 16B, tantalum oxide (TaOx), alumina (Al ₂ O ₃ ), yttria (Y ₂ O ₃ ), or the like can be formed. By forming the second insulating film 16B on the upper layer side of the first insulating film 16A, a stopper layer excellent in barrier property against mixing of impurities from the atmosphere can be formed. As a result, the transistor characteristics can be stabilized.

The first insulating film 16A may be made of a metal oxide film, and the second insulating film 16B may be made of a silicon oxide film or a silicon nitride film. Even with such a configuration, it is possible to obtain the same effects as described above.

8A, 8B, and 8C are schematic configuration diagrams of a vacuum processing apparatus for performing a part of the manufacturing process of the transistor element 101 (field effect transistor) described above. In addition, about the part corresponding to FIG. 6, the same code | symbol is attached | subjected and the detailed description is abbreviate | omitted.

The vacuum processing apparatus 203 shown in FIG. 8 (A) is a single wafer type (cluster type) vacuum processing apparatus. The spatter chamber 214 includes a sputtering cathode Tc for forming the IGZO film 15F constituting the active layer 15, a sputtering cathode Ts1 for forming the first insulating film 16A of the stopper layer 16, and And a sputtering cathode Ts2 for forming the second insulating film 16B of the stopper layer 16, respectively.

Similarly, the vacuum processing apparatuses 204 and 205 shown in FIGS. 8B and 8C are also constituted by a single-leaf type (cluster type) vacuum processing apparatus. The vacuum processing apparatus 204 forms a first splitter chamber 214A for forming the IGZO film 15F, and a stopper layer forming film 16F (the first insulating film 16A and the second insulating film 16B). The second compactor chamber 214B is provided for this purpose. The vacuum processing apparatus 205 forms a first sputtering chamber 214A for forming the IGZO film 15F and a second sputtering chamber 214B for forming the first insulating film 16A constituting the stopper layer 16. ) And a third sputtering chamber 214C for forming the second insulating film 16B constituting the stopper layer 16.

Also in this embodiment, it is possible to form the stopper layer forming film 16F without exposing the IGZO film 15F to the atmosphere after the film formation of the IGZO film 15F, similarly to the first embodiment described above. Thereby, deterioration of the film quality resulting from adhesion of moisture or impurities in the air to the surface of the IGZO film 15F can be prevented. In addition, since the stopper layer forming film 16F can be formed continuously after the IGZO film 15F is formed, the process time required for forming the stopper layer forming film 16F can be shortened, thereby improving productivity. Can be.

In addition, according to the vacuum processing apparatus 203, the stopper layer forming film 16F can be formed continuously in the film forming chamber of the IGZO film 15F. This makes it possible to form the stopper layer forming film 16F without carrying out the substrate 10 from the film forming chamber of the IGZO film 15F, so that the productivity can be further improved.

&Lt; Third Embodiment >

9 shows a third embodiment of the present invention. In addition, in the figure, the same code | symbol is attached | subjected about the part corresponding to 1st and 2nd embodiment mentioned above, and the detailed description is abbreviate | omitted.

The transistor element 102 of this embodiment is manufactured through the same process as in the first embodiment. The transistor element 102 shown has the multilayer structure of the gate insulating film 14 and the 1st gate insulating film 14A and the 2nd gate insulating film 14B, The transistor element of 2nd Embodiment mentioned above ( 101).

The gate insulating film is formed for the purpose of ensuring electrical insulation between the gate electrode and the active layer. However, the gate insulating film composed of the silicon oxide film has a low barrier property against diffusion of impurities from the substrate (substrate), so that the predetermined insulating function cannot be secured by the diffusion of impurities from the substrate in the gate insulating film. There is a case. In this case, since the desired insulating function cannot be obtained in the gate insulating film, there is a fear that a deviation of the gate threshold voltage occurs, or an electrical leak between the active layer may occur.

Therefore, in the present embodiment, the gate insulating film 14 is formed by the first gate insulating film 14A composed of the metal oxide film and the second gate insulating film 14B composed of the silicon oxide film or silicon nitride film formed thereon. It was set as a layer structure. The desired barrier property is secured by the first gate insulating film 14A, and the desired electrical insulating property is secured by the second gate insulating film 14B.

As the first gate insulating film 14A, an insulating metal oxide having high barrier property against diffusion of impurities from the substrate is used. As the first gate insulating film 14A, tantalum oxide (TaOx), alumina (Al ₂ O ₃ ), yttria (Y ₂ O ₃ ), or the like can be formed. By forming the first gate insulating film 14A on the lower layer side of the second gate insulating film 14B, a gate insulating film excellent in barrier property against diffusion of impurities from the substrate can be formed. Thereby, it becomes possible to manufacture the transistor element which has desired transistor characteristic stably.

The first gate insulating film 14A may be made of a silicon oxide film or a silicon nitride film, and the second gate insulating film 14B may be made of a metal oxide film. Also with such a configuration, the same effects as described above can be obtained.

10A, 10B, and 10C are schematic configuration diagrams of a vacuum processing apparatus for performing a part of the manufacturing process of the transistor element 102 (field effect transistor) described above. In addition, the same code | symbol is attached | subjected about the part corresponding to FIG. 6 and FIG. 8, and the detailed description is abbreviate | omitted.

The vacuum processing apparatus 206 shown in FIG. 10 (A) is a sheet type (cluster type) vacuum processing apparatus. The vacuum processing apparatus 206 includes two sputter chambers 213A for forming the first gate insulating film 14A and a sputter chamber 213B for forming the second gate insulating film 14B. have. The spatter chamber 213A includes a sputtering cathode Tg1 for forming the first gate insulating film 14A, and the spatter chamber 213B includes a sputtering cathode Tg2 for forming the second gate insulating film 14B. Doing. The sputtering chambers for forming the IGZO film 15F constituting the active layer and the first and second insulating films 16A and 16B constituting the stopper layer 16 are constituted by a common sputtering chamber 214.

Similarly, the vacuum processing apparatuses 207 and 208 shown in FIG. 10 (B) and (C) are also comprised by the single wafer type | mold (cluster type) vacuum processing apparatus. The vacuum processing apparatus 207 includes a first sputter chamber 213 for forming the first and second gate insulating films 14A and 14B constituting the gate insulating film 14, and an IGZO film constituting the active layer 15. 2nd sputter chamber 214A for forming 15F, and 3rd sputter chamber 214B for forming the 1st and 2nd insulating films 16A and 16B which comprise the stopper layer 16 are provided. . The vacuum processing apparatus 208 includes a first sputter chamber 213A for forming the first gate insulating film 14A, a second sputter chamber 213B for forming the second gate insulating film 14B, and an IGZO film. Third sputtering chamber 214A for forming the film 15F, fourth sputtering chamber 214B for forming the first insulating film 16A, and fifth sputtering chamber for forming the second insulating film 16B ( 214C).

Also in this embodiment, it is possible to form the stopper layer forming film 16F without exposing the IGZO film 15F to the atmosphere after the film formation of the IGZO film 15F, similarly to the first and second embodiments described above. Become. Thereby, deterioration of the film quality resulting from adhesion of moisture or impurities in the air to the surface of the IGZO film 15F can be prevented. In addition, since the stopper layer forming film 16F can be formed continuously after the IGZO film 15F is formed, the process time required for forming the stopper layer forming film 16F can be shortened, thereby improving productivity. Can be.

In addition, according to the vacuum processing apparatus 208, since the gate insulating film 14 is formed into a film by the sputtering method, the introduction system of the source gas required for the CVD process and the removal equipment of the exhaust gas are unnecessary. Thereby, it becomes possible to aim at reduction of equipment cost and cleaning of a process.

&Lt; Fourth Embodiment &

11 (A), (B), and (C) are schematic configuration diagrams of a device for manufacturing a field effect transistor according to a fourth embodiment of the present invention. In this embodiment, the example in which the said manufacturing apparatus is comprised with the inline vacuum processing apparatus is demonstrated.

In addition, the vacuum processing apparatus may be a horizontal type which conveys a board | substrate in the attitude | position which rolled the board | substrate horizontally, and may be a vertical type | mold which conveys a board | substrate in the substantially upright attitude | position. When the substrate (substrate) size is large, the vertical type is advantageous in that the installation area can be reduced. Note that the film formation on the substrate 10 may be a through film forming a film in the process chamber while the substrate is being conveyed, and a film forming in the process chamber with the substrate stopped. ) May be adopted.

The vacuum processing apparatus 301 shown in FIG. 11A includes a load chamber 311, a first heating chamber 312, a CVD chamber 313, a buffer chamber 314, a first sputter chamber 315, The 2nd heating chamber 316, the 2nd sputter chamber 317, and the unloading chamber 318 are provided. Although the vacuum processing apparatus 301 is not shown in figure, the conveyance mechanism for conveying the base material 10 to each process chamber is provided, and this conveyance mechanism is directed from the load chamber 311 to the unload chamber 318, and the base material 10 is carried out. ) Is returned to each treatment chamber. Although not shown, valve mechanisms, such as a gate valve, are interposed between the adjacent process chambers, and the gate required at the time of conveyance of a base material is opened. Each of the processing chambers is maintained at a predetermined degree of vacuum, and the transfer of the substrate 10 between the processing chambers 311 to 318 is performed in a vacuum atmosphere.

Typically, the base material 10 (refer FIG. 1 (F)) in which the gate electrode 11 was formed is carried in to the load chamber 311. The base material 10 carried in the load chamber 311 is conveyed to the 1st heating chamber 312. In the first heating chamber 312, the substrate 10 is heated, and moisture or the like adhering to or adsorbed on the surface is removed. The base material 10 is conveyed to the CVD chamber 313 after heating, and the gate insulating film 14 is formed in the CVD chamber 313 (FIG. 2 (A)). After the formation of the gate insulating film 14, the substrate 10 is transferred to the first sputter chamber 314 through the buffer chamber 314, and the IGZO film 15F is formed in the first sputter chamber 314. After the formation of the IGZO film 15F, the substrate 10 is conveyed to the second heating chamber 316 and subjected to a heat treatment for imparting predetermined transistor characteristics to the IGZO film 15F in the second heating chamber 316. do. The base material 10 is conveyed to the 2nd sputtering chamber 317 after heating, and the stopper layer formation film 16F is formed into a film in 2nd sputtering chamber 317 (FIG. 2 (B)). After formation of the stopper layer forming film 16F, the base material 10 is conveyed to the unloading chamber 318 and carried out to the outside of the vacuum processing apparatus 301.

The buffer chamber 314 is provided for the purpose of ensuring atmospheric insulation between the CVD chamber 313 and the first sputter chamber 315. That is, in general, the CVD chamber is treated under low vacuum and different from the atmospheric gas as compared to the sputter chamber. For this reason, when arranging a CVD chamber and a spatter chamber adjoining in an inline vacuum processing apparatus, the inside of a spatter chamber is contaminated by the atmosphere in a CVD chamber flowing out into a sputter chamber. In order to suppress this, a buffer chamber kept at a higher vacuum than those of the processing chamber is interposed between the CVD chamber and the sputter chamber to prevent cross talk of the atmosphere between the CVD chamber and the sputter chamber.

In the vacuum processing apparatus 302 shown in FIG. 11B, the stopper layer 16 is constituted by a two-layer structure of the first insulating film 16A and the second insulating film 16B. It is used to manufacture the transistor element 101 (FIG. 7) which concerns. That is, the vacuum processing apparatus 302 is equipped with the spreader chamber 317A for forming the 1st insulating film 16A, and the spreader chamber 317B for forming the 2nd insulating film 16B.

In the vacuum processing apparatus 303 shown in FIG. 11C, the gate insulating film 14 has a two-layer structure of the first gate insulating film 14A and the second gate insulating film 14B, and the stopper layer 16 is provided. It consists of the two-layer structure of this 1st insulating film 16A and the 2nd insulating film 16B, and is used for manufacture of the transistor element 102 (FIG. 9) which concerns on 3rd Embodiment mentioned above. In other words, the vacuum processing apparatus 303 includes a splitter chamber 313A for forming the first gate insulating film 14A, a splitter chamber 313B for forming the second gate insulating film 14A, and a first insulating film ( A spreader chamber 317A for forming the film of 16A and a spreader chamber 317B for forming the second insulating film 16B are provided.

Also in this embodiment, it is possible to form the stopper layer forming film 16F without exposing the IGZO film 15F to the atmosphere after the film formation of the IGZO film 15F, similarly to the first and second embodiments described above. Become. Thereby, deterioration of the film quality resulting from adhesion of moisture or impurities in the air to the surface of the IGZO film 15F can be prevented. In addition, since the stopper layer forming film 16F can be formed continuously after the IGZO film 15F is formed, the process time required for forming the stopper layer forming film 16F can be shortened, thereby improving productivity. Can be.

In addition, according to the vacuum processing apparatus 303, since the gate insulating film 14 is formed into a film by the sputtering method, the introduction system of the source gas required for the CVD process and the removal equipment of the exhaust gas are unnecessary. Thereby, it becomes possible to aim at reduction of equipment cost and cleaning of a process. In addition, since the gate insulating film 14 is formed by the sputtering method, it is possible to eliminate the necessity of providing a buffer chamber between the sputter chamber for forming the active layer.

As mentioned above, although embodiment of this invention was described, of course, this invention is not limited to this, A various deformation | transformation is possible for it based on the technical idea of this invention.

For example, in the above embodiment, although the manufacturing method of the bottom gate type field effect transistor was demonstrated as an example, this invention is applicable to the manufacturing method of a top gate type field effect transistor not limited to this.

In the above-described third and fourth embodiments, examples of forming the first gate insulating film 14A and the second gate insulating film 14B constituting the gate insulating film 14 by the sputtering method, respectively, have been described. The present invention is not limited thereto, and at least one of the first and second gate insulating films 14A and 14B may be formed by a CVD method.

In addition, the gate insulating film 14 is not limited to the example comprised by the single | mono layer film of a silicon oxide film or a silicon nitride film, For example, it is also possible to comprise a gate insulating film by the laminated film of a silicon oxide film and a silicon nitride film.

10 description
11 gate electrode
14 gate insulating film
14A first gate insulating film
14B second gate insulating film
15 active layer
15F IGZO film
16 stopper layer
16A first insulating film
16B second insulating film
16F stopper layer forming film
17 (17S, 17D) source / drain electrodes
100, 101, 102 transistor element (field-effect transistor)
201 ~ 208, 301 ~ 303 Vacuum Processing Unit

Claims (9)

On the substrate, an active layer having an In—Ga—Zn—O based composition is formed by the sputtering method,
A stopper layer having a laminated structure of a silicon oxide film or a silicon nitride film and an insulating metal oxide film on the active layer and protecting the active layer from an etchant with respect to the active layer is subjected to a sputtering method without exposing the active layer to the atmosphere. Formed by
A metal film is formed to cover the active layer and the stopper layer,
Using the stopper layer as an etching stopper to weight-etch the metal film to form a source electrode and a drain electrode,
Etching the active layer using the stopper layer as a mask,
Method of manufacturing a field effect transistor. The method of claim 1,
The step of forming the stopper layer,
After the active layer is formed, the stopper layer is continuously formed in the film formation chamber of the active layer.
Method of manufacturing a field effect transistor. The method of claim 1,
The step of forming the stopper layer,
Forming a first insulating film comprising a silicon oxide film or a silicon nitride film on the active layer by a sputtering method;
A step of forming a second insulating film composed of a metal oxide film on the first insulating film by a sputtering method,
Method of manufacturing a field effect transistor. The method of claim 1,
The step of forming the stopper layer,
Forming a first insulating film composed of a metal oxide film on the active layer by a sputtering method,
Forming a second insulating film composed of a silicon oxide film or a silicon nitride film by a sputtering method on the first insulating film,
Method of manufacturing a field effect transistor. The method of claim 1,
The step of forming the stopper layer,
Continuously forming the silicon oxide film or the silicon nitride film and the metal oxide film in the same chamber,
Method of manufacturing a field effect transistor. The method of claim 5,
The step of forming the stopper layer,
After the active layer is formed, the stopper layer is continuously formed in the film formation chamber of the active layer.
Method of manufacturing a field effect transistor. The method of claim 1,
The substrate includes a gate electrode,
Before forming the active layer, further forming a gate insulating film covering the gate electrode,
Method of manufacturing a field effect transistor. The method of claim 7, wherein
The process of forming the gate insulating film,
The gate insulating film is formed by a sputtering method,
Method of manufacturing a field effect transistor. The method of claim 7, wherein
The process of forming the gate insulating film,
Forming a first gate insulating film composed of a metal oxide film on the gate electrode;
Forming a second gate insulating film composed of a silicon oxide film or a silicon nitride film on the first gate insulating film,
Method of manufacturing a field effect transistor.

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