KR101264701B1 - LCD and drive method thereof - Google Patents

Abstract

According to the present invention, the N-frame inversion driving method can adjust the level of the gate low voltage used to supply the scan pulse so that the data voltage of each pixel can be quickly discharged during the next frame driving among the adjacent frames without inversion. A liquid crystal display device comprising: a high level gate low voltage and a low level gate low voltage for determining a low level of a scan pulse; A timing controller controlling the supply of the high level gate low voltage and the low level gate low voltage and controlling inversion and driving timing of a frame; A switch for selectively switching the high level gate low voltage and the low level gate low voltage according to the control of the timing controller; And a gate sequentially supplying scan pulses having a low level determined by the high level gate low voltage or the low level gate low voltage, which are selectively input through the switch, under the control of the timing controller. It includes a drive unit.

LCD, Frame, Inversion, Gate Low Voltage

Description

Liquid crystal display and driving method thereof

1 is an equivalent circuit diagram of a pixel formed in a general liquid crystal display device.

2 is a block diagram of a conventional liquid crystal display device.

3 is an illustrative example of N-frame inversion.

4 is a signal characteristic diagram of a conventional liquid crystal display device.

5 is a configuration diagram of a liquid crystal display device according to an exemplary embodiment of the present invention.

6 is a signal characteristic diagram of a liquid crystal display of the present invention.

Description of the Related Art

100 and 200: liquid crystal display 110: liquid crystal display panel

120, 250: data driver 130, 240: gate driver

140: gamma reference voltage generator 150: backlight assembly

160: inverter 170: common voltage generator

180: gate driving voltage generation unit 190, 220: timing controller

210: gate low voltage generator 230: switch

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and in particular, in the N-frame inversion driving method, data of each pixel is driven during the next frame driving among adjacent frames without inversion by adjusting the level of the gate low voltage used for supplying the scan pulse. A liquid crystal display device capable of quickly discharging a voltage and a driving method thereof are provided.

A liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to a video signal, and an active matrix type liquid crystal display device in which a switching element is formed for each liquid crystal cell enables active control of the switching element. This is advantageous for video implementation. As the switching element used in the active matrix liquid crystal display device, a thin film transistor (hereinafter referred to as TFT) is mainly used as shown in FIG. 1.

Referring to FIG. 1, an active matrix type liquid crystal display converts digital input data into an analog data voltage based on a gamma reference voltage and supplies it to the data line DL and simultaneously supplies scan pulses to the gate line GL. The liquid crystal cell Clc is charged.

The gate electrode of the TFT is connected to the gate line GL, the source electrode is connected to the data line DL, and the drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc and one electrode of the storage capacitor Cst. Connected.

A common voltage Vcom is supplied to the common electrode of the liquid crystal cell Clc.

The storage capacitor Cst serves to charge the data voltage applied from the data line DL when the TFT is turned on to maintain the voltage of the liquid crystal cell Clc constant.

When a scan pulse is applied to the gate line GL, the TFT is turned on to form a channel between the source electrode and the drain electrode to apply a voltage on the data line DL to the pixel electrode of the liquid crystal cell Clc Supply. At this time, the liquid crystal molecules of the liquid crystal cell Clc modulate the incident light by changing the arrangement by the electric field between the pixel electrode and the common electrode.

A configuration of a conventional liquid crystal display device having pixels having such a structure will be described with reference to FIG. 2.

2 is a block diagram of a conventional liquid crystal display device.

Referring to FIG. 2, the liquid crystal display 100 according to the related art includes a thin film for driving the liquid crystal cell Clc at the intersections of the data lines DL1 to DLm and the gate lines GL1 to GLn. A liquid crystal display panel 110 including a TFT (TFT: Thin Film Transistor), a data driver 120 for supplying a data voltage Vdata to the data lines DL1 to DLm of the liquid crystal display panel 110, A gate driver 130 for supplying scan pulses to the gate lines GL1 to GLn of the liquid crystal display panel 110, and a gamma reference voltage generator for generating a gamma reference voltage and supplying the gamma reference voltage to the data driver 120. 140, a backlight assembly 150 for irradiating light to the liquid crystal display panel 110, an inverter 160 for applying an alternating voltage and current to the backlight assembly 150, and a common voltage Vcom. To supply the common electrode of the liquid crystal cell Clc of the liquid crystal display panel 110 to The voltage generator 170, the gate driving voltage generator 180 for generating the gate high voltage VGH and the gate low voltage VGL and supplying the gate driver 130 to the gate driver 130, the data driver 120, A timing controller 190 for controlling the gate driver 130 is provided.

In the liquid crystal display panel 110, liquid crystal is injected between two glass substrates. On the lower glass substrate of the liquid crystal display panel 110, the data lines DL1 to DLm and the gate lines GL1 to GLn are orthogonal. TFTs are formed at intersections of the data lines DL1 to DLm and the gate lines GL1 to GLn. The TFT supplies the data on the data lines DL1 to DLm to the liquid crystal cell Clc in response to the scan pulse. The gate electrodes of the TFTs are connected to the gate lines GL1 to GLn, and the source electrodes of the TFTs are connected to the data lines DL1 to DLm. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc and the storage capacitor Cst.

The TFT is turned on in response to the scan pulse supplied to the gate terminal via the gate lines GL1 to GLn. When the TFT is turned on, video data on the data lines DL1 to DLm is supplied to the pixel electrode of the liquid crystal cell Clc.

The data driver 120 supplies the data voltage Vdata to the data lines DL1 through DLm in response to the data driving control signal DDC supplied from the timing controller 190. Here, the data driver 120 samples and latches the digital video data RGB supplied from the timing controller 190, and then the liquid crystal display panel 110 based on the gamma reference voltage supplied from the gamma reference voltage generator 140. In the liquid crystal cell (Clc) of the () is converted into an analog data voltage (Vdata) that can represent the gray level is supplied to the data lines (DL1 to DLm).

The gate driver 130 sequentially generates scan pulses, that is, gate pulses, in response to the gate driving control signal GDC and the gate shift clock GSC supplied from the timing controller 190, thereby providing the gate lines GL1 to GLn. To feed. The gate driver 130 determines the high level voltage and the low level voltage of the scan pulse in accordance with the gate high voltage VGH and the gate low voltage VGL supplied from the gate drive voltage generator 180, respectively.

The gamma reference voltage generator 140 receives a high potential power supply voltage VDD to generate a positive gamma reference voltage and a negative gamma reference voltage and output the same to the data driver 120.

The backlight assembly 150 is disposed on the rear surface of the liquid crystal display panel 110 and emits light by an AC voltage and a current supplied from the inverter 160 to irradiate light to each pixel of the liquid crystal display panel 110.

The inverter 160 converts the square wave signal generated therein into a triangular wave signal and compares the triangular wave signal with a DC power supply voltage (VCC) supplied from the system to generate a burst dimming signal proportional to the comparison result. . When a burst dimming signal determined according to an internal square wave signal is generated, a driving IC (not shown) for controlling the generation of AC voltage and current in the inverter 160 is supplied to the backlight assembly 150 according to the burst dimming signal. Control the generation of alternating voltage and current.

The common voltage generator 170 receives the high potential power voltage VDD to generate the common voltage Vcom and supplies the common voltage Vcom to the common electrodes of the liquid crystal cells Clc of each pixel of the liquid crystal display panel 110.

The gate driving voltage generator 180 receives the high potential power voltage VDD to generate the gate high voltage VGH and the gate low voltage VGL to supply the gate driver 130 to the gate driver 130. Here, the gate driving voltage generation unit 180 generates a gate high voltage VGH that is greater than or equal to the threshold voltage of the TFTs provided in each pixel of the liquid crystal display panel 110, and the gate low voltage that is less than or equal to the threshold voltage of the TFT. VGL). The gate high voltage VGH and the gate low voltage VGL generated in this way are used to determine the high level voltage and the low level voltage of the scan pulse generated by the gate driver 130, respectively.

The timing controller 190 supplies the digital video data RGB supplied from the system to the data driver 120 and controls the data driving by using the horizontal / vertical synchronization signals H and V according to the clock signal CLK. The signal DDC and the gate driving control signal GDC are generated and supplied to the data driver 120 and the gate driver 130, respectively. The timing controller 190 generates a gate shift clock GSC and supplies it to the gate driver 130. The data driving control signal DDC includes a source shift clock SSC, a source start pulse SSP, a polarity control signal POL, a source output enable signal SOE, and a gate driving control signal GDC. ) Includes a gate start pulse (GSP) and a gate output enable (GOE).

Various inversion methods for driving a conventional liquid crystal display device having such a configuration and function have been developed. For example, an N-frame inversion method has been developed to improve interlace afterimages.

Referring to the N-frame inversion driving method, the frames ((N-3) F, (N-2) F, (N-1)) sequentially input to the conventional LCD as shown in FIG. Inversion is performed between neighboring frames among F, (N) F, (N + 1) F, and (N + 2) F, but any two neighboring frames ((N) F, (N-1) There is no inversion between F). That is, the N-frame inversion driving method inverts a plurality of frames which are sequentially input in order, but does not invert adjacently input frames at every specific time by dividing the plurality of input frames into a certain number of frame units. .

Signal characteristics of the conventional liquid crystal display device driven by the N-frame inversion method will be described with reference to FIG. 4 as follows.

As shown in FIG. 4B, the gate low voltage VGL, which determines the low level of the scan pulse, is kept constant in all frames input by the N-frame inversion scheme. In this case, when the gate low voltage VGL is kept constant, neighboring frames ((N) F, (N + 1) F, and (N + 2) F) that have been inverted as shown in FIG. ), The polarity of the data voltage (Vdata) is inverted based on the common voltage (Vcom), but the polarity of the data voltage (Vdata) between the adjacent frames ((N-1) F, (N) F) without inversion Remains the same.

Then, as shown in Fig. 4A, the data charging amount of the next frame (N) F among the adjacent frames (N-1) F and (N) F without inversion is the previous frame ((N−). Since it is larger than the data charging amount of 1) F), the next frame ((N) F) of the neighboring frames ((N-1) F, (N) F) without inversion as shown in Fig. 4C. The luminance level of? Is significantly higher than the luminance level of the previous frame (N-1) F.

As described above, the conventional liquid crystal display device driven by the N-frame inversion method has a large amount of change in luminance between neighboring frames ((N-1) F and (N) F) without inversion, thereby preventing flicker. Have

The present invention has been made to solve the above problems, an object of the present invention is to adjust the level of the gate low voltage used for the supply of the scan pulse in the N-frame inversion driving method by neighboring frames without inversion The present invention provides a liquid crystal display and a driving method thereof capable of quickly discharging the data voltage of each pixel during heavy frame driving.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device and a driving method thereof capable of reducing the amount of change in luminance by quickly discharging a later frame among neighboring frames without inversion in the N-frame inversion driving scheme.

An object of the present invention is to provide a liquid crystal display device and a driving method thereof capable of removing flicker by reducing the amount of change in luminance in the N-frame inversion driving method.

According to an aspect of the present invention, there is provided a liquid crystal display device comprising: a gate low voltage generator configured to generate a high level gate low voltage and a low level gate low voltage to determine a low level of a scan pulse; A timing controller controlling the supply of the high level gate low voltage and the low level gate low voltage and controlling inversion and driving timing of a frame; A switch for selectively switching the high level gate low voltage and the low level gate low voltage according to the control of the timing controller; And a gate sequentially supplying scan pulses having a low level determined by the high level gate low voltage or the low level gate low voltage, which are selectively input through the switch, under the control of the timing controller. It includes a drive unit.

The timing controller may be configured to control N-frame inversion of frames input in sequence.

The switch may switch the low level gate low voltage to the gate driver during the driving period of neighboring frames inverted in the N-frame inversion driving.

The switch may switch the high level gate low voltage to the gate driver during a driving period of a next frame among neighboring frames that are not in-versioned in the N-frame inversion driving.

The switch may switch the low level gate low voltage to the gate driver during a driving period of a previous frame among neighboring frames that are not in-versioned in the N-frame inversion driving.

The low level of the scan pulse determined by the high level gate low voltage is higher than the low level of the scan pulse determined by the gate low voltage of the low level.

A driving method of a liquid crystal display according to the present invention includes: generating a low level gate low voltage and a high level gate low voltage for determining a low level of a scan pulse; Supplying the low level gate low voltage during a driving period of inverted neighboring frames; And selectively supplying the high level gate low voltage and the low level gate low voltage during the driving period of the non-inverted neighboring frames. Here, the low-level gate low voltage is supplied during a driving period of a previous frame among the non-inversioned neighboring frames in N-frame inversion, and the non-inverted neighboring frames in the N-frame inversion. The high level gate low voltage is supplied during the driving period of the heavy frame.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5 is a configuration diagram of a liquid crystal display according to an exemplary embodiment of the present invention. However, the liquid crystal display device 200 of the present invention also has the same gamma reference voltage generator 140, backlight assembly 150, inverter 160, and common voltage as the liquid crystal display device 100 shown in FIG. 2. Although the generator 170 is provided, these components are not shown in FIG. 5 for convenience of description.

Referring to FIG. 5, in the liquid crystal display device 200 of the present invention, the data lines DL1 through DLm and the gate lines GL1 through GLn intersect with each other to drive the liquid crystal cell Clc at an intersection thereof. The liquid crystal display panel 110 includes a thin film transistor TFT.

The liquid crystal display 200 of the present invention includes a gate low voltage generator 210 for generating a high level gate low voltage VGL_H and a low level gate low voltage VGL_L for determining a low level of a scan pulse. The timing controller 220 controls the supply of the high level gate low voltage VGL_H and the low level gate low voltage VGL_L, and the timing of supplying the scan pulse and the data voltage Vdata. A switch 230 for selectively switching the high level gate low voltage VGL_H and the low level gate low voltage VGL_L output from the gate low voltage generator 210 according to the control, and for the control of the timing controller 220. Accordingly, scan pulses having a low level determined by the high level gate low voltage VGL_H or the low level gate low voltage VGL_L which are alternatively inputted through the switch 230 are applied to the gate lines GL1 to GLn. By a frame that is input in an order according to the control gate of the class driver 240, a timing controller 220 for N- frame inversion and a data driver 250 to implement a liquid crystal display panel 110.

The gate low voltage generator 210 receives the high potential power voltage VDD to generate a high level gate low voltage VGL_H and a low level gate low voltage VGL_L that determine a low level of the scan pulse, and thus switch 230. )

The timing controller 220 outputs an inversion control signal NIC for instructing N-frame inversion of frames sequentially input from the system to the data driver 250. That is, the data driver 250 N-frames the frames input through the timing controller 220 in response to the inversion control signal NIC to implement the N-frame in the liquid crystal display panel 110. The data driver 250 supplies the data voltage Vdata to the data lines DL1 to DLm of the liquid crystal display panel 110.

More specifically, as shown in FIG. 3, the data driver 250 includes frames ((N-3) F, (N-2) F, (N-1) F, (N) F, The neighboring frames of (N + 1) F and (N + 2) F are inverted, but the two neighboring frames ((N) F and (N-1) F) are not inverted.

When the N-frame is inverted in this manner, the common voltage (N) between the inverted neighboring frames ((N) F, (N + 1) F, and (N + 2) F) as shown in FIG. The polarity of the data voltage Vdata is inverted with respect to Vcom, but the polarity of the data voltage Vdata remains the same between the adjacent frames (N-1) F and (N) F without inversion.

When inversion is performed in N-frame inversion driving, as shown in FIG. 6B, the timing controller 220 performs the inversion of neighboring frames ((N + 1) F and (N + 2) F). The switching direction of the switch 230 is controlled so that the low level gate low voltage VGL_L is supplied to the gate driver 240 during the driving period. Here, the timing controller 220 supplies the low level polarity channel control signal POLCH to the switch 230 so that the switch 230 is switched in the supply direction of the low level gate low voltage VGL_L.

When frame inversion is not performed in N-frame inversion driving, as shown in FIG. 6 (B), the timing controller 220 performs neighboring frames ((N-1) F and (N) without inversion. The switching direction of the switch 230 is controlled so that the high-level gate low voltage VGL_H is supplied to the gate driver 240 during the driving period of the next frame (N) F during F, and the previous frame ((N-1) The switching direction of the switch 230 is controlled so that the low level gate low voltage VGL_L is supplied to the gate driver 240 during the driving period of F). Here, the timing controller 220 supplies the low level polarity channel control signal POLCH to the switch 230 in the previous frame (N-1) F so that the switch 230 receives the low level gate low voltage VGL_L. Then, the switch 230 is supplied with the high level polarity channel control signal POLCH to the switch 230 in the next frame (N) F, so that the switch 230 receives the high level gate low voltage VGL_H. To be switched in the supply direction.

In addition, the timing controller 220 supplies the digital video data RGB supplied from the system to the data driver 250, and also uses the horizontal / vertical synchronization signals H and V according to the clock signal CLK. The driving control signal DDC and the gate driving control signal GDC are generated and supplied to the data driver 250 and the gate driver 240, respectively. The timing controller 220 generates a gate shift clock GSC and supplies it to the gate driver 240. The data driving control signal DDC includes a source shift clock SSC, a source start pulse SSP, a polarity control signal POL, a source output enable signal SOE, and a gate driving control signal GDC. ) Includes a gate start pulse (GSP) and a gate output enable (GOE).

The switch 230 has switching terminals connected to the high level gate low voltage output terminal and the low level gate low voltage output terminal of the gate low voltage generator 210 and the switching terminal connected to the gate driver 240, respectively. When the low level polarity channel control signal POLCH is supplied from the timing controller 220, the switch 230 is switched in the direction of the low level gate low voltage output terminal of the gate low voltage generator 210 to provide a low level gate low voltage ( VGL_L) is switched to the gate driver 240. On the contrary, when the high level polarity channel control signal POLCH is supplied from the timing controller 220, the switch 230 is switched toward the high level gate low voltage output terminal of the gate low voltage generator 210 to provide a high level gate. The low voltage VGL_H is switched to the gate driver 240.

The gate driver 240 sequentially generates scan pulses while the frame is driven on the liquid crystal display panel 110 in response to the gate driving control signal GDC and the gate shift clock GSC from the timing controller 220. Supply to lines GL1 to GLn. Here, the gate driver 240 adjusts the low level of the scan pulse in proportion to the level of the high level gate low voltage VGL_H or the low level gate low voltage VGL_L supplied from the gate low voltage generator 210. That is, the low level of the scan pulse determined by the high level gate low voltage VGL_H becomes higher than the low level of the scan pulse determined by the low level gate low voltage VGL_L.

More specifically, when frame inversion is not performed in N-frame inversion driving, neighboring frames ((N-1) F, (N) F) without inversion as shown in FIG. 6 (B). The high level gate low voltage VGL_H is supplied to the gate driver 240 during the driving period of the heavy frame (N) F and the low level gate low voltage during the driving period of the previous frame (N-1) F. Since VGL_L is supplied to the gate driver 240, the low level of the scan pulse used to drive the previous frame (N-1) F is set to the scan pulse used to drive the next frame (N) F. Lower than the low level. Accordingly, as shown in FIG. 6 (A), the discharging speed of each pixel is faster when driving the next frame (N) F than in the conventional case shown in FIG. 4 (A). As shown in Fig. 2A, the luminance levels of the previous frame (N-1) F and the subsequent frame (N) F become equal. 4 (C) and 6 (C), the luminance level of the frame (N) F is drastically reduced after being driven by the liquid crystal display 200 of the present invention.

As described above, the present invention adjusts the level of the gate-low voltage used for supplying the scan pulse in the N-frame inversion driving method, thereby adjusting the data voltage of each pixel when driving the next frame among neighboring frames without inversion. By quickly discharging, the amount of change in luminance can be reduced, thereby eliminating flicker.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

Claims (8)

A gate low voltage generator configured to generate a high level gate low voltage and a low level gate low voltage to determine a low level of the scan pulse; A timing controller controlling the supply of the high level gate low voltage and the low level gate low voltage and controlling inversion and driving timing of a frame; A switch for selectively switching the high level gate low voltage and the low level gate low voltage according to the control of the timing controller; And Under the control of the timing controller, a gate driver for sequentially supplying a scan pulse having a low level determined by the high level gate low voltage or the low level gate low voltage that is selectively input through the switch to a liquid crystal display panel. It includes; The timing controller controls N-frame inversion (N is a natural number greater than or equal to 2) of frames inputted in order; And the switch switches the high level gate low voltage to the gate driver during a driving period of a next frame among neighboring frames that are not inversioned in the N-frame inversion driving. delete The method of claim 1, And the switch switches the low level gate low voltage to the gate driver during a driving period of neighboring frames inverted in the N-frame inversion driving. delete The method of claim 1, And the switch switches the low level gate low voltage to the gate driver during a driving period of a previous frame among neighboring frames that are not in-versioned in the N-frame inversion driving. The method according to any one of claims 1, 3, and 5, And the low level of the scan pulse determined by the high level gate low voltage is higher than the low level of the scan pulse determined by the gate low voltage of the low level. Generating a low level gate low voltage and a high level gate low voltage for determining a low level of the scan pulse; Supplying the low level gate low voltage during a driving period of inverted neighboring frames; And Selectively supplying the high level gate low voltage and the low level gate low voltage during the driving period of the non-inverted neighboring frames Method of driving a liquid crystal display comprising a. The method of claim 7, wherein In the selective feeding step, In the N-frame inversion, the low level gate low voltage is supplied during a driving period of a previous frame among the non-inverted neighboring frames, And supplying the high level gate low voltage during the driving period of a subsequent frame among the non-inverted neighboring frames in the N-frame inversion.

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