KR101244593B1 - Flat panel display device and manufacturing method thereof - Google Patents

Abstract

According to an aspect of the present invention, there is provided a flat panel display including: a substrate having a pixel area, a gate pad area, and a data pad area; A plurality of gate lines and a plurality of data lines provided in the pixel area; A plurality of gate pad lines provided in the gate pad area and connected to the gate lines; A plurality of data pad lines provided in the data pad area and connected to the data lines; And a plurality of floating lines formed of the same material as the gate line and connected to the data pad line in the data pad area.

In addition, a method of manufacturing a flat panel display device according to the present invention includes the steps of forming a first base layer on a substrate; Applying an etching resist (ER) layer on the first base layer; Providing a stamp having a plurality of intaglio patterns for patterning the ER layer; Contacting the stamp with the ER layer to form an ER pattern; And etching the first base layer to form a gate line in a pixel region, a gate pad line in a gate pad region, and a floating line in a data pad region by the ER pattern.

Therefore, the present invention can solve problems such as electrical interference generated between lines due to the overlapping metal formed due to the stacked structure of the flat panel display device.

Description

Flat panel display device and manufacturing method

1 is a plan view showing a conventional liquid crystal display device.

2 is a cross-sectional view taken along line II ′ II-II ′ and III-III ′ of FIG. 1.

3A-3C illustrate a soft lithography process for forming conventional gate lines and gate pad lines.

4 is a plan view showing a liquid crystal display device according to the present invention;

5 is an enlarged view of area A of FIG. 4;

6A is a cross-sectional view taken along line VI-VI 'of FIG. 5;

FIG. 6B illustrates another embodiment of the data padline of FIG. 6A. FIG.

7A illustrates another embodiment of a data padline in accordance with the present invention.

FIG. 7B is a cross sectional view along VII-VII ′ of FIG. 7A; FIG.

8A to 8J are process drawings for forming a liquid crystal display device according to the present invention.

Description of the Related Art

   1 liquid crystal display 3 pixel area

   5: gate pad area 8: data pad area

  10: substrate 20: gate pad line

 20a: Floating line 23: Gate line

  30: gate insulating film 40: data pad line

  43: data line 50: passivation film

  60 conductive film 65 pixel electrode

 110: ER pattern 120: photosensitive pattern

 200: stamp

The present invention relates to a flat panel display and a manufacturing method thereof.

As semiconductor products become smaller and more integrated, there is a growing interest in patterning techniques for forming patterns to improve new functions. In the past, lithography for patterning has been developed as a core technology of semiconductor manufacturing. Currently, there are methods that can realize a pattern structure of nano size smaller than micron size in an economical and simple process. Is being presented.

However, the current patterning technology for forming a pattern having a high degree of integration has a high technical cost for forming a pattern in an apparatus or a process. In addition, the polymer material used as a conventional photosensitive material has reached the physical limit, there is a problem that is difficult to apply in the patterning speed and resolution, curved surface.

In particular, in order to provide an active display device in a flat panel display device, a substrate on which a thin film transistor is provided includes a semiconductor process and requires a plurality of mask processes, thereby increasing the complexity of the manufacturing process and increasing the manufacturing cost of the flat panel display device. It is a major cause.

This is because one mask process includes many processes such as a thin film deposition process, a cleaning process, a photolithography process, an etching process, a photoresist stripping process, and an inspection process.

Thus, a new concept of patterning technology, Soft-Lithography, is proposed.

Soft lithography is a technique of repeatedly manufacturing a pattern or a structure by embedding an organic material in a flexible polymer mold without using light or large energy particles.

In such soft lithography, ink is applied to a stamp to transfer a pattern. Here, the material of the stamp is mainly used a polymer of polydimethylsiloxane (PDMS).

In the case of a general photolithography process, a photo process and a complicated etching process are required several times. However, the use of the stamp makes the process simple and easy to apply, such as a large area and a curved surface, and can be easily patterned by selective thin film coating. have.

FIG. 1 is a plan view illustrating a conventional liquid crystal display, and FIG. 2 is a cross-sectional view taken along line II ′ and III-III ′ of FIG. 1. FIG. 2 shows only one line because the line is repeated for convenience of drawing.

As illustrated in FIG. 1, the liquid crystal display 501 includes a pixel region 503 for displaying an image and pad regions 505 and 508 including a plurality of driving circuits on the side of the pixel region 503. This is provided.

The pixel area 503 is an area for displaying a screen, and a plurality of gate lines 523 and a plurality of data lines 543 are arranged orthogonal to each other at a predetermined interval. A thin film transistor TR is formed at a point where the two lines 523 and 543 cross each other.

In the thin film transistor TR, a semiconductor layer 570 is formed on the gate electrode 523a integrated with the gate line 523, and source / drain electrodes 543a overlapping a portion of the semiconductor layer 570. 543b) is formed.

The source electrode 543a is integral with the data line 543, and the drain electrode 543b is spaced apart from each other by the source electrode 543a and the semiconductor layer 570 therebetween.

The drain electrode 543b is connected to the pixel electrode 565 to transfer the pixel voltage input to the data line 543 to the pixel electrode 565.

The pad regions 505 and 508 include a gate pad region 505 for connecting a signal to the gate line 523 and a data pad region 508 for connecting a data signal to the data line 543.

The pad regions 505 and 508 are provided with a plurality of lines 520 and 540 to which driving circuits capable of driving the pixel region 503 are connected. The line provided in the gate pad region 505 is defined as the gate pad line 520 and the line provided in the data pad region 508 is defined as the data pad line 540.

The gate pad line 520 of the gate pad region 505 is connected to the gate line 523 of the pixel region 503 to transmit a gate signal to the gate line 523.

The data pad line 540 of the data pad region 508 is connected to the data line 543 of the pixel region 503 to transfer the pixel voltage to the data line 543.

Here, a dummy pattern 520a may be formed in a portion of the data pad region 508 by partially depositing the gate metal deposited when the gate line 523 and the gate pad line 520 are formed. The reason why the gate metal remains in the data pad region 508 will be described in detail later with reference to FIGS. 3A to 3C.

As such, since the gate metal (ie, the dummy pattern 520a) remaining in the data pad region 508 is formed under the data pad line 540, two metals (dummy pattern 520a and data pad) are formed. There is a problem that parasitic capacitance occurs between lines 540. Accordingly, problems such as signal delay may occur due to electrical interference between the two metals, which may cause deterioration of the display device.

As shown in the cross-sectional view of the liquid crystal display of FIG. 2, the liquid crystal display 501 is provided with pad regions 505 and 508 including a plurality of pad lines 520 and 540 and a thin film transistor TR to display an image. The pixel area 503 to display is provided.

The pixel region 503 is provided with a thin film transistor TR that performs a switching role in a region where the gate line 523, the data line 543, and the two lines cross each other.

As illustrated in II-II ′ of FIG. 2, a thin film transistor TR is provided in the pixel region 503, and the thin film transistor TR includes a gate line 523 and a gate line 523 having a gate electrode formed therein. ) Is insulated from the gate insulating film 530, the semiconductor layer 570 forming a channel in the gate signal applied to the gate line 523, and a pixel voltage is transferred on the semiconductor layer 570 and spaced apart from each other. A source electrode 543a and a drain electrode 543b are provided. The source electrode 543a is integrally formed with the data line 543.

In order to protect the thin film transistor TR, a passivation film 550 having passivation holes is formed on the entire surface of the substrate 510, and a pixel electrode 565 is provided on the passivation film 550.

The pad regions 505 and 508 include a gate pad region 505 for transmitting a gate signal to the gate line 523 and a data pad region 508 for transmitting a pixel signal to the data line 543. have.

As illustrated in II ′ of FIG. 2, the gate pad region 505 includes a plurality of gate pad lines 520 connected to the gate line 523. The gate pad line 520 is protected by the gate insulating film 530 and the passivation film 550. In order to transfer the gate signal to the gate line 523 later, a contact pad may be further provided by drilling holes in predetermined regions of the two insulating layers 530 and 550.

As illustrated in III-III ′ of FIG. 2, the data pad region 508 is provided with a plurality of data pad lines 540 for transferring pixel signals to the data lines 543.

The semiconductor material layer 570a remaining when the semiconductor layer 570 is formed may be formed under the data pad line 540. When the semiconductor material film 570a is subjected to a four mask process, the semiconductor layer 570 and the data line 543 are formed at the same time, so that the semiconductor material film 570a is disposed below the data line 543 or the data pad line 540. ) May remain. On the other hand, the semiconductor material layer 570a may not remain in the five mask process. In the figure presented, a four mask process is cited.

In addition, a dummy pattern 520a may be formed under the data pad line 540. When forming the gate line 523 and the gate pad line 520, the dummy pattern 520a may be formed under the data pad line 540 because the gate metal is not etched.

The data pad line 540 is connected to the data line 543 to transfer the pixel voltage to the pixel electrode 565. The dummy patterns 520a overlap each other under the data pad line 540. Since the parasitic capacitance is generated between the two metals 540 and 520a, it may cause problems such as signal delay.

Accordingly, problems such as signal delay may occur due to electrical interference between the two metals 540 and 520a, which may cause display quality degradation of the liquid crystal display.

3A through 3C are diagrams of a soft lithography process for forming a gate line and a gate pad line of the related art.

In the soft lithography process, an organic material is brought into contact with a stamp provided with a yin-yang pattern, and a pattern is formed by moving the organic material to the intaglio pattern by using the repulsive force of the stamp and the organic material and capillary phenomenon generated in the yin pattern. Patterning method.

As shown in FIG. 3A, the gate metal layer 520 is formed on the substrate 510 to form the gate line 523 of the pixel region 503 and the gate pad line 520 of the gate pad region 505. ') Is deposited and an etching resist (ER) is applied on the gate metal layer 520' to form an ER layer (610a).

In addition, a stamp 700 having a negative / embossed pattern is provided, and the stamp 700 is brought into contact with the viscous ER layer 610a. Here, the etching resist moves the material between the stamp 700 and the ER layer 610a due to the repulsive force between organic materials, and a capillary phenomenon occurs in the intaglio pattern of the stamp 700, so that the etching resist is applied to the intaglio pattern. Will be filled.

That is, as the material moves to the intaglio pattern, the pattern of the stamp 700 is transferred onto the ER layer 610a. Thus, an ER pattern (610 of FIG. 3B) for forming the gate line 523 and the gate pad line 520 may be formed in the stamp 700.

The gate line 523 and the gate pad line 520 are not formed in the data pad region 508. Therefore, the stamp 700 does not have the intaglio pattern corresponding to the gate line 523 and the gate pad line 520. That is, the intaglio pattern formed of the gate metal material is not present in the data pad region 540.

Accordingly, the data pad region 508 does not have a space (engraved pattern) for the material to move the etching resist. Thus, the etching resist in the data pad region 508 remains as it is.

As shown in FIG. 3B, when the stamp 700 is in contact with the etching resist (ER layer 610a) and a predetermined time elapses, the etching resist is moved to fill the intaglio pattern.

When the stamp 700 is detached from the substrate 510, the etching resist material-moved into the intaglio pattern forms the ER pattern 610 according to the shape of the intaglio pattern.

The ER pattern 610 for forming the gate line 523 and the ER pattern 610 for forming the gate pad line 520 in the gate pad region 505 are respectively formed in the pixel region 503. do. As the etching resist moves, the gate metal layer 520 ′ is exposed from the ER layer 610a around the ER pattern 610.

On the other hand, the data pad region 508 does not have a pattern formed of a gate metal, or less metal patterns than the number of gate lines 523 and gate pad lines 520 are formed, so that the number of ER patterns 610 (ie , The density of the ER pattern 610) is less distributed. That is, since the intaglio pattern density (the number of the intaglio patterns) of the stamp 700 in which the etch resist may move may be relatively small, the data pad region 508 may leave the etch resist not moved. For this reason, the gate metal layer 520 'may not be exposed.

As shown in FIG. 3C, an etching step is performed to etch the gate metal layer 520 ′ by providing an etchant on the substrate 510 on which the ER pattern 610 is formed.

The etchant etches the exposed gate metal layer 520 '. Here, the gate metal layer 520 ′ in the region where the ER pattern 610 is formed is protected from the etchant to form the gate line 523 and the gate pad line 520.

Here, as shown in FIG. 3B, the etching resist, which is not moved, may remain in the data pad region 508. Therefore, the provided etchant cannot etch the gate metal layer 520 ′ of the data pad region 508 in which the etching resist remains.

When the etch pattern is removed and the ER pattern 610 is stripped, the gate metal layer 520 ′ under the ER pattern 610 may remain to form the gate line 523 and the gate pad line 520. do.

In addition, in the data pad region 508, if the etching resist is not moved, the gate metal layer 520 'may remain to form a dummy pattern 520a.

Referring to FIG. 1, a gate insulating film 530, a semiconductor layer 570, and a data line 540 formed later are stacked to form a thin film transistor TR. In this case, a data pad line 540 connected to the data line 543 and formed in the data pad region 508 is formed on the gate insulating layer 530.

However, when the gate line 523 and the gate pad line 520 are formed under the gate insulating layer 530, a dummy pattern 520a may be formed in the data pad region 508.

As such, the dummy pattern 520a may be formed under the data pad line 540 to overlap the data pad line 540. Thus, electrical interference such as parasitic capacitance may occur between the two metals 540 and 520a.

Accordingly, problems such as signal delay may occur due to electrical interference generated between the two metals 520a and 540, and the signal delay may cause display quality degradation of the display device.

According to the present invention, in the process of forming a pattern using a stamp, problems such as electrical interference occurring between overlapping metals in a display device having a laminated structure by connecting a dummy pattern, which may be formed during the pattern formation process, with a pad line are provided. An object of the present invention is to provide a flat panel display device and a method of manufacturing the same.

According to an aspect of the present invention, a flat panel display device includes: a substrate having a pixel area, a gate pad area, and a data pad area; A plurality of gate lines and a plurality of data lines provided in the pixel area; A plurality of gate pad lines provided in the gate pad area and connected to the gate lines; A plurality of data pad lines provided in the data pad area and connected to the data lines; And a plurality of floating lines formed of the same material as the gate line and connected to the data pad line in the data pad area.

The data line and the data pad line may be formed of molybdenum.

The data pad line and the floating line may be formed to overlap a predetermined area.

A method of manufacturing a flat panel display device according to the present invention includes the steps of forming a first base layer on a substrate; Applying an etching resist (ER) layer on the first base layer; Providing a stamp having a plurality of intaglio patterns for patterning the ER layer; Contacting the stamp with the ER layer to form an ER pattern; And etching the first base layer to form a gate line in a pixel region, a gate pad line in a gate pad region, and a floating line in a data pad region by the ER pattern.

And sequentially forming a gate insulating film, a semiconductor material film, a second base layer, and a photosensitive film on the substrate; Patterning the photosensitive film to form a photosensitive pattern and etching the substrate; Stripping the photosensitive pattern to form a semiconductor layer forming data lines and channels in the pixel region and a data pad line transferring a data signal to the data pad region; Forming a passivation film on the entire surface of the substrate; Forming a plurality of holes in the data pad region of the passivation layer to connect the floating lines and the data pad lines; And forming a conductive layer connecting the data pad line and the floating line on the hole.

Hereinafter, a flat panel display device according to the present invention will be described in detail with reference to the following embodiments through a liquid crystal display device, and those skilled in the art can implement many other embodiments using the teachings of the present invention. It is intended for illustrative purposes and not limited to the following embodiments.

The present invention forms a thin film transistor of an array substrate and a liquid crystal display device having a stacked structure by soft lithography (Soft-Lithography), a new concept of patterning technology different from the previous photoelectron method. Soft lithography is a technique of repeatedly manufacturing a pattern or a structure by embedding an organic material in a flexible polymer mold without using particles of light or large energy.

In such soft lithography, ink is applied to a stamp to transfer a pattern. The material of the stamp is mainly used a polymer of polydimethylsiloxane (PDMS).

Using the stamp has the advantage that the process is simple, easy to apply to a large area and can be patterned simply because selective thin film coating is possible.

In the present invention, a liquid crystal display device which is one of the flat panel display devices will be described as an embodiment.

4 is a plan view illustrating a liquid crystal display according to the present invention, and FIG. 5 is an enlarged view of region A of FIG. 4.

As shown in FIG. 4, the liquid crystal display device 1 includes a plurality of switching elements TR and a plurality of switching elements TR formed by crossing a plurality of gate lines 23 and a plurality of data lines 43. A pixel region 3 for displaying an image by providing a pixel electrode 65 to be connected is provided, and pad regions 5 and 8 for driving the pixel region 3 are provided.

The pad regions 5 and 8 are formed with a plurality of pad lines 20 and 40 connecting the driving circuit, the gate line 23, the data line 43, and the like.

In the pixel region 3, a plurality of switching elements TR serving as a switching role are provided. The switching element TR is disposed on the gate electrode 23a protruding from the gate line 23, the semiconductor layer 70 formed on the gate electrode 23a to form a channel, and a portion of the semiconductor layer 70. Overlapping source / drain electrodes 43a and 43b are provided. The drain electrode 43b is connected to the pixel electrode 65 through the pass hole 57. A portion of the source electrode 43a is formed to protrude from the data line 43, and the drain electrode 43b is formed to be spaced apart from the source electrode 43a by a predetermined distance with the semiconductor layer 70 therebetween. It is.

The pad regions 5 and 8 include a gate pad region 5 having a gate pad line 20 and a data pad region 8 having a data pad line 40.

A gate pad line 20 is provided in the gate pad region 5 to be connected to the gate line 23, and the gate pad line 20 applies a gate voltage applied from a driving circuit to the gate line 23. Will be delivered.

A data pad line 40 is provided in the data pad region 8 to be connected to the data line 43, and the data pad line 40 applies a pixel voltage applied from a driving circuit to the data line 43. Will be delivered.

In addition, the data pad region 8 has a floating line 20a formed of a gate metal material. The floating line 20a is connected to the data pad line 40. The floating line 20a is represented by a thick line to distinguish it from the data pad line 40. Formation of the floating line 20a will be described later in detail in the manufacturing process of the liquid crystal display of FIGS. 8A to 8J.

As shown in an enlarged view of region A of FIG. 4 in FIG. 5, a plurality of data pad lines 40 are formed in the data pad region 8, and a floating line 20a is formed in the data pad lines 40. ) Is connected. Here, only a few lines are displayed for convenience of drawing.

The data pad line 40 is connected to the data line 43, and the data pad line 40 is also connected to the floating line 20a. The floating line 20a may be simultaneously formed when the gate line 23 of the pixel region 3 and the gate pad line 20 of the gate pad region 5 are formed, which will be described later. This will be explained in detail.

In addition, a first contact hole 25 is formed in the floating line 20a to connect the data pad line 40 and the floating line 20a, and a second contact hole 45 is formed on the data pad line 40. Provide a large number. Here, the plurality of first and second contact holes 25 and 45 may use contact holes of different shapes or use contact holes of the same shape as shown in the drawing.

The second contact hole 45 adjusts the number of holes to adjust resistance and current difference that may occur due to length deviation. Here, the data pad line 40 has a shape concentrated in one region in order to be connected to a driving circuit. Thus, the data pad line 40 may have a different length.

The data pad line 40 formed as described above may have an R / C delay due to the formed length deviation, and the resistance and current may be differently transmitted to the data line 43 due to the R / C delay. Thus, the number of contact holes 25 and 45 is adjusted to provide a predetermined resistance and current according to the length deviation of the data pad line 40 to the data line (see reference numeral 43 in FIG. 4).

The material connecting the data pad line 40 and the floating line 20a may use a conductive film 60 such as ITO. The conductive layer 60 including the ITO may be formed of the same material as the pixel electrode 65 of the pixel region 3. Therefore, in the process of forming the switching element TR of the pixel region 3, the two electrodes 20a and 40 may be connected without an additional process.

Since ITO and the like used as the conductive film 60 are oxides, they are resistant to oxygen even when exposed to air, so that the lines 20, 40 and 20a provided under the ITO film can be protected from air (humidity). do. That is, there is also an advantage that can improve the reliability of the lines 20, 20a, 40.

FIG. 6A is a cross-sectional view taken along line VI-VI 'of FIG. 5, and FIG. 6B is a view showing another embodiment of the data pad line of FIG. 6A. Herein, the components of the pixel region 3 refer to FIG. 4, and the data pad line 40 and the floating line 20a are described in comparison with the process of forming the switching element TR of the pixel region 3. do.

As shown in FIG. 6A, the floating line 20a and the data pad line 40 are formed on the substrate 10 at predetermined intervals in the data pad region 8 of the liquid crystal display.

The floating line 20a may be formed simultaneously with the gate line 23 of the pixel region 3 and the gate pad line 20 of the gate pad region 5.

A gate insulating film 30 covering the entire surface of the substrate 10 is formed on the floating line 20a, and a data pad line 40 is spaced apart from the floating line 20a by a predetermined distance on the gate insulating film 30. Is formed.

Referring to FIG. 4, a gate electrode having a semiconductor layer 70 integral with the gate line 23 may be formed in the pixel region 3 to form a channel by coating a semiconductor material to form a switching device TR. It forms in the area | region corresponding to 23a.

The source / drain electrodes 43a and 43b overlap each other region on the semiconductor layer 70. The source electrode 43a and the drain electrode 43b are spaced apart by a predetermined interval with the semiconductor layer 70 therebetween, and the source electrode 43a is integrally formed with the data line 43.

When the data line 43 is formed, the data pad line 40 is formed in the data pad region 8.

The passivation layer 50 is formed on the entire surface of the substrate 10 on which the data line 43 and the data pad line 40 are provided. Here, the passivation film 50 is reduced in the pixel region 3 to form a passivation hole 57, and a transparent conductive material is deposited on the passivation film 50 to form the pixel electrode 65. .

In this case, when the pass hole 57 is formed in the pixel area 3, the data pad area 8 includes a second contact hole 45 in a predetermined area of the data pad line 40, and the floating line. A first contact hole 25 formed in 20a is formed. Here, the passivation film 50 is dry etched to form the plurality of contact holes 25 and 45. The dry etching is not easy to etch the metal film. Thus, when the metal is exposed under the etched region, dry etching does not proceed anymore.

When the pixel electrode 65 of the pixel region 3 is formed, the transparent conductive material deposited on the passivation film 50 in which the first and second contact holes 25 and 45 are formed in the data pad region 8. The conductive layer 60 may be formed by patterning the conductive layer 60.

The conductive layer 60 connects the floating line 20a and the data pad line 40 through first and second contact holes 25 and 45. In addition, the conductive film 60 may be formed of oxides such as ITO and IZO to protect a plurality of lines formed under the conductive film 60 from air (humidity).

As shown in another embodiment of FIG. 6B, the data line 43 and the data pad line 40 may be formed of molybdenum. The molybdenum metal has a property that can be etched by dry etching. Therefore, when the data line 43 and the data pad line 40 are formed, the mask process can be reduced in steps. Here, the data pad line 40a formed of a metal which can be etched by dry etching, such as molybdenum, is denoted as “40a”.

In the dry etching process, an organic film, an inorganic film, a semiconductor material, or the like may be etched. That is, in the present invention, the gate insulating film 30 may be formed of an inorganic film, the passivation film 50 may be formed of an organic film, the semiconductor material film 70a may be formed of a semiconductor layer 70, and molybdenum may be formed. The formed data line 43 and the data pad line 40a may be etched. On the other hand, in the dry etching process, the gate line 23 and the gate pad line 20 formed of metal are not easily etched.

In the pixel region 3, when the semiconductor layer 70 and the data line 43 are simultaneously formed, patterning is performed through the dry etching.

In the present invention, when forming the pass hole 57 of the pixel region 3, the first and second contact holes 25 and 45 are formed in the data pad region 8.

Thus, when the data pad line 40a is etched to form the first and second contact holes 25 and 45 in the data pad region 8 formed of molybdenum, the passivation layer 50 is etched. The data pad line 40a, the semiconductor material layer 70a, and the gate insulating layer 30 may be etched.

Accordingly, when the first contact hole 25 is formed in the floating line 20a, that is, the dry etching process is performed until the gate pad line 20 is exposed, the second contact hole 45 is formed of the substrate 10. May be exposed up to.

In the data pad region 8 in which the data pad line 40a is made of molybdenum, the first and second contact holes 25 and 45 may be formed because the second contact hole 45 may be formed to the surface of the substrate 10. The conductive oxide formed on the passivation layer 50 makes side contact with the data pad line 40a. That is, the conductive layer 60 formed by patterning the conductive oxide may be connected to the data pad line 40a by side contacts.

Accordingly, the floating line 20a and the data pad line 40 are connected to the conductive layer 60 formed by depositing and patterning a conductive oxide material on the substrate 10 on which the first and second contact holes 25 and 45 are formed. do.

FIG. 7A illustrates another embodiment of a data pad line according to the present invention, and FIG. 7B is a cross-sectional view taken along line VII-VII ′ of FIG. 7A.

As shown in FIG. 7A, the data pad region 8 is provided with a data pad line 40a formed of molybdenum and a floating line 20a formed of a gate metal material. The data pad line 40a is provided to overlap a portion of the floating line 20a.

A plurality of contact holes 47 are provided in an area where the data pad line 40a and the floating line 20a overlap. The contact hole 47 may be provided with a plurality of contact holes 27 to improve the reliability of the contact between the floating line 20a and the data pad line 40. Here, the data pad region 8 in which two contact holes 27 are formed is shown for convenience of illustration. In addition, by providing a plurality of contact holes 27 it is possible to minimize the potential difference between the two metal (20a, 40a).

The conductive line 60 is connected on the two lines 20a and 40a to connect the floating line 20a and the data pad line 40a to minimize problems such as corrosion of the lines 20a and 40a from outside air. ). The conductive layer 60 is preferably an oxide such as ITO, IZO.

As shown in the cross-sectional view of the data pad region 8 in FIG. 7B, the data pad region 8 formed on the substrate 10 forms a floating line 20a formed of a gate metal material. A gate insulating film 30 is formed on 20a.

A data pad line 40a overlapping the floating line 20a and a partial region is formed on the gate insulating layer 30. Here, the semiconductor material layer 70a may remain under the data pad line 40a as in the four mask process. The passivation film 50 is formed on the data pad line 40a. Here, a plurality of contact holes 27 are formed in an area where the data pad line 40a and the floating line 20a overlap.

Since the data pad line 40a is formed of molybdenum, the data pad line 40a may be etched even by dry etching. The dry etching may be a semiconductor material, organic, inorganic material etching.

Therefore, when the contact hole 47 is formed by dry etching in an area where the floating line 20a and the data pad line 40a overlap, the data pad line 40a, the passivation film 50, and the semiconductor material film are formed. 70a and the gate insulating film 30 are etched to form contact holes 47 formed therethrough.

The conductive layer 60 is formed on the contact hole 47 to connect the floating line 20a and the data pad line 40a. The data pad line 40a and the floating line 20a are in side contact with the conductive layer 60 due to the contact holes 47 formed therethrough.

As described above, when forming the pass hole (reference 57 of FIG. 8J) formed in the pixel region 3, the contact hole 47 can be formed, so that the contact hole 47 can be formed without adding a mask process. The floating line 20a and the data pad line 40a may be connected through the contact hole 47.

8A to 8J are process drawings for forming a liquid crystal display device according to the present invention.

As shown in FIG. 8A, a gate metal material is deposited on the substrate 10 to form a first base layer 20 ′, and an etching resist is applied on the first base layer 20 ′ to form an ER layer 110 a. To form. In this case, the ER layer 110a may be formed of a material that is not etched in an etchant such as resin or polymer.

As shown in FIG. 8B, a stamp 200 having a negative / embossed pattern is provided.

The stamp 200 is manufactured to have a pattern of yin and yang embossed to form a fine image by curing and drying the polymer material to be the material of the stamp 200 in the master mold produced by the photoelectric method for pattern formation.

Here, the material of the stamp 200 is preferably a material having low interfacial energy and easy molding process so that adhesion does not occur when molding other polymers, and it is preferable that the material is a durable elastomer.

The stamp 200 has a positive and negative pattern for forming the gate line 23, the gate pad line 20, and the floating line 20a, respectively, in the pixel area 3, the gate pad area 5, and the data pad area. It is provided so as to correspond to (8). In this case, the positive and negative patterns corresponding to the floating line 20a may be provided in the data pad region 8 so that the remaining amount of the ER layer 110a does not remain.

As shown in FIG. 8C, the ER layer 110a provided on the substrate 10 is brought into contact with the stamp 200.

Here, when the organic material ER layer (110a) and the organic material stamp 200 is in contact with the repulsive force generated between the organic material and the intaglio pattern engraved in the stamp 200 is generated, the fluidity of the ER layer (110a) is a material You will move. Therefore, as the etching resist of the ER layer 110a moves to the intaglio pattern of the stamp 200, the etching resist is filled with the intaglio pattern. As the etching resist is filled with the intaglio pattern, the stamp 200 comes into contact with a portion of the first base layer 20 ′.

In this case, the ER layer 110a is applied on the first base layer 20 ', and is coated on the entire surface of the substrate 10 in a predetermined amount. However, the gate line 23 and the gate pad line 20 are not uniformly distributed over the entire substrate. A gate line 23 is provided in the pixel region 3, and a gate pad line 20 is provided in the gate pad region 5. In other words, the distribution density of the gate line 23 and the gate pad line 20 (that is, the number of the gate line 23 and the gate pad line 20) is relatively low in the data pad region 8. Have

Accordingly, referring to FIG. 2, the etching resist of the ER layer 610a applied to the gate metal layer 520 ′ in a predetermined amount does not have a space (a negative pattern) in which a material may move. As a result, the etching resist remains in the data pad region 508, thereby forming a dummy pattern 520a. The dummy pattern 520a overlaps with the data pad line 540 formed later, causing parasitic capacitance to cause problems such as signal delay of the display device.

Therefore, in order to solve the problem in which the dummy pattern 520a is formed, the floating line 20a formed of the first base layer 20 'material is formed in the data pad region 8. In order to form the floating line 20a in the data pad region 8, an intaglio pattern is formed on the stamp 200 to form the floating line 20a.

As shown in FIG. 8D, when the ER layer 110a and the stamp 200 are brought into contact with each other to move the material of the etching resist, the stamp 200 may be detached from the substrate 10 after a predetermined time has elapsed. do.

An etching resist filled with the intaglio pattern on the stamp 200 is transferred onto the substrate 10, and an ER pattern 110 is formed on the substrate 10. The ER pattern 110 is positioned at a position where the gate line 23 of the pixel region 3, the gate pad line 20 of the gate pad region 5, and the floating line 20a of the data pad region 8 correspond to each other. Is formed.

In this case, an etchant is provided to the substrate on which the ER pattern 110 is formed. The etchant etches the first base layer 20 ′, which is a metal material, and the first base layer 20 ′ under the ER pattern 110, which is an organic material, is protected by the etchant because of the ER pattern 110.

As shown in FIG. 8E, the first base layer 20 ′ exposed to the etchant provided to the substrate 10 is etched. As such, when the first base layer 20 'is etched, the ER pattern 110 is stripped.

The first base layer 20 ′ protected by the ER pattern 110 remains on the gate line 23 of the pixel region 3, the gate pad line 20 of the gate pad region 5, and the data pad region 8. To form a floating line 20a.

The floating line 20a is formed independently of the data pad region 8, and the floating line 20a may be formed in different shapes (lengths) in the data pad region 8. It may also be formed in the same length. The floating line 20a is connected to a data pad line 40 formed later.

As shown in FIG. 8F, a gate insulating layer 30 is formed on the substrate 10 on which the gate line 23, the gate pad line 20, and the floating line 20a are formed. The semiconductor material layer 70a for forming the semiconductor layer 70, the second base layer 40 ′ for forming the data line 43, and the photosensitive layer for forming a pattern on the gate insulating layer 30. 120 'are sequentially formed.

Here, the second base layer 40 ′ will be described with reference to FIGS. 7A and 7B using molybdenum as an example. In addition, as illustrated in FIG. 6A, the data line 43 and the data pad line 40 formed of the second base layer 40 ′ may use a conductive metal other than molybdenum.

The photosensitive layer 120 ′ is subjected to a photolithography process using a halftone mask. The halftone mask may include a light transmitting region through which light passes, a light blocking region through which light is blocked, and a semi-transmissive region with a limited amount of light, and may harden the photosensitive layer 120 'according to the amount of transmitted light. Is a mask.

As shown in FIG. 8G, the photosensitive layer 120 ′ is exposed to a halftone mask. Here, the photosensitive layer 120 'is cured to form the photosensitive pattern 120.

The photosensitive pattern 120 is formed at a position corresponding to the data line 43 of the pixel region 3 and the data pad line 40 of the data pad region 8.

Here, the substrate 10 is etched. The etching may be etched by a dry etching method. The dry etching method may etch an organic, an inorganic film, a semiconductor film, and molybdenum metal. The dry etching may be etched to the upper portion of the gate insulating layer 30 by adjusting an etching atmosphere (current strength, gas pressure, etc.).

As described above, the photosensitive pattern 120 is etched to form a data line 43 and a data pad line 40. The photosensitive pattern 120 is then stripped.

As shown in FIG. 8H, a passivation film 50 is formed on the substrate 10 on which the data line 43 and the data pad line 40 are formed to protect a plurality of lines such as the switching element TR. .

As shown in FIG. 8I, a plurality of holes 27, 47, and 57 are formed in the predetermined region of the passivation film 50 to connect the plurality of electrodes.

The holes 27, 47, and 57 may include a pass hole 57 exposing the drain electrode 43b of the pixel region 3 and a gate pad line 20 exposing the gate pad region 5. A contact hole 47 is formed in the gate pad contact hole 27 and the data pad region 8 to connect the data pad line 40 and the floating line 20a to expose the floating line 20a.

Here, a dry etching method is used to form the holes 27, 47, and 57, and the dry etching method may etch organic, inorganic layers, semiconductor materials, and molybdenum metal. Here, as shown in FIG. 8G, the dry etching may be performed until the gate line 23 and the floating line 20a are exposed by adjusting an etching atmosphere (current intensity, gas pressure, etc.).

The gate insulating layer 30 formed around the gate electrode of the pixel region 3 may be partially etched. As such, it is possible to form a plurality of holes 27, 47, 57 without an additional mask process.

As illustrated in FIG. 8J, the conductive layer 60 and the pixel electrode 65 are formed by depositing a transparent conductive material on the substrate 10 on which the plurality of holes 27, 47, and 57 are formed. The transparent conductive material may be used, such as ITO, IZO.

The pixel electrode 65 is formed in the pixel region 3 and connected to the drain electrode 43b. The pixel electrode 65 receives the pixel voltage transferred to the drain electrode 43b to display the screen.

The conductive layer 60 connects the floating line 20a and the data pad line 40 to the data pad region 8. Meanwhile, in the gate pad region 5, a gate voltage may be applied to the gate line 23 by the gate contact pad 63 connected to the gate pad line 20.

Since the conductive layer 60 is an oxide such as ITO or IZO, the line under the conductive layer 60 can be protected from air (humidity), etc., thereby improving the reliability of the line.

As described above, in forming the pattern using the stamp 200, by adjusting the amount of material movement of the etching resist according to the distribution density of the pattern, the residual amount of the etching resist which may occur in a region where the pattern distribution density is relatively small is determined. It becomes possible to reduce.

Thus, in the present invention, the floating line 20a formed of the gate metal material is formed in the data pad region 8 in which the line formed of the gate metal material is relatively smaller than the pixel region 3 and the gate pad area 5. . In order to form the floating line 20a, a stamp 200 for forming the floating line 20a may be provided, and an intaglio pattern corresponding to the floating line 20a may be further formed on the stamp 200. .

That is, by providing an intaglio pattern for forming the floating line 20a in the data pad region 8 and transferring the etching resist to the intaglio pattern, the residual amount of the etching resist in the data pad region 8 is increased. Can be reduced.

As such, in forming a predetermined pattern with the stamp 200, the remaining amount of the etching resist may be reduced by further forming a floating pattern 20a for minimizing the difference in distribution density in the intaglio pattern of the stamp 200. Will be.

Therefore, it is possible to solve the generation of the dummy metal such as the dummy pattern formed by the residual amount of the etching resist, and to solve the parasitic capacitance generated by overlapping with the metal stacked on the dummy metal, thereby causing problems such as signal delay of the display device. Will solve the problem.

As described above, a flat plate capable of minimizing a line overlapping a display device having a stacked structure by further forming a floating line in the data pad area so as to minimize the occurrence of a dummy pattern caused by a difference in the distribution density of the line. The display device can be formed.

Accordingly, by eliminating the overlapping lines, parasitic capacitance generated in the overlapping lines can be eliminated, and problems such as signal delay caused by the parasitic capacitance can be minimized.

Those skilled in the art through the above description will be capable of various changes and modifications without departing from the spirit of the present invention.

Claims (13)

A substrate having a pixel region, a gate pad region and a data pad region; A plurality of gate lines provided in the pixel region; A plurality of data lines intersecting the gate lines with the plurality of gate lines and a gate insulating layer interposed therebetween; A plurality of gate pad lines provided in the gate pad area and connected to the gate lines; A plurality of data pad lines provided in the data pad area and connected to the data lines; A plurality of floating lines formed on the same layer as the gate line and spaced apart from the data pad lines to prevent generation of parasitic capacitance; And And a conductive layer connecting the floating line and the data pad line in the data pad area. The method of claim 1, And a switching element in the pixel area. The method of claim 1, And a passivation layer for insulating the gate line, the gate pad line, and the floating line, and a passivation layer for insulating the data line and the data pad line. The method of claim 1, And the conductive layer is formed on the same layer as the pixel electrode connected to the switching element in the pixel region. The method of claim 1, And the data line and the data pad line are formed of molybdenum. delete delete Forming a first base layer on the substrate; Applying an etching resist (ER) layer on the first base layer; Providing a stamp having a plurality of intaglio patterns for patterning the ER layer; Contacting the stamp with the ER layer to form an ER pattern; Etching the first base layer to form a gate line in a pixel region, a gate pad line in a gate pad region, and a floating line in a data pad region by the ER pattern. 9. The method of claim 8, Sequentially forming a gate insulating film, a semiconductor material film, a second base layer, and a photosensitive film on the substrate; Patterning the photosensitive film to form a photosensitive pattern, and etching the semiconductor material film and the second base layer using the photosensitive pattern as a mask; Stripping the photosensitive pattern to form a semiconductor layer forming data lines and channels in the pixel region and a data pad line transferring a data signal to the data pad region; Forming a passivation film on the entire surface of the substrate; Forming a plurality of holes in the data pad region of the passivation layer to connect the floating lines and the data pad lines; And forming a conductive layer connecting the data pad line and the floating line on the hole. 10. The method of claim 9, Forming a hole in the passivation layer and connecting the floating line and the data pad line to the conductive layer; And forming a pass hole in the passivation layer of the pixel region, and further forming a pixel electrode on the passivation layer using the same material as the conductive layer. 10. The method of claim 9, And the data line or the data pad line is formed of molybdenum. 10. The method of claim 9, And the floating line and the data pad line are spaced apart from each other by a predetermined interval. 10. The method of claim 9, And the data pad line and the floating line overlap a predetermined area.

Images