KR101224259B1 - High speed sense amplifier and Method of operating the high speed sense amplifier - Google Patents

Abstract

A sense amplifier of a semiconductor memory device having a memory cell array having a plurality of memory cells includes a sense amplifier circuit for sensing and amplifying a difference between a cell current of a first input node and a reference current of a second input node, and the sense amplifier circuit. A current coupled to the first and second input nodes of to provide a multiple of N times the bias current to the first and second input nodes, where N is two or more natural number-amplified first and second distributed currents, respectively. It includes a mirror circuit. A simple current mirror structure provides a fast response speed of the sense amplifier and provides high sensitivity during read operation of the sense amplifier by separating the bit line node and the input of the sense amplifier. .

Description

High speed sense amplifier and method of operating the high speed sense amplifier

The present invention relates to a sense amplifier of a semiconductor memory.

Spin-Transfer-Torque MRAM (hereinafter STT-MRAM) is being actively researched as the next generation universal memory. Universal memory features nonvolatile and infinite write cycles. Such a universal memory is expected to bring a significant performance improvement in digital devices because it can store information even when the power is turned off when the fast operation speed is high.

However, the limitations of silicon-based memory and the development of conventional DRAM, SRAM, and flash memory have their advantages and disadvantages due to their inherent limitations. On the other hand, STT-MRAM, a magnetic-based memory using spin torque, is being researched rapidly as a powerful next-generation memory that can replace existing memory due to its high density, high speed, and non-volatile advantages.

STT-MRAM is based on MTJ (Magnetic Tunnel Junction), which is composed of a free layer, a tunnel barrier, and a pinned layer. MTJ, a cell of MRAM composed of a ferromagnetic layer, has the following characteristics.

Firstly, MTJ is nonvolatile due to memory operation along the magnetization direction. Secondly, the MTJ has a low power and high integration due to the decrease in critical current density as the device size decreases. Thirdly, the MTJ has a faster switching speed in the magnetization direction due to spin torque, which allows a write operation faster than a DRAM in theory.

These advantages make STT-MRAM a new next-generation memory. However, the method for driving STT-MRAM requires precise current and voltage control to guarantee the data of the MTJ cell, and the need to improve the read and write speed in terms of circuitry for faster speed than DRAM. have.

Another important feature of STT-MRAM is the rate of change of magnetoresistance (MR) relative to the MTJ voltage. MR decreases as the voltage applied to the MTJ increases. Therefore, precise voltage and current control is required to ensure sufficient sensing margin during read operation.

1 is a conceptual diagram of a sense amplifier used in a conventional voltage-type MRAM. The cell structure of FIG. 1 is a basic 1T 1MTJ structure. That is, the cell on the left consists of one transistor M01 and one MTJ (MTJ1), and the reference cell on the right consists of one transistor M02 and one MTJ (MTJ2). MTJ1 10 and MTJ2 30 may each be modeled as a resistor. Current sources I1 12 and I2 32 are used to apply appropriate bias to each MTJ1 10 and MTJ2 30, respectively. Due to the current source I1, the voltage of the V _BL node (bit line node voltage) is determined by the magnetoresistance value of MTJ1, and the voltage (reference voltage) of the V _BLB node is determined by the magnetoresistance value of MTJ2 due to the current source I2. The voltage of the V _BL node is applied to the input terminal of the sense amplifier 200 to read the state of the cell through comparison with the reference voltage V _BLB .

On the other hand, a current method that receives the input of the sense amplifier 200 as a current may be used for a faster response speed. The current method of operation is similar to the conventional voltage method described above. A constant current is generated through the current source and the generated constant current flows through two paths. One of the two paths is to the MTJ cell and the other is to the input of the sense amplifier. The constant current generated from the current source is distributed according to the size of the MTJ's magnetoresistance. Similarly, the reference current is determined according to the value of the reference cell, and the cell state is read through the comparator according to the size of the cell current and the reference current. .

In the case of the conventional voltage method, the response speed is slower than that of the current method, but the voltage of the V _BL node (bit line node voltage) is applied to the input node of the sense amplifier 200-the gate node of the sense amplifier 200. That is, since the bit line node voltage is applied to the gate node of the sense amplifier 200, the output of the sense amplifier does not interfere with the bit line node so that interference does not occur in the MTJ cell.

As the density of memory cells increases, the read current decreases in proportion, so the read current must be very low, such as several amperes.

Therefore, in the current method, since the input current is small, compensation for sensing margin and response speed of the sense amplifier is necessary. In addition, in the conventional current method, since the gain of the sense amplifier is very large, kickback noise may occur when the output of the sense amplifier affects the bit line node during operation, and thus sensitivity during read operation. There is a problem that fall.

When the voltage method is used so that there is no interference to the cell of the MTJ due to the kickback noise during the read operation, the response speed during the read operation is lower than that of the current method. In the case of the current method, the response speed during the read operation is determined by the voltage method. Higher than this, but the interference of the MTJ cell due to the kickback noise occurs, the sensitivity (sensitivity) is reduced during the read operation.

Accordingly, an object of the present invention is to provide a sense amplifier for improving response speed during a read operation while having high sensitivity in read operation in consideration of an operation characteristic of the MRAM.

The sense amplifier of the semiconductor memory device having a memory cell array having a plurality of memory cells according to an aspect of the present invention for achieving the above object of the present invention is the reference of the cell current of the first input node and the reference of the second input node A sense amplifier circuit that senses and amplifies the difference between the currents and a bias current coupled to the first and second input nodes of the sense amplifier circuit to the first and second input nodes by N times where N is a natural number greater than two A current mirror circuit providing the amplified first and second distributed currents respectively.

In addition, a semiconductor memory device having a memory cell array having a plurality of memory cells according to another aspect of the present invention for achieving the object of the present invention is included in the cell current of the first input node and the reference current of the second input node A method of operating a sense amplifier that senses and amplifies a difference between the steps of receiving a bias current and N times the bias current to the first and second input nodes of the sense amplifier circuit, where N is a natural number of two or more Providing a first distribution current and a second distribution current, respectively, and distributing the N times amplified first and second distribution currents when the sense amplifier enable signal is activated to respectively divide the first and second distribution currents of the sense amplifier circuit. Providing as a cell current and a reference current to a second input node.

As described above, according to the sense amplifier according to the embodiments of the present invention, a simple current mirror structure may be used to compensate for a low sensing margin due to a very low input current in the conventional current method. In addition, by ensuring sufficient sensing margin, it is possible to realize faster response speed than conventional current methods.

In addition, by separating the bit-line node and the sense amplifier input stage, it is possible to prevent kickback noise generated by the existing current method, so that it has a high sensitivity during read operation. Read operation can be performed.

In particular, when applied to STT-MRAM, the next-generation memory using magnetoresistance, it can perform fast and stable operation even at low Tunneling Magnetoresistance (TMR), and it will be able to show sufficient performance even if the cell performance of STT-MRAM is not high. In addition, the cost can be reduced due to the simple structure and simple operation method, and thus high efficiency can be achieved.

1 is a conceptual diagram of a sense amplifier used in a conventional voltage-type MRAM.
2 is a conceptual diagram illustrating a sense amplifier according to an embodiment of the present invention.
FIG. 3 shows a detailed circuit diagram of the sense amplifier circuit of FIG. 2.
4 is an operation timing diagram of a sense amplifier according to an embodiment of the present invention.
5 is a graph showing a simulation result of a change in response speed of a sense amplifier according to an embodiment of the present invention while varying the amplification factor of a current mirror.
6 is a graph showing a simulation result of a change in response speed of a sense amplifier according to an embodiment of the present invention while varying the TMR.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the invention is not intended to be limited to the particular embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.

When a component is referred to as being "top" or "bottom" of another component, it should be understood that other components may be present in between, although they may be formed directly on the other component.

The terms first, second, A, B, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. And / or < / RTI > includes any combination of a plurality of related listed items or any of a plurality of related listed items.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In order to facilitate a thorough understanding of the present invention, the same reference numerals are used for the same means regardless of the number of the drawings.

First, the overall operation of the bit line sense amplifier will be described.

Although not shown in the drawings, the semiconductor memory includes a memory cell array having a plurality of memory cells, each of which is connected to a word line WL and a bit line and is connected to the bit line BL by a bit line sense amplifier. The carried amplified data is transferred to the data bus to read the data.

The bit line BL is precharged to a precharge voltage, for example, 1/2 of the internal power supply voltage VDD, wherein the bit line BL and the bit line BLB to which the selected memory cell is connected are not. The two bit lines BL are equalized to eliminate the voltage difference between them. The row decoder analyzes an externally input row address to select a word line WL corresponding to the row address, and the bit line BL connected to the memory cell connected to the selected word line WL and the bit line BL not connected to the row line. A potential difference is generated between the BLBs.

In this case, when the sense amplifier control signal Ven is enabled, the sense amplifier operates to sense and amplify a potential difference between the bit line BL to which the selected memory cell is connected and the bit line BLB to which the selected memory cell is not connected. For example, assuming that the data stored in the selected memory cell is low-level data, the voltage of the bit line BL to which the selected memory cell is connected is lower than the precharge voltage. In this case, the bit line to which the selected memory cell is not connected Since the voltage of the BLB maintains the precharge voltage, a potential difference occurs between the two bit lines BL and BLB.

Subsequently, when the column address is analyzed by the column decoder and the column control signal corresponding to the column address is enabled, the amplified data carried on the bit line BL is transmitted to the data bus by the bit line sense amplifier.

Hereinafter, a sense amplifier according to an embodiment of the present invention will be described.

2 is a conceptual diagram illustrating a sense amplifier according to an embodiment of the present invention, FIG. 3 is a detailed circuit diagram of the sense amplifier circuit of FIG. 2, and FIG. 4 is an operation timing diagram of the sense amplifier according to an embodiment of the present invention. to be.

Referring to FIG. 2, the memory cell Cell connected to the selected word line WL includes MTJ1 110, which is modeled as a resistor, and M01 having a word line WL connected to a gate thereof. Bit line BL is V _BL of a memory cell connected to selected word line WL. Is connected to the voltage node.

The reference cell includes MTJ2 310, which is modeled as a resistor, and M02 having a word line WL connected to a gate thereof. Bit line BLB is V _BLB of reference cell Is connected to the voltage node.

2, a sense amplifier according to an embodiment of the present invention includes a sense amplifier circuit 200 and current mirrors 120 and 320. The current mirror may include a first current mirror 120 and a second current mirror 320.

The sense amplifier circuit 200 may be preferably implemented as a latch type sense amplifier circuit, but is not limited thereto, and may be implemented as other types of sense amplifier circuits that sense and amplify voltages or currents of two different output stages. This is possible. Hereinafter, a case where a latch type sense amplifier circuit is used as the sense amplifier circuit 200 will be described.

The current source I _bias is MTJ1 (110) and MTJ2 second reference to provide a first reference current I _ref1 to MTJ1 (110) to divide the current of current source I _bias, and MTJ2 310 to now applying a bias to the 310 Provide the current I _ref2 .

The first current mirror 120 generates a first distribution current I1 obtained by amplifying the first reference current I _ref1 at a ratio of 1: N to generate a first input node of the sense amplifier circuit 200 (eg, FIG. 3). Provided to node c) corresponding to the drain of transistor M07. For example, N may have a power of 2, such as 2, 4, 8, 16, 32, and 64, but is not limited thereto and may have another natural number of 2 or more.

The second current mirror 330 generates a second distribution current I3 obtained by amplifying the second reference current I _ref2 , which divides the current of the current source I _bias , in a ratio of 1: N to generate a second input node of the sense amplifier circuit 200. (For example, the node d corresponding to the drain of the transistor M08 in FIG. 3).

The sense amplifier according to an embodiment of the present invention compensates for the low sensing margin due to the very low input current of the sense amplifier circuit 200 in the conventional current scheme by using the current mirror structure as described above, and provides sufficient sensing. By securing a margin, the response speed is faster than that of conventional current sense amplifiers.

In addition, the sense amplifier according to an embodiment of the present invention provides a structure in which a bit line BL node connected to a memory cell and a first input node (node c of FIG. 3) of the sense amplifier are separated. In addition, a bit line (BLB) node connected to a reference cell corresponding to the memory cell and a second input node (node d) of the sense amplifier are provided. Specifically, V _BL determined by the state of the memory cell to the gates of MP01 and MP02 of the current mirror 130 composed of the PMOS transistors of MP01 and MP02. By configuring the voltage node (bit line BL node) to be connected, the input terminal of the memory cell and the sense amplifier circuit can be separated. Also, V _BLB to the gates of MP04 and MP05 of the current mirror 330 composed of PMOS transistors of MP04 and MP05. By configuring the voltage node (bit line BLB node) to be connected, it is possible to separate the reference cell and the second input node (node d) of the sense amplifier circuit.

Therefore, due to the large gain of the sense amplifier circuit 200 during operation of the sense amplifier circuit 200, the output terminal of the sense amplifier circuit 200 (for example, the drain of the transistor M09 of FIG. 3) affects the bit line node. By preventing kickback noise, the read operation may have a high sensitivity, and thus the read operation may be stably performed.

Hereinafter, an operation of a sense amplifier according to an embodiment of the present invention will be described with reference to FIG. 3.

Referring to FIG. 3, a sense amplifier according to an embodiment of the present invention includes a cell current supply unit 110, a first current mirror 130, a second current mirror 330, a first input current distribution circuit 140, A second input current distribution circuit 340, a comparator 220 and an equalizer 210 are included.

The cell current supply unit 110 may include a current source I _bias . The bias current I _bias provided from the cell current supply unit 110 is distributed left and right, and serves to apply a bias to the MTJ1 110 by providing a first reference current I _ref1 to the MTJ1 110, and MTJ2 310. The second reference current I _ref2 serves to apply a bias to the MTJ2 310.

The first current mirror 130 amplifies the first reference current I _ref1 at a ratio of 1: N to generate a first distribution current I1 and provides it to the first input node (node c) of the sense amplifier circuit 200. . The first current mirror 130 may be implemented with PMOS transistors MP01 and MP02. The source of MP01 and the source of MP02 are commonly coupled to one end of current source I _bias , the gate of MP01 is connected to the gate of MP02 to the drain and bitline voltage node (V _BL ) of MP01, and the drain of MP02 is A drain of M03 and a first input node (node c) of sense amplifier circuit 200 in first input current distribution circuit 140.

The second current mirror 330 amplifies the second reference current I _ref2 at a ratio of 1: N to generate a second distribution current I3 and provides it to the second input node (node d) of the sense amplifier circuit 200. . The second current mirror 330 may be implemented with PMOS transistors MP04 and MP05. The source of MP04 and the source of MP05 are commonly coupled to one end of current source I _bias , the gate of MP04 is connected to the gate of MP05 to the drain and bitline voltage node (V _BLB ) of MP04, and the drain of MP05 is Is connected to a drain of M06 in second input current distribution circuit 340 and a second input node (node d) of sense amplifier circuit 200.

When the sense amplifier enable signal V _EN becomes High, the first input current distribution circuit 140 distributes the first distribution current amplified by a ratio of 1: N by the current mirror 130 on the left to sense amplifier circuit 200. Cell current I2 is provided to a first input node (node c in FIG. 3). The first input current distribution circuit 140 may be implemented with NMOS transistors M03 and M07. In detail, when the sense amplifier enable signal V _EN becomes High, the first input current distribution circuit 140 may turn on M07 to turn on the first distribution current amplified by a ratio of 1: N by the current mirror 130 on the left. To provide the cell current I2 to the first input node (node c in FIG. 3) of the sense amplifier circuit 200.

When the sense amplifier enable signal V _EN becomes High, the second input current divider circuit 340 distributes the second divider current I3 amplified by a ratio of 1: N by the current mirror 330 on the right to sense the sense amplifier circuit ( To the second input node (node d of FIG. 3) as a reference current of the reference cell. The second input current distribution circuit 340 may be implemented with NMOS transistors M06 and M08. Specifically, when the sense amplifier enable signal V _EN becomes High, the second input current distribution circuit 340 turns on the second distribution current amplified at a ratio of 1: N by M08 turned on by the current mirror 330 on the right. And distributes it to the second input node (node d in FIG. 3) of the sense amplifier circuit 200 as the reference current of the reference cell.

The sense amplifier circuit 200 includes a first input unit 142, a second input unit 342, a comparator 220, and an equalizer 210.

The first input unit 142 may be implemented with, for example, an NMOS transistor M07, and the second input unit 342 may be implemented with, for example, an NMOS transistor M08.

When the sense amplifier enable signal V _EN becomes High, the current amplified in the ratio of 1: N by the current mirror 130 on the left side is caused by the current path of the input current distribution circuit 140 on the left side consisting of transistors M03 and M07. The current amplified in the ratio of 1: N by the current mirror 330 on the right side is distributed by the current path of the input current distribution circuit 340 on the right side consisting of transistors M06 and M08.

The comparator 220 senses a difference between a current flowing in the drain of M07 distributed by the first input current distribution circuit 140 and a current flowing in the drain of M08 distributed by the second input current distribution circuit 340. By amplifying, data is read during a read operation. For example, the comparator 220 cross-couples the inputs and outputs of the first inverter including the NMOS transistor M09 and the PMOS transistor M11 and the second inverter including the NMOS transistor M10 and the PMOS transistor M12 to each other as illustrated in FIG. 3. can be implemented. The sources of the PMOS transistors M11 and M12 may be implemented to be coupled to the power supply voltage VDD, and the drain node (output node a of the sense amplifier) of the PMOS transistor M11 is connected to one end of the switching element M14 constituting the equalizer portion 210. The drain node of the PMOS transistor M12 (the output node b of the sense amplifier) may be implemented to be connected to one end of the switching element M15 constituting the equalizer 210. The source of the NMOS transistor M09 may be implemented to be connected to the drain of M07 constituting the first input terminal 142, and the source of the NMOS transistor M10 may be implemented to be connected to the drain of M08 constituting the second input terminal 342. have.

The equalizer 210 performs an equalization operation to eliminate the voltage difference between the bit line BL to which the selected memory cell is connected and the bit line BLB to which the selected memory cell is connected when the sense amplifier enable signal V _EN is set to High. To perform. The equalizing unit 210 may be implemented with PMOS transistors M13, NMOS transistors M14, M15, and M16. In detail, when the sense amplifier enable signal V _EN becomes High, the equalizing unit 210 outputs the voltage of the output amplifier of the sense amplifier circuit 200 when M14 and M15 are turned on so that the voltage divided by 1/2 VDD by M13 and M16 is divided. A memory cell connected to the selected word line _WL is activated by performing the equalization operation by eliminating the voltage difference between the sense amplifier output nodes a and b by providing it to (nodes a and b). The voltage difference between the connected bit line BL and the bit line BLB that is not connected is equalized.

Hereinafter, the operating mechanism of the sense amplifier according to the exemplary embodiment of the present invention will be described with reference to FIGS. 3 and 4.

In the sense amplifier according to the exemplary embodiment of the present invention, first, both ends of the output nodes a and b of the sense amplifier are precharged so that the bit line BL is precharged, for example, 1 / time of the internal power supply voltage VDD. It is pre-charged to 2- and the two bit lines BL and BLB are equalized. Specifically, when the row decoder analyzes an externally input row address and selects a word line WL corresponding to the row address, the word line selection signal V _WL is activated at high at T1 to be coupled to the word line WL. At the same time as M01 is selected, a cell is loaded and both ends (output nodes a and b) of the comparator 220 of the sense amplifier circuit 200 are configured with the transistors M13, M14, and M15 constituting the equalizer 210. And the current flowing through the transistor M07 equalized by M16 and constituting the first input terminal 142 of the sense amplifier circuit 200 and M08 constituting the second input terminal 342 of the sense amplifier circuit 200. Be prepared.

When the transistor M01 coupled to the word line WL is turned on and the cell is loaded, the bit line voltages V _BL and V _BLB are determined according to resistance values of the MTJ1 and MTJ2 (reference cell), and accordingly, a first configured of M01 and M02 The current is amplified by a preset ratio of 1: N in the current mirror 130 and the second current mirror 330 composed of M04 and M05.

Then, when the sense amplifier enable signal V _EN signal is activated high to operate the sense amplifier at T2 while the word line select signal V _WL is activated high, it is amplified by the current mirrors 130 and 330. The current is again distributed by the current paths of M03 and M07 constituting the first input current distribution circuit 140 and M06 and M08 constituting the second input current distribution circuit 340, and constituting the latch comparator 220. M09, M10, M11, and M12 operate to sense and amplify the current difference between the cell current flowing through M07 and the reference cell current flowing through M08, and as a result, data stored in the memory cell is read. At this time, as shown in FIG. 4, the voltage difference between the output node voltage V _OUT of the sense amplifier circuit 200 and the output node voltage / V _OUT of the sense amplifier circuit 200 is sensed and amplified.

Subsequently, when the column address is analyzed by the column decoder and the column control signal corresponding to the column address is enabled, the amplified data carried on the bit line BL is transmitted to the data bus by the bit line sense amplifier.

Here, the amplification factor of the current mirror is defined by the following simple equations (1) to (3).

[Equation 1]

I _{dm 01} = -1 / 2 _{u p} c _ox (W / L) m ₀₁ (V _GS -V _TH ) ²

&Quot; (2) "

I _dm02 = -1 / 2 _{u p} c _ox (W / L) m ₀₁ (V _GS -V _TH ) ²

&Quot; (3) "

I _dm02 = I _dm01 [(W / L) ₀₂ / (W / L) ₀₁ ]

(However, PMOS transistors MP01, MP02 and MP04, MP05 are all operative in the saturation region, I _dm01 is a drain current in a saturation region of the PMOS transistor MP01, I _dm02 is a drain current in a saturation region of the PMOS transistor MP02, u _p Is the mobility of holes, c _ox is the thickness of oxide used as the insulating film, W is the channel width, L is the channel length, W / L is the aspect ratio, V _GS is the voltage difference between gate and source, and V _TH is the threshold voltage.

In the same manner as above, the current may be amplified in the ratio of 1: N in the first current mirror 130 by the aspect ratio of the W / L between the PMOS transistors MP01 and MP02, and the W / L between the PMOS transistors MP04 and MP05 may be amplified. The current may be amplified in the ratio of 1: N in the second current mirror 330 by the aspect ratio.

 If the MTJ has an MR ratio of 100% and the cell current is 5 uA or less, the cell current difference is about 0.1 uA or less. When the current is amplified by about 10 times, the current difference entering the sense amplifier circuit 200 becomes 1uA, so that the operating speed can be faster. This may be equally applied even if the MR ratio is lowered. In addition, even if the MR ratio is lower, the compensating current of the current mirror may have a response speed that is hardly different from the high MR ratio.

5 is a graph showing a simulation result of a change in response speed of a sense amplifier according to an embodiment of the present invention while varying the amplification factor of a current mirror.

In FIG. 5, when the ratio of Tunneling Magnetoresistance (TMR) is 100% and the current flowing through the MTR is 2 uA, the amplification ratios of the current mirrors 130 and 330 of the sense amplifier according to an embodiment of the present invention are N = 8, N. The response characteristics of the sense amplifier are shown by changing from = 4, N = 2, and N = 1.

Referring to FIG. 5, it can be seen that the response speed of the sense amplifier can be improved by adjusting the amplification factor of the current mirror of FIG. 3 according to an embodiment of the present invention. That is, it can be seen that the response speed is improved as the amplification ratio N of the current mirrors 130 and 330 of the sense amplifier increases.

6 is a graph showing a simulation result of a change in response speed of a sense amplifier according to an embodiment of the present invention while varying the TMR.

6 shows the response characteristics of the sense amplifier while changing the TMR to 200%, 100%, 50%, and 10% when the amplification ratio N = 1 of the current mirror and the current flowing through the MTR is 2uA.

Referring to FIG. 6, it can be seen that the larger the TMR, the faster the response speed of the sense amplifier.

In the case of commercially available products, the TMR has a value of 100% or less. Referring to FIGS. 5 and 6, the response speed of the sense amplifier is increased by increasing the amplification ratios N of the current mirrors 130 and 330 even for the TMR of 100% or less. It can be seen that it can increase. That is, even when the TMR is low, the response speed of the sense amplifier may be increased by increasing the amplification factor N of the current mirrors 130 and 330.

The sense amplifier according to the embodiments of the present invention is not limited to MRAM, but is similarly applied to phase change RAM (PCRAM), which is being actively developed as a next-generation memory, so that the sense amplifier has high sensitivity and improves operation speed during read operation of the sense amplifier. Can be applied. PCRAM is a non-volatile memory that uses heat to change a substance into crystalline or amorphous material. The PCRAM is similar to a sensing method using an MRAM that uses resistivity to classify data into resistance components according to a change in material properties. In addition, the sense amplifier according to the embodiments of the present invention is also applied to ReRAM, which is a next-generation memory device using resistivity, and has high sensitivity during read operation of the sense amplifier and may be applied to improve the operation speed.

Preferred embodiments of the present invention described above are disclosed for purposes of illustration, and those skilled in the art will be able to make various modifications, changes, and additions within the spirit and scope of the present invention. Additions should be considered to be within the scope of the following claims.

130, 330: current mirror
140, 340: input current distribution circuit
200: sense amplifier circuit

Claims (12)

A sense amplifier of a semiconductor memory device having a memory cell array having a plurality of memory cells,
A sense amplifier circuit for sensing and amplifying a difference between the cell current of the first input node and the reference current of the second input node; And
N times the bias current to the first and second input nodes coupled to the first and second input nodes of the sense amplifier circuit, where N is the two or more natural number-amplified first and second distribution currents. And a current mirror circuit for providing each of the sense amplifiers of the semiconductor memory device. The sense amplifier of claim 1, further comprising a cell current supply including a current source for providing the bias current. 3. The current mirror circuit of claim 2, wherein the current mirror circuit
A first current mirror which amplifies the first reference current divided by the bias current by N times to generate a first divided current and provides the first divided current to the first input node of the sense amplifier circuit; And
And a second current mirror configured to generate a second distribution current by amplifying the second reference current divided by the bias current by N times to generate a second distribution current and to provide the second input node to the sense amplifier circuit. amplifier. The method of claim 3, wherein the first current mirror is
A first PMOS transistor having a source coupled to one end of a current source supplying the bias current, the gate being connected to a drain and a first bit line node; And
A second PMOS transistor having a gate connected to the gate of the first PMOS transistor, a source coupled to one end of a current source supplying the bias current, and a drain connected to the first input node of the sense amplifier circuit
A sense amplifier of a semiconductor memory device comprising a. The method of claim 4, wherein the second current mirror is
A third PMOS transistor having a source coupled to one end of a current source supplying the bias current, the gate being connected to a drain and a second bit line node; And
A fourth PMOS transistor having a gate connected to the gate of the third PMOS transistor, a source coupled to one end of a current source supplying the bias current, and a drain connected to the second input node of the sense amplifier circuit
A sense amplifier of a semiconductor memory device comprising a. The method of claim 5,
A first input current distribution circuit for distributing the first distribution current amplified N times by the first current mirror to provide a cell current to a first input node of the sense amplifier circuit when the sense amplifier enable signal is activated; And
A second input current distribution circuit for distributing the second distribution current amplified N times by the second current mirror to provide a reference current to the second input node of the sense amplifier circuit when the sense amplifier enable signal is activated
The sense amplifier of the semiconductor memory device further comprises. 7. The circuit of claim 6, wherein the first input current distribution circuit is
A drain of the second PMOS transistor and a first input node of the sense amplifier circuit, a gate of which is connected to a source, and a source of which includes a first NMOS transistor connected to ground Sense amplifiers. 7. The circuit of claim 6, wherein the second input current distribution circuit is
A drain of the fourth PMOS transistor and a second input node of the sense amplifier circuit, a gate of which is connected to a source, and a source of which includes a second NMOS transistor connected to ground Sense amplifiers. 2. The first bit line of claim 1, wherein a first bit line node connected to a memory cell selected by a word line and a first input node of the sense amplifier circuit are electrically separated from each other, and the first bit line connected to a reference cell corresponding to the memory cell. And a node and a second input node of the sense amplifier circuit are electrically separated. The sense amplifier of claim 1, wherein the sense amplifier circuit is a latch type sense amplifier circuit. Method of operating a sense amplifier included in a semiconductor memory device having a memory cell array having a plurality of memory cells to sense and amplify the difference between the cell current of the first input node and the reference current of the second input node,
Receiving a bias current; And
Providing a first distribution current and a second distribution current, wherein the bias current is N times the first and second input nodes of the sense amplifier circuit, where N is at least two natural number-amplified first and second distribution currents, respectively; And
Distributing the N and amplified first and second distribution currents when the sense amplifier enable signal is activated and providing them as the cell current and reference current to the first and second input nodes of the sense amplifier circuit, respectively.
Method of operation of a sense amplifier comprising a. 12. The first bit line of claim 11, wherein the first bit line node connected to the memory cell selected by the word line and the first input node of the sense amplifier circuit are electrically separated and connected to the reference cell corresponding to the memory cell. And a node and a second input node of the sense amplifier circuit are electrically separated.

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