KR101211987B1 - Power providing apparatus and power providing method for processor having multiple power level - Google Patents

Abstract

The present invention conforms to a power supply order for a processor having a plurality of power levels, and supplies power stably so that a processor having a plurality of power levels can boot stably. Provides a supply device and a power supply method.
By using a power supply and a power supply method for a processor having a plurality of power levels, the inventors take into account component variations, eliminate unwanted power or current applied to a processor having a plurality of power levels, and By eliminating the leakage current applied from the component to enable stable booting, the failure rate due to boot failure of electronic products can be significantly reduced.

Description

POWER PROVIDING APPARATUS AND POWER PROVIDING METHOD FOR PROCESSOR HAVING MULTIPLE POWER LEVEL}

The present invention provides a power supply and a power supply method for a processor having a plurality of power levels, specifically, a plurality of power supplies to enable a stable booting of a processor in accordance with a power supply order for a processor having a plurality of power levels. The present invention relates to a power supply and a power supply method for a processor having a plurality of power levels, which can variably control the power-on time for power supplies having a level, and can remove external leakage current and unwanted power or current. will be.

As semiconductor technology advances, various functions can be performed in a processor integrated with a semiconductor. For example, a processor may include a coprocessor capable of performing arithmetic, a coprocessor for processing audio and video, an auxiliary block for processing external I / O, and the like in addition to a plurality of CPU cores that execute instructions. It became. This advancement in semiconductor technology also lowers the power levels driven within the processor, bringing the CPU cores or internal logic blocks of 3.3V or 5V power supplies down to 1.2V or even lower. These lower power levels contribute to reducing processor power consumption, reducing heat generation, and increasing processing speed within the processor.

On the other hand, although the power level inside the processor is lowered, the processor is mounted on the main board, so that it cannot communicate uniformly at the lower power level in order to communicate with the external chipset. As a result, the processor generally receives power from one or more power levels from the outside, and thus the processor is mixed with a plurality of power levels.

As processors get faster and multiple power levels are scattered, vendors of processors define the relevant standards that must be adhered to amongst a number of challenging power levels as provided development standards, and developers, such as motherboards, can choose power levels according to those development standards. You are asked to meet the relevant standards.

Standards related to these power levels include the time required for a plurality of power supplies to start to stabilize to a specific power level, the relationship with each power supply before the power supplies have stabilized to a specific level, and a reset after the power has stabilized. The timing at which the signal is released, and the allowable power supply error range of the power supply level after each of the plurality of power supplies are stabilized are defined.

To better understand the standards related to these power levels, FIG. 1 is a diagram illustrating a standard of a power supply sequence of a multimedia processor having three power sources as an example. The multimedia processor uses 1.2V for internal core logic, 2.5V for memory interface and 3.3V for external chipset or GPIO communication. According to the standard of FIG. 1, a maximum of 10 mSec must be reached from 1.2 V power supply to 1.08 V until 3.3 V power supply is 3 V, 1.2 V is stabilized first, then 2.5 V is stabilized and finally 3.3 V is supplied. Requires stabilization. And below 0.7 V, the 3.3 V supply must be higher than the 1.2 V supply, and 2.5 V has the same requirements. However, at 0.7V or less, it is defined that a 1.2V power supply may be higher at 0.5V or less than other 2.5V or 3.3V power supply for a period of about 250msec or less. In case of violating the standard, it is described that excessive current flow may occur in the I / O cell, and also latchup phenomenon may occur inside. In case of breaking the power supply sequence, the multimedia processor cannot read the initialization code and start up normally. In this case, a latch-up phenomenon or the like occurs in a register in the multimedia processor, such that the processor fails to start normally and fails to initialize. As a result, a large number of defective products may be produced. In addition, these phenomena face a difficult problem that cannot be verified by a developer even using a debugging port.

On the other hand, in addition to the processor, the main board is equipped with a number of components connected to the processor. Depending on the error range of multiple components, for example, depending on the capacitance error that charges each of a plurality of power sources, the time point at which the power is stabilized is 10% or more (20% or more depending on parts) for each main board. You may fly. In addition, it may be difficult to accurately meet the requirements of the power supply according to the difference in the error of the capacitance of each power supply of a plurality of power supply, and the size of the capacitance of the capacitance for a plurality of power supply may vary, respectively, so that exactly the requirements of the power supply standard It may be difficult to match. There is also a need to prevent leakage current caused by the current from signals being output from multiple components (e.g., GPIO output ports) before the processor power is stabilized, and a method or device is needed to collectively address these problems. Do.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and a plurality of power levels of a processor having the plurality of power levels as an input power supply the power of the processor so as to stably boot a processor having a plurality of power levels. It is an object of the present invention to provide a power supply and a power supply method that conforms to the order.

Another object of the present invention is to provide a power supply device and a power supply method for stably booting the processor by removing leakage current from other ICs connected through a processor having a plurality of power levels and a GPIO port. .

Another object of the present invention is to provide a power supply device and a power supply method for stably booting the processor by removing an unintended power source from a power source provided to a processor having a plurality of power levels.

A power supply for a processor having a plurality of power levels for achieving the above object is a plurality of DC-DC converters, each of the plurality of DC-DC converters, the output power level of the level specified from the input power level Power supply for supplying or stopping power to input power of the plurality of DC-DC converters and the plurality of DC-DC converters to output power according to control of an enable signal for each of the plurality of DC-DC converters A power control processor for outputting a stop control signal and outputting at least one enable signal to the plurality of DC-DC converters after power is supplied to input power of the plurality of DC-DC converters, The power control processor controls the power supply-discontinued control signal so that power is supplied to input power of the plurality of DC-DC converters repeatedly two or more times. It is characterized in that.

In addition, the power supply method for a processor having a power level for achieving the above object, the step of supplying power to the input power of the plurality of DC-DC converter and the power supply to the input power of the plurality of DC-DC converter Stopping supply, re-powering input power of the plurality of DC-DC converters, and outputting at least one enable signal to allow a power control processor to control power outputs of the plurality of DC-DC converters Steps.

The power supply and power supply method for a processor having a plurality of power levels in accordance with the present invention as described above, by first removing the unwanted power or current (eg inrush current) to the plurality of power applied to the processor. The advantage that the processor can be booted stably and secondly, the power supply time for each power source of the processor can be automatically selected in consideration of component deviations, thereby providing developers with design convenience and failing to boot the processor. It can be reduced to reduce the defective products, and third, the advantage that can eliminate the leakage current caused by the components connected to the processor.

1 is a diagram showing a standard showing a power supply sequence of a multimedia processor having three power sources as inputs.
2 is a diagram illustrating an exemplary electronic device in which a power supply is used.
3 is a block diagram illustrating an embodiment of a power supply device.
4 is a detailed block diagram of a power control processor.
5 is a signal chart illustrating each signal in chronological order as controlled by the CPU core in the power supply control processor or used as an input.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail. However, the spirit of the present invention is not limited to the embodiments in which the present invention is presented, and those skilled in the art who understand the spirit of the present invention may easily add other embodiments by adding, changing, deleting or adding components within the scope of the same idea. It may be suggested, but this will also fall within the scope of the spirit of the present invention.

2 is a diagram illustrating an exemplary electronic device using a plurality of power sources in which the power supply 200 is used. According to FIG. 2, the electronic device includes an SMPS 100 (SMPS is an abbreviation of “Switching Mode Power Supply”), a power supply 200, and a processor 300 having a plurality of power levels. For example, it may further include a graphics processor or a video encoder. Exemplary graphics processors or video encoders are illustrative, but not limited to, for ease of understanding. An example graphics processor or video encoder may communicate with a processor 300 having a plurality of power levels and a processor 300 having a plurality of power levels through a General Purpose Input Output (GPIO) or other standard interface. Control signals or powers transferred between the SMPS 100, the power supply 200, the processor 300 having a plurality of power levels, and / or other ICs may be differently connected according to the hardware configuration of the electronic device. For example, if each is configured on a separate PCB board, it can be connected using wires and connectors, and if it is connected on the same PCB board, it can also be connected using a PCB pattern in the board.

The SMPS 100 receives an AC power supply or a DC power supply, and outputs the switching power and the constant power supply of one or more specific power levels as the DC power supply. In addition, the SMPS 100 may further receive an input of a power ON / OFF switch. The SMPS 100 includes an AC-DC converter 110, a switching power supply unit 130, and a constant power supply unit 150. When the input power is input to DC power, the AC-DC converter 110 may be omitted. have. The AC-DC converter 110 converts AC power into one or more DC power. The converted DC power is used as the reference power of the switching power supply 130 and the constant power supply 150. The constant power supply unit 150 converts the power supply 200 to a power level to be used as a standby power in the power supply device 200 from a reference power input from the AC-DC converter 110 (such as boosting or reducing pressure). ) To provide one or more constant power. The switching power supply unit 130 outputs one or more switching power supplies from the input reference power supply. The switching power supply is provided to the power supply device 200 to supply power to the processor 300 having a plurality of power levels and other ICs, and each of the one or more switching power supplies of the switching power supply unit 130 includes a capacitor. Including a discharge circuit including a and resistance, it is possible to supply a stable power to the load change by the charging circuit, and when the switching power supply of the switching power supply unit 130 is interrupted by the discharge circuit, the power stored in the charging circuit Allow discharge in time. Such charge time and discharge time will be apparent to those skilled in the art from the capacity and resistance of the capacitor. The switching power supply 130 may also receive a power supply-stop control signal from the power supply device 200 and further receive a power ON / OFF switch input. The output of the switching power supply or the output interruption of the switching power supply unit 130 may be controlled according to the power supply-stop control signal. For example, the switching power is output through the DC-DC converter included in the switching power supply unit 130 and the DC If the DC converter has an Enable terminal, the output of the switching power supply may be controlled by connecting a power supply-stop control signal to the enable terminal or supplying a reference power input to the switching power supply unit 130. A switching circuit (eg, using a transistor, relay, or photocoupler, etc.) can be configured to interrupt the circuit, and a power supply-down control signal can be configured to control the connection / disconnection of the switching circuit. Although the power supply-stop control signal has been exemplarily described as one signal line, it will be apparent that the present invention is not limited thereto.

The power supply 200 receives the constant power and one or more switching powers from the SMPS 100 and conforms to a power supply sequence for the processor 300 having a plurality of power levels from the received switching power. In addition, a plurality of powers are output so that current is not applied to the processor 300 having a plurality of power levels due to the GPIO of the IC, and the output power is provided to the processor and the other ICs. In addition, the power supply 200 may output a power supply-discontinuity control signal to control the output of the switching power supply of the SMPS 100, and in addition to the reset signal to the processor and other ICs, the processor or the like. A boot completion signal may be received from the IC indicating whether the boot has proceeded normally. The power supply device 200 will be described in detail with reference to FIGS. 3 to 5 below.

The processor 300 and other ICs having a plurality of power levels are supplied with a plurality of power levels from the power supply 200, and thus, for example, decode MPEG and convert the decoded image into an analog video signal. It plays the role of the back. The processor receives power of two or more power levels, and a plurality of power sources complying with a specification, for example, a standard such as FIG. 1, must be applied between two or more power levels. Of course, unlike FIG. 1, it is obvious that the present invention can also be applied to other types of standards (e.g., other power sources must be applied after the core power source is fully stabilized). ICs other than the processor are also supplied with power from the power supply device 200. It should be noted that the same power source can be used without generating power provided to the IC separately from the power source of the processor. This share of power eliminates the need for a separate DC-DC regulator, separate control of the DC-DC regulator, and leakage current that can be applied from other ICs (e.g. leakage through GPIO). Current) problem can be managed uniformly.

3 is a block diagram illustrating an embodiment of a power supply device 200. The example of FIG. 3 illustrates one specific example, and it will be apparent to those skilled in the art that the concept of the present invention may be easily applied to other specific design examples.

According to FIG. 3, the power supply device 200 includes a plurality of DC-DC converters 210 and a power control processor 230, and further includes a plurality of charging units 250 and a plurality of discharge units 270. It may include. The power supply device 200 of the exemplary block diagram according to FIG. 3 includes 5 V and 12 V switching power supplies from the switching power supply unit 130 of the SMPS 100 and 3.3 V from the constant power supply unit 150 of the SMPS 100. Receives a constant power of the power supply, and outputs a plurality of power generated by the plurality of DC-DC converter 210 (for example 1.2V, 2.5V, 3.3V, 5V) as the output power of the power supply device 200. . In addition, the power supply 200 outputs a power supply stop control signal to the SMPS 100 by the power control processor 230, and outputs a reset signal to the processor 300 having a plurality of power levels or / and other ICs. And a boot completion signal from a processor 300 or / or other IC having a plurality of power levels.

The DC-DC converter 210 outputs from the input power to a predetermined output power according to the signal control of the enable terminal. In the example of FIG. 3, each of the DC-DC converters 210 receives a 5 V input and outputs 3.3 V, 2.5 V, and 1.2 V, and receives a 12 V power supply level and outputs 5 V. FIG. When the input of the enable terminal is disabled (for example, a '0' level), the DC-DC converter 210 stops supplying output power using an internal switching circuit.

The power control processor 230 may be booted by a constant power source. Preferably, the power control processor 230 is a microcomputer type processor that is directly bootable by applying a constant power source because an internal reset circuit of 8 bit or 16 bit is built in. The power control processor 230 outputs one or more enable signals to control the power output of the plurality of DC-DC converters 210 according to the power supply order in the determined basic time order, and the switching power supply of the SMPS 100 is controlled. Output a power down control signal to control the output. In addition, the power control processor 230 may output a reset signal to control the reset signal in conjunction with the power supply order, and also receive a boot completion signal from the processor 300 having a plurality of power levels and other ICs. For example, when the booting is not completed normally, the enable signal and the reset signal may be controlled in a new time order to enable rebooting. The enable signal output from the power control processor 230 may be output as separate signal lines as the number of the plurality of DC-DC converters 210, and may be output to at least two of the plurality of DC-DC converters 210. The same signal line may be used for the same. A detailed configuration and flowchart of the power control processor 230 will be described below with reference to FIGS. 4 and 5.

The charging unit 250 is connected to the output power of the DC-DC converter 210, so that the power output from the DC-DC converter 210 can be stably supplied to a specific power level irrespective of a change in external load. The charging unit 250 may include an electrolytic capacitor or a tantalum capacitor, and the charging capacity of the capacitor may vary depending on a load amount connected to the output power and a variable power range of the power level. For example, when the power of a specific power level connected through the charging unit 250 is provided only to the processor 300 having a plurality of power levels, the charging capacity may be calculated based on the load required by the processor. If it is also available in other ICs, the charge capacity can be calculated including the load required by the other IC. Accordingly, the charging capacity of each charging unit 250 of the plurality of charging units 250 is preferably configured to be the same, but may have different charging capacities.

The discharge unit 270 is connected to the output power of the DC-DC converter 210 to discharge the power charged in the charging unit 250 within a specific time when the supply of power output from the DC-DC converter 210 is stopped. Do it. For example, it may be designed to discharge the power charged in the charging unit 250 to less than a predetermined power level within 1 second. Such a design will be obvious to those skilled in the art, so detailed description thereof will be omitted. The discharge unit 270 may include a resistor. When the discharge unit 270 fails to boot due to failure to meet the processor standard, for example, the processor 300 having a plurality of power levels is latched up. In the event of a boot failure, for example, the power is quickly removed, eliminating the generated latchup and allowing a reboot in a new changed time sequence.

4 is a detailed block diagram of the power control processor 230.

According to FIG. 4, the power control processor 230 includes an I / O interface unit 233, an ADC unit 235, a memory unit 237, and a CPU core 239 connected to a system bus or a control bus, and includes a reset unit. 231 may be further included. The power control processor 230 preferably uses a single power source or a bootable processor regardless of the power supply order even if a plurality of power sources are used. For example, a general-purpose 8-bit or 16-bit microcomputer that is industrially used. May be a processor of the type.

The reset unit 231 automatically generates a reset signal at a time when the constant power provided to the power control processor 230 starts to be applied (for example, from a time when the power supply level is abnormal), and generates the reset signal. Provide it to the block to proceed with the initialization. In response to the reset signal, the CPU core 239 and / or the I / O interface unit 233, the ADC unit 235, and the memory unit 237 transition to an initial state.

The I / O interface unit 233 stores data received through the I / O port provided by the power control processor 230 through a register, etc., and provides the received data to the CPU core 239, and receives the data from the CPU core 239. The data can be output through the I / O port. A time-controlled reset generated from the CPU core 239 and output through the I / O port via the I / O interface 233 and output from the CPU core 239. Signal may be output for use as a reset signal for a processor 300 having multiple power levels and / or other ICs, or boot-up completion signal from a processor 300 having multiple power levels and / or other ICs Can be received and delivered to the CPU core 239. Of course, such a control signal may be received through a communication method other than the I / O interface unit 233.

The ADC unit 235 receives an analog signal, converts it into a digital signal, for example, an 8-bit or 16-bit digital signal, and provides the converted digital signal for use by the CPU core 239. The ADC unit 235 may receive each or at least two output powers of the plurality of DC-DC converters 210. By converting the received output power into a digital signal, the CPU core 239 detects a change in the output power output from the plurality of DC-DC converters 210 to determine whether it meets the requirements required by the power supply order standard. If the requirement is not satisfied, the enable signal for controlling the output power of the DC-DC converter 210 may be dynamically controlled to control to meet the requirement.

The memory unit 237 stores a program to be driven in the CPU core 239, and may also include data to be used in the program. The memory unit 237 may include a nonvolatile memory (eg, EEPROM) and may further include a volatile memory. Although the memory unit 237 is exemplarily described as a component of the power control processor 230, it is apparent that the memory unit 237 may be configured as a separate IC outside the power control processor 230. something to do. The data stored in the memory unit 237 includes a default timing sequence for controlling an enable signal of a processor 300 having a plurality of power levels and / or a plurality of DC-DC converters 210 for an IC. sequence), and the default time sequence also contains one or more other time sequences to be used if the boot fails. It will be apparent that the time sequence may also include an application time point and a release time point of the power-down control signal, and this time order may be implemented as fixed program code in the program itself in the CPU core 239. .

The basic time sequence is a set time sequence that is highly likely to succeed in booting without latch-up or the like in the exemplary electronic device of FIG. 2, or has a history of successful booting. In general, it is advantageous for the electronic device to boot using various time sequences, rather than applying the same time sequence according to variations of components in the electronic device. For example, when booting using one time sequence, the time sequence that fails to boot in a specific electronic device is likely to fail even when the same time sequence is booted again. This is because the deviations of the components are already fixed in the electronic device. Therefore, if booting fails in one time sequence, booting is performed using a different time sequence. If the booting is successful due to another time sequence, the successful time sequence is set in the memory unit 237 as the default time sequence. It is preferable to boot using the time sequence.

The basic time sequence used for the first time in the production of the electronic device equipped with the power supply device 200 of the present invention is calculated in consideration of the standard charging capacity of the charging unit 250 or in addition to the enable signal of the DC-DC converter 210. The calculation is made considering the time point at which the power is output. Of course, other calculations may be taken into account. For example, the charging capacity of the plurality of charging units 250 may vary the amount of change in the load of each output power and the variable range of the output power (for example, the variable range of 1.2 V input power as the input power of the processor is 1.08 V to 1.28 V). The 3.3V input power is calculated in consideration of the normal operating range of 3.1 V to 3.5 V, which is defined in the processor specification), and the higher the load of the output power or the narrower the variable range of the power level, the higher the charge capacity This requires a capacitor that can charge higher amounts. In this way, the charging capacity of each charging unit 250 may be calculated, and the charging capacity may be partially adjusted to meet the standard representing the power supply order of the processor 300 having the plurality of power levels. The charging capacity of the plurality of charging units 250 is advantageously the same, but may vary according to the reasons described above. The start time of the enable signal of each DC-DC converter 210 is calculated by calculating the charging time according to the corresponding charging capacity and the time from the enable signal of the DC-DC converter 210 to the output of the power. Can be determined to meet the standard, and the determined starting time points can be determined in one initial base time order. Of course, this initial basic time sequence may be measured by measuring the change of the output terminal of the DC-DC converter 210 in a plurality of electronic devices as a measured value or the charging time and power supply sequence that the developer clearly understands. It can be calculated using the standard of. On the other hand, it may further include a plurality of different time sequences different from the first basic time sequence, which may be distributed according to the deviation of the electronic device calculated using the deviation of components mounted in the electronic device. For example, a specific location on a Gaussian distribution may be calculated as a target. That is, all of the components have a deviation, and the deviation of the components may be used to calculate another time sequence of the electronic device. In particular, the deviation of a particular part may be more inconsistent with the power supply order standard than the deviation of that particular part, and the calculation of another time sequence may be more efficient by calculating a different time sequence with particular consideration of the deviation of such a part. Can be. For example, the charging capacity that can be used in the charging unit 250 may have a deviation of up to +/- 20% depending on the type of component. In addition, the processor 300 having a plurality of power levels and other ICs also have variations in load. One or more other time sequences can be configured to account for these deviations, especially if the other time sequences have the highest probability of being on the initial base time sequence, which would cause the output power of the DC-DC converter 210 to fail to meet the standards of the powering sequence. The enable signal may be adjusted to adjust the time for the charging unit 250. For example, the charging capacity of the charging unit 250 of the DC-DC converter 210 is larger than that of the other charging unit 250 when the output of the 1.2 V DC-DC converter 210 is related to other power outputs. In order to comply with the standard as shown in FIG. 1, charging must be started before other power sources. This is because the longer the charging time is used for the capacitor having a larger charge capacity, and the larger the deviation is, the larger the capacitor is used, which may cause a problem of non-compliance with the standard as shown in FIG. Therefore, another basic time sequence may be configured to change the application timing of the enable signal centered on the enable signal of the corresponding 1.2 V DC-DC converter 210. By configuring a plurality of basic time sequences in consideration of the deviation of the components of the electronic device and storing them in a memory, even if the processor 300 or other ICs having a plurality of power levels in a specific time sequence fails to boot, It can be configured to boot using the default time sequence of has the effect of significantly lowering the defective rate of the electronic device. Or alternatively driven by the CPU core 239 to compare in real time the level of the output power of each DC-DC converter 210 input from the ADC unit 235 without using multiple time sequences stored in memory. Program is configured so that each output power level violates or may be violated between the output power according to the standard (for example, if it is determined that the standard has been violated that the 1.2 V power must be lower than the other power supply). The enable signal of the DC-DC converter 210 may be controlled repeatedly by outputting 1.2 V) to control the enable signal of the DC-DC converter 210 in real time.

The CPU core 239 is configured to load a program stored in the memory unit 237 to control each block in the power control processor 230 and to control each block according to the program. An embodiment of a program executed in the CPU core 239 will be described in detail with reference to FIG. 5.

FIG. 5 is a signal chart illustrating each signal, in chronological order, being controlled by the CPU core 239 in the power control processor 230 or used as an input. The signal chart of FIG. 5 illustrates control according to an input time and an input of an output signal of each power control processor 230 using the embodiment of FIG. 3 using the power supply sequence of FIG. 1 as one exemplary standard. One drawing. Therefore, it will be apparent to those skilled in the art that the spirit of the present invention may be applied in accordance with other power supply order or other exemplary standards.

5 illustrates control signals output or input from the power control processor 230 on the vertical axis, and changes in the respective control signals over time on the horizontal axis.

According to FIG. 5, after the constant power is applied from the SMPS 100 and the power control processor 230 boots using the memory and loads the program, the SMPS 100 uses the power supply-stop control signal. Supply power. Also, the enable control signal may be applied to the enable signal on the time chart of FIG. 5 so that the charging unit 250 connected to each DC-DC converter 210 may be charged. The SMPS 100 is applied with the switching power supply, and additionally, the enable control signal is applied to charge the charging unit 250 of the SMPS 100 charging circuit or the DC-DC converter 210.

② After a predetermined time, the power supply-stop control signal is controlled to stop the supply of the switching power supply of the SMPS 100 by using the power supply-stop control signal. In addition, if the enable control signal of the DC-DC converter 210 is applied in the previous step, the enable control signal is controlled again so that the output power of the DC-DC converter 210 is not supplied to the SMPS. The discharge circuit 100 is discharged by the discharge circuit 270 or the discharge unit 270 of the DC-DC converter 210.

③ Then, the power supply-stop control signal is used again after a discharge time (for example, 3 seconds) calculated to sufficiently discharge power to the charging circuit 250 of the SMPS 100 or the charging unit 250 connected to the DC-DC converter 210. SMPS 100 to supply power. Steps ② and ③ may be repeatedly performed one or more times. The reason for supplying power to the charging circuit or the charging unit 250 of the SMPS 100 first and then discharging again is to supply power again, for example, the charging component constituting the charging circuit or the charging unit 250 of the SMPS 100. Based on the characteristics of the capacitor. For example, if the capacitor is completely discharged (e.g. no external AC power is supplied), the capacitor will not charge the input power first applied for charging for a certain period of time after full discharge. There is a characteristic to bypass. This characteristic allows unwanted output power to appear at a low level for some time and is one example of inrush current. This is due to the physical properties of the capacitor (e.g., in case of a complete discharge, the capacitor can form a short circuit or an open circuit for a certain period of time after the power is applied). For example, the core power supply of the processor may be recognized as a voltage above a threshold voltage that can operate, causing a malfunction. This inrush current or voltage may appear from the first power supply to the output power of the switching power supply 130 or the output power of the DC-DC converter 210 for a predetermined time. On the other hand, by supplying the power more than two times, in the first power supply, although inrush current flows, it is supplied to the processor 300 and other ICs having multiple power levels, which may violate the standard of power supply order or cause malfunction. However, in the second power supply after the first power supply, such inrush current can be prevented from being supplied to the processor 300 and other ICs having a plurality of power levels. This is because when the charging circuit of the SMPS 100 or the capacitor of the charging unit 250 discharges, it discharges rapidly at the initial stage of discharge, but slowly discharges over time (eg 1 / log Discharge function in the form of a function, etc., the remaining capacity remains after a certain period of discharge time and discharges below a certain power reference (for example, 0.2 V or less), and then, when a second or later power supply is applied. Since the power supply is used for charging the charging circuit of the SMPS 100 or the charging unit 250 and can prevent the output of unwanted inrush current, the standard of power supply order of a processor or other IC having a plurality of power levels. It can make it possible to comply with and to prevent malfunctions.

④ After the switching power supplied from the SMPS 100 is stabilized, the enable signal of each DC-DC converter 210 is output by outputting the enable signal of each DC-DC converter 210 in the order set in the basic time order to the memory. Controls the start time of output power. For example, the charging capacity of the charging unit 250 connected to the 1.2 V output power is greater than that of the other charging units 250. First, the enable signal of the DC-DC converter 210 that outputs 1.2 V is first applied and then constant. After the time, the enable signal of the 3.3-V DC-DC converter 210 is applied, and again after the predetermined time, the enable signal of the DC-DC converter 210 is applied. Finally, the enable signal of the 5 V DC-DC converter 210 is applied. Of course, if the output of the DC-DC converter 210 of 5 V is not connected to the processor 300 having a plurality of power levels through GPIO, etc., unlike the other power supply to enable the enable signal at a free time Can be. For example, the 3.3 V enable signal can be used as one signal line as the 5 V enable signal. The output power of the DC-DC converter 210 not only supplies to the processor 300 having a plurality of power levels, but also can be simultaneously supplied to other ICs, so that other ICs before the processor is stabilized according to the standard from other ICs. It is possible to reduce the leakage current imparted through GPIO.

⑤ Then, the reset signal is released to allow the processor 300 having a plurality of power levels to boot.

(6) After the reset signal is released, the controller waits for a predetermined time (for example, 5 seconds) and receives a boot completion signal from the processor 300 having a plurality of power levels. When the boot completion signal is normally received, the processor boots normally and performs a given function according to a program mounted on the processor.

⑦ If the booting completion signal is not received or if the time set by the timer has passed, reset the reset signal and control the enable signal to stop the output power of the plurality of DC-DC converters 210. Steps 2 to 6 or steps 4 to 6 are executed using different time sequences stored in the memory. If the booting is successful in other time sequences, the other time sequences are stored in the memory as the default time sequence. The other time sequence in this example reflects the deviation of the charging capacity of the charging unit 250 connected to the 1.2 V output power which may be in violation of the standard of the power supply order. An example would be to reduce the time interval, and if another output power is likely to violate the standard of the power supply sequence, then the other output power may be adjusted in a way that allows for compliance with the standard, taking into account component deviations. Will be set. That is, for example, when 1.2 V is designed to be powered higher than the other 3.3 V or 2.5 V at the level of approximately 0 to 0.4 V according to the basic time sequence calculated or measured from the initially set standard charging capacity, and When the charging capacity of the charging unit 250 connected to the 1.2 V output power mounted in the electronic device has a deviation of -20%, the charging speed becomes even faster, so that the power supply sequence shown in FIG. 1 is not satisfied, and in this case, 1.2 V By delaying the timing of the enable signal of the output power supply and adjusting it closer to the timing of the enable signal of the 3.3V output power, the problem caused by the failure to comply with the power supply order standard can be solved.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. The present invention is not limited to the drawings.

100: SMPS 110: AC-DC converter
130: switching power supply 150: always power supply
200: power supply 210: DC-DC converter
230: power control processor 231: reset unit
233: I / O interface unit 235: ADC unit
237: memory part 239: CPU core
250: charging unit 270: discharging unit
300: processor with multiple power levels

Claims (7)

A power supply for a processor with multiple power levels,
A plurality of DC-DC converters, each of the plurality of DC-DC converters outputs power according to control of an enable signal for each of the plurality of DC-DC converters from an input power level to an output power level of a specified level. A plurality of DC-DC converters; And
Outputs a power supply-stop control signal for supplying or interrupting power to input power of the plurality of DC-DC converters, and after power is supplied to input power of the plurality of DC-DC converters, the plurality of DC- A power control processor that outputs a plurality of enable signals connected to each of the DC converters.
≪ / RTI &
The power control processor controls the power supply-stop control signal so that power is supplied to input power of the plurality of DC-DC converters, and the power is supplied to input power of the plurality of DC-DC converters. Outputting the plurality of enable signals for the DC-DC converters to the plurality of DC-DC converters according to a specified time sequence,
Power supply. The method of claim 1,
The designated time sequence is a basic time sequence stored and set in the power control processor.
The power control processor checks whether the booting is normally started from the processor having the plurality of power levels from a boot completion signal or the elapsed time, and when the startup is not normal, the plurality of power levels. Outputting the plurality of enable signals according to a second time sequence different from the basic time sequence to reinitialize a processor having:
Power supply. The method of claim 2,
The power control processor sets the second time sequence to the basic time sequence when it is confirmed from the boot completion signal that the startup is normal after outputting the plurality of enable signals according to the second time sequence. doing,
Power supply. The method of claim 1,
The power control processor may receive each of the output powers of the plurality of DC-DC converters, and determine the level of each of the received output powers.
Power supply. A power supply method for a processor having multiple power levels,
i) powering input power of the plurality of DC-DC converters;
ii) stopping power supply to input power of the plurality of DC-DC converters;
iii) re-powering input power of the plurality of DC-DC converters; And
iv) a power control processor outputting at least one enable signal to control a power output of the plurality of DC-DC converters,
Power supply method. 6. The method of claim 5,
ii) discontinuing power supply to input power of the plurality of DC-DC converters, and iii) re-powering input power of the plurality of DC-DC converters is performed one or more times. doing,
Power supply method. The method according to claim 6,
iv) the power control processor outputting at least one enable signal to control the power output of the plurality of DC-DC converters,
Outputting the at least one enable signal for the plurality of DC-DC converters to the plurality of DC-DC converters according to a first time sequence that is a default timing sequence;
Confirming that the processor is normally booted from the plurality of power levels;
Outputting the at least one enable signal in a second time order to reinitialize the processor with the plurality of power levels if the startup is found to be abnormal.
Power supply method.

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