KR101206511B1 - Compact analog phase shifter - Google Patents

Abstract

The present invention relates to a small analog phase shifter, comprising a pair of capacitors connected in series, a first inductor connected in parallel to the pair of capacitors, and a node between the pair of capacitors and a ground potential line connected to each other. The structure provided with the all-pass network provided with a 2nd inductor is provided.
By using such a small analog phase shifter, the present invention designs and manufactures a small phase shifter using an all-pass network at 2 GHz, and integrates a bias circuit using a new type of inductor to construct a small phase shifter. The nonlinearity of the varactor, which is a phase variable element, can be improved to have a linear phase shift characteristic with respect to the voltage.

Description

Compact Analog Phase Shifter {COMPACT ANALOG PHASE SHIFTER}

The present invention relates to a small analog phase shifter, and more particularly, to a small analog phase shifter having a linear phase shift characteristic with respect to voltage.

The phase shifter is a circuit that changes the pass phase of the transfer characteristic with low loss in the desired frequency band. Phase shifters are classified into digital and analog types according to the method of phase shift.

The digital type is a circuit for generating discrete phase shifts in bits and is widely used for phased array antennas and radars. Discrete phase shifters use PIN diodes or Schottky diodes, which are switching devices, and combine them with hybrids or load lines.

On the other hand, the analog phase shifter uses a varactor diode having a variable capacitance to voltage, and has a continuous phase shift. Conventional analog phase shifter implementations combine varactor diodes with hybrid or load lines, similar to discrete phase shifters. However, in the 2 GHz band, one wavelength is equivalent to 15 cm, and hybrid or load line circuits are constructed using 1/4 wavelength transmission lines having a length of about 40 mm.

Therefore, the size of the phase shifter using a hybrid or a load line circuit is expected to be at least 40mm × 40mm or more, which makes it difficult to miniaturize 5 mm × 5 mm or less.

In terms of the linearity of the phase shifter, it depends on its application. In the case of the voltage-controlled oscillator using the proposed phase shifter, it has been announced that the adjustment characteristic of the phase shifter is the same as the frequency adjustment characteristic of the oscillator.

That is, when the oscillation frequency is f, the phase shift value is θ, and the group delay of the resonator is t _d , the oscillation frequency is expressed as f = Cθ / t _d .

At this time, since t _d can be seen as a constant, the phase adjustment characteristic according to the voltage appears as the oscillation frequency voltage adjustment characteristic as it is.

Where C represents the proportionality constant.

In particular, an oscillator having such a linear frequency adjustment provides an advantage of not requiring a separate linearization circuit when used in a frequency modulated continuous wave (FMCW) radar frequency modulation circuit. Therefore, a phase shifter intended for application to such an oscillator must have linear phase adjustment characteristics.

Therefore, the linear phase shifter is the core of this oscillation mechanism.

For example, an all-pass network is considered suitable for analog phase shifters having linear phase shifting characteristics of 5 mm x 5 mm or less.

All-pass networks can easily design input impedances of 50 ohms within the frequency band and have a constant insertion loss due to broadband matching. In addition, the all-pass network can be made compact by using a flat circuit.

Meanwhile, the unit phase shifter has a phase shift of 120 °, and two or more all-pass phase shifters can be connected in series to design a phase shifter of 360 ° or more.

Reactance variable devices used in such phase shifters have been presented with various phase shifters using varactor diodes, field effect transistors (FETs), ferro-electric materials, and the like.

However, in general, most of phase shifters designed using two or more all-pass phase shifters have a problem in which nonlinearity occurs during phase shift due to nonlinearity of the reactance variable element.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a small analog phase shifter having a linear phase shift characteristic with respect to voltage.

Another object of the present invention is to provide a small analog phase shifter which linearizes the capacitance with respect to voltage to improve the nonlinearity of the phase shifter.

According to a feature of the present invention for achieving the above object, the present invention provides a pair of capacitors connected in series, a first inductor connected in parallel to the pair of capacitors, a node between the pair of capacitors And an all-pass network having a second inductor connected between and the base potential line, inductances L ₁ and L ₂ of the first and second inductors are calculated by Equation 1.

L ₁ = 2L ₀ , L ₂ = 1 / 2L ₀ ............... [Equation 1]

Where L ₀ is the inductance threshold set between 0.1 and 10 nH.

The all-pass network is characterized in that the return loss (S ₁₁ ) is '0' and the insertion loss (S ₂₁ ) has an all-pass characteristic that satisfies '1'.

The return loss (S ₁₁ ) and insertion loss (S21) is the return loss (S ₁₁ ) = 0, insertion loss (S ₂₁ ) = 1 when the frequency ω ₀ = (L ₀ C ₁ ) ^-1/2 It is characterized by being satisfied.

The pair of capacitors are each replaced with varactor diodes,

A reverse voltage is applied to the varactor diode.

A series capacitor is connected between the varactor diode and the base potential line so as to reduce the overall phase shift and have linearity.

The all-pass network includes an upper path and a lower path, wherein the upper path includes a bias resistor, and the lower path includes a grounded second inductor, the varactor diode, and a series capacitor.

The lower path may further include a grounding resistor.

The first and second inductors are characterized in that the flat circuit.

The second inductor is a planar spiral inductor, and the series capacitor is a single layer capacitor.

The second inductor includes two resistors having an upper resistance pad connected to a central portion thereof, a first air bridge connecting a lower portion of one resistance pad and an input port, a second air bridge connecting the upper resistance pad, and an external device. The conductor pads are characterized by consisting of vias.

As described above, the present invention can design and manufacture a small phase shifter using an all-pass network at 2 GHz, and use a new type of inductor to construct a bias circuit in an integrated structure to construct a small phase shifter. .

In addition, the present invention can improve the nonlinearity of the varactor, which is a phase variable element, to have a linear phase shift characteristic with respect to voltage.

To this end, the present invention connects a series capacitor to a varactor diode to linearize the capacitance over voltage to improve the nonlinearity of the phase shifter.

According to the experimental results, the present invention slightly reduced the phase change amount to about 79 °, and showed linear phase shift characteristics as expected in the design.

1 is a circuit diagram of a small analog phase shifter according to a preferred embodiment of the present invention.
2A and 2B are operational state diagrams of the all-pass network phase shifter shown in FIG.
3 is a graph showing the change of phase and reflection coefficient according to C ₁ of the all-pass network at 2 GHz.
4A is a nonlinear characteristic simulation circuit diagram of a varactor diode.
FIG. 4B is a circuit diagram in which a series capacitor is added to the circuit shown in FIG. 4A, and FIG. 4C is a capacitance graph according to voltage.
FIG. 5 is a circuit diagram of C ₁ replaced with FIG. 4B in the all-pass network circuit of FIG. _1. FIG.
FIG. 6 is a graph comparing the results of an improved phase shifter simulation with an all-pass circuit phase shifter using only varactor diodes. FIG.
FIG. 7A is a circuit diagram modified from the phase shifter circuit shown in FIG. 5; FIG.
Figure 7b is a block diagram showing an HFSS simulation structure.
8A is a bias circuit diagram composed of an inductor corresponding to the upper path and R ₁ in FIG. 5, FIG. 8B is a schematic diagram of a general spiral inductor, and FIG. 8C is a schematic diagram of an inductor according to the present invention.
9A is an EM simulation circuit diagram.
9B is a graph of simulation results of S-parameters obtained after DC bias at 0, 3, 5 V of phase shifter.
Figure 9c is a graph showing the change in phase when the voltage is continuously changed to 0 ~ 5V.
10 is a block diagram of a small analog phase shifter manufactured in accordance with the present invention.
11A to 11D illustrate a measuring method using a wafer probe.
12A to 12C are graphs of measurement results of reflection loss S ₁₁ and insertion loss S _{21 according} to voltage Vt.
13 is a graph of measured and simulated phase change with supply voltage.

Hereinafter, a small analog phase shifter according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1. Whole pass circuit Mans  Phase shifter

1 is a circuit diagram of an all-pass network phase shifter according to the present invention, and FIGS. 2A and 2B are operational state diagrams of the all-pass network phase shifter shown in FIG.

The all-pass network exhibits all-pass characteristics satisfying return loss (S ₁₁ ) = 0 and insertion loss (S ₂₁ ) = 1 in a desired frequency band, and are configured as shown in FIG. 1.

That is, a pair of capacitors C1 are connected in series between the input terminal In and the output terminal Out, and the first inductor L ₁ is connected to the first node N in parallel with the pair of capacitors C ₁ . ₁ ) and the second node (N ₂ ), the second inductor (L ₂ ) is connected between the third node (N ₃ ) and the ground potential line.

Here, the first and second inductances (L _1, L ₂₎ are as follows: Equation (1).

Here, L ₀ is an appropriately set inductance reference value that can be implemented, and has a value of 0.1 to 10 nH. Under this condition, in order to confirm the global pass characteristic of the circuit shown in FIG. 1, the circuit board was decomposed into odd and even modes in FIGS. 2A and 2B.

In the even mode shown in FIG. 2A, the center point of symmetry is open so that L ₁ has no contribution and parallel decomposition leaves 2L ₂ .

In the radix mode shown in FIG. 2B, the center point of symmetry is shorted so that L ₂ has no contribution, leaving L _1/2 decomposed in series. Only one C ₁ is included in both circuits. In this simplified circuit, the reflection coefficient for the reference impedance Z ₀ is expressed by Equations 2 and 3 below.

S ₁₁ and S ₂₁ are obtained using the even mode reflection coefficient Γ _ε and the odd mode reflection coefficient Γ ₀ obtained by Equations 2 and 3, as shown in Equations 4 and 5 below.

When the frequency is ω ₀ = (L ₀ C ₁ ) ^-1/2 , S ₁₁ = 0 and S ₂₁ = 1 in Equations 4 and 5 are satisfied.

When viewed as a transmission line, the characteristic impedance is expressed by Equation 6 below.

Therefore, by substituting ω ₀ = (L ₀ C ₁ ) ^-1/2 and center frequency 2 GHz and Z ₀ = 50 ohm in Equation 6, L ₀ and C ₁ can be obtained. Substitution determines the L ₁ and L ₂ values, which are listed in Table 1 below.

Table 1 is a table of individual device design values for the all-pass network at 2 GHz.

By varying C ₁ in the all-pass network of FIG. 1, it is possible to easily change the phase of S ₂₁ in Equation 5. The result of varying the value of C ₁ from 0.5 to 3.5 pF around 1.6 pF is shown in FIG. 3 with the size of S ₂₁ and S ₁₁ , which is a reflection coefficient.

3 is a graph showing a change in phase and reflection coefficient according to C ₁ of the all-pass network at 2 GHz.

C ₁ a having a maximum matching in a 1.6 pF, as the area S ₁₁ of the C ₁ is to meet a 10 dB shown in Figure 3, is the 0.75 ~ 3.25 pF. In this region, the total phase shift is up to 150 ° relative to the phase at 0.75 pF.

As a phase shifting device, C ₁ having a voltage range of 0.75 to 3.25 pF in an arbitrary voltage varying range, and a varactor diode as a voltage varying device having 1 to 3.2 pF at 0 to 5V were most suitable.

2. Linear Global Pass Through network  Phase shifter design

In the all-pass network of FIG. 1, when C ₁ is changed to a varactor diode and a reverse voltage is applied to the diode, the phase changes according to the diode characteristics. The varactor diode can adjust the capacitance generated at the diode junction to reverse voltage, but nonlinear characteristics show different capacitance change rates at low and high voltages.

FIG. 4A is a circuit diagram of a nonlinear characteristic simulation of a varactor diode, FIG. 4B is a circuit diagram of a series capacitor added to the circuit of FIG. 4A, and FIG. 4C is a capacitance graph according to voltage.

In order to confirm the nonlinear characteristics of the capacitance change rate, the circuit was configured as shown in FIG. 4A using the circuit model of the varactor diode, and the reflection coefficient seen from the RF port was simulated using an ADS (Advanced Design System).

From this result, the capacitance can be obtained from the RF of the reverse biased diode. The calculated results are shown in solid lines in FIG. 4C. At 2 GHz, the capacitance of the varactor diode is near hyperbolic with respect to the reverse voltage, which means that the capacitance to the voltage changes nonlinearly.

In order to improve the nonlinearity with respect to the voltage of the diode, as shown in FIG. 4B, a series capacitor (C _series ) was added to the varactor diode to configure a circuit. The value of the series capacitor was determined to be 4 pF greater than the diode's capacitance of 1 to 3.2 pF in order to reduce nonlinearity and obtain sufficient phase shift. The change in capacitance with respect to the voltage of the varactor diode to which the series capacitor is connected is shown by a dotted line in FIG. 4C.

Compared to the single diode indicated by the solid line, the change in total capacitance decreases from 0.9 to 2 pF, but as the slope difference at 0 V and 5 V decreases, the result is a linear capacitance change.

FIG. 5 is a circuit diagram of C ₁ replaced with FIG. 4B in the all-pass network circuit of FIG. 1.

As shown in FIG. 5, the upper path includes bias resistors R ₁ for L ₁ and RF isolation, and the lower path includes a grounded L ₂ and FIG. 4B.

A bias is applied to the two diode cathodes using a 1.2 kohm resistor (R1), respectively, and a resistor having the same value as the resistor for the bias for DC ground is connected to the anode of the varactor. Capacitor C ₂ connected in series with the circuit of FIG. 4B reduces the overall capacitance C _Tot . As a result, the inductance L ₁ , L ₂ is changed.

Table 2 shows a table of device design values (C _Tot is the capacitance of a varactor diode having a series C ₂₎ of a phase shifter with improved linearity. The capacitance and inductance values of the resistors and capacitors shown in FIG. 5 are described. .

Looking at Table 2, the overall phase shift is reduced to 80 ° by a rather small C _Tot compared to Table 1 with a maximum phase shift of 150 °.

6 is a graph comparing the results of an improved phase shifter simulation with an all-pass network phase shifter using only a varactor diode.

That is, FIG. 6 shows the phase change with respect to the voltage of the all-pass network phase shifter of Table 1 and the phase shifter of FIG. 5 of Table 2 using C ₁ as a varactor diode model.

In FIG. 6, solid lines represent simulation results, and a dotted line is a straight line having an inclination at an inclination near 0 V of each phase shifter. The closer to this straight line, the more linear the phase shifter. A single diode phase shifter is far from a straight line, while a phase shifter using a diode connected with a series capacitor is close to a straight line. Through this, it was confirmed that the phase shifter circuit shown in FIG. 5 has excellent linearity with respect to voltage.

3. Small phase shifter configuration

The phase shifter shown in FIG. 5 is divided into an upper path and a lower path.

FIG. 7A shows the value of the inductor, which is a planar circuit included in each path of the phase shifter shown in FIG. 5, through EM simulation, and is designed when a single layer capacitor and a bias resistor are combined. FIG. 7B is a schematic diagram illustrating an HFSS simulation structure in which a value is modified to give a phase shifter characteristic.

As shown in FIG. 7A, the lower path includes a varactor, which is a reactance variable element, a capacitor for improving linearity, and a resistor for grounding. In order to consider the inductors, single layer capacitors, and parasitic components by wire bonding, which are planar circuits, the 3D high-performance electromagnetic field simulation software High Frequency Structure Simulator (HFSS) is used. Designed in detail.

The value obtained here is somewhat different from the design of a single device for a planar inductor. This is presumably due to parasitic components of the bonding wires and other conductor patterns. Corresponding to the single-layer capacitor value, the length of the inductor was adjusted so that the value of the desired L ₂ inductor is shown in Table 2. In this simulation, the varactor diode is excluded in FIG. 7B, where the characteristics of the varactor cannot be considered. A passive circuit in the lower path, where L ₂ is a grounded flat spiral inductor and C ₂ is a single layer capacitor. This single layer capacitor is a small flat capacitor that can be configured with HFSS using the dielectric information and size provided by the manufacturer. HFSS simulation was performed by connecting two single-layer capacitors and inductors with gold wires. The values of C ₂ are checked using the S-parameters obtained here, and the values of L ₂ are adjusted to Table 2.

8A is a bias circuit diagram composed of an inductor corresponding to the upper path and R ₁ in FIG. 5, FIG. 8B is a schematic diagram of a general spiral inductor, and FIG. 8C is a schematic diagram of an inductor according to the present invention.

An inductor with a resistance equal to 1.2 kohms should have a relatively large value of 14.6 nH.

The typical spiral inductor shown in FIG. 8B has a size of 1.8 mm x 1.8 mm and has an asymmetrical structure by connecting an output from an inner wound conductor to an air bridge.

On the other hand, the inductor according to the present invention has a structure in which a bias circuit is coupled, as shown in FIG. 8C.

That is, the inductor according to the present invention is first selected to 100 ohm / square in order to reduce the size of the plane resistance for the bias, and is designed to 0.05 mm × 0.98 mm to be 1.2 kohm. Place two resistors in the center of the inductor and connect the upper resistor pad of each resistor. The conductors are wound three times in the direction of increasing the rectangular spiral structure starting from the conductor pad in the lower left, with a minimum clearance of 0.02 mm in the outward direction.

In addition, an input / output (In, Out) port is disposed under the inductor to facilitate connection with the lower path shown in FIG. 7. Connect to the right resistor lower conductor pad and air bridge for bias at the out port. To apply reverse bias to the varactor from the input (In) port, use an air bridge from the lower left resistor pad to the input (In) port.

At this time, the difference in the length of the air bridge occurs, and to compensate for this, the conductor length at the input / output port is adjusted.

A phase shifter on the upper resistor pad is connected by an air bridge to supply a DC bias from the outer top.

Vias are provided on the external conductor pad for verification through simulation of the bias circuit.

Fully isolate the port to reduce coupling between input and output. The width and height of 1.5 mm x 1.4 mm were reduced. The area of the inductor can be reduced by 40%.

Table 3 is a characteristic table of the inductor shown in FIGS. 8B and 8C.

The values shown in Table 3 are converted to Y parameters using the measured S-parameters and converted into π equivalent models, where (-Y ₂₁ ) is replaced by L ₂₁ , and (Y ₁₁ + Y ₂₁ ) is C ₁₁ . (Y ₂₂ + Y ₂₁ ) changes to C ₂ 2.

The capacitance generated here is assumed to be the capacitance generated at the inductor input and output. In FIG. 8B, the inductor value has a design value, but capacitance asymmetrically occurs at the input and the output.

On the other hand, in FIG. 8C, since parasitic components C ₁₁ and C ₂₂ are close to zero, there is no problem in connection with the lower circuit.

4. Final Simulation Results

Using the EM simulation, the device needed for phase shifter was designed by dividing it into upper and lower sides.

FIG. 9A is an EM simulation circuit diagram, FIG. 9B is a simulation result graph of an S-parameter obtained after DC biasing at 0, 3, and 5 V of a phase shifter, and FIG. 9C is 0 to 5 V when the voltage is continuously changed. This graph shows the change of phase.

In the present invention, a single layer capacitor, a spiral inductor and parasitic components that are hard to predict circuits are included in the simulation through the circuit configuration as shown in FIG. 9A. This reduces the error with the actual circuit. The two-port simulation results from the upper path and the two-port simulation results from the lower path are included in the circuit simulation using data items of ADS. The resistor circuit for bias was calculated and included, and the measurement result provided by the manufacturer of the broadband capacitor was inputted. This capacitor is used at the DC bias input stage, as shown in FIG. 9A.

The upper and lower EM simulation results are used to optimize the device values of the phase shifter.

As a result, some circuits were modified to be similar to Table 2 except for C ₂ , but it was confirmed that C ₂ was optimized at 5.1 pF. It is thought to be due to the inductance and other parasitic components of the bonding wire used to connect the single-layer capacitor and diode anode.

The phase shifter's varactor diode is included in the circuit as a large signal model provided by the manufacturer.

9B, the insertion loss is flat at about 4 dB at each voltage at 2 GHz, and the return loss is 10 dB or less. Here, the 4 dB insertion loss is caused by the varactor diode and the bias resistor, and can be improved by using a process with a large unit thin film resistance and using a varactor diode with a smaller series resistance.

Referring to FIG. 9C, it can be seen that the designed phase shifter result is almost the same as the result of FIG. 6 and shows a constant linear phase shift characteristic.

5. Phase Shifter Fabrication and Measurement

10 is a block diagram of a small analog phase shifter manufactured according to the present invention.

Referring to FIG. 10, the substrate used is a ceramic substrate having a dielectric constant of 9.9 and a thickness of 5 mils (1/1000 inch), and the size is 4 mm x 4 mm. At this time, the input and output was added to the corresponding 50 ohm CPW to be connected to the 1000 μm probe tip to facilitate on-wafer (on-wafer) measurement. The pitch distance from the center of the CPW signal conductor to the ground conductor is 1,000 μm, and the width of the signal conductor is equal to the 50 ohm width of the microstrip on the conventional substrate. The capacitor used in the DC supply (MW cap of FIG. 10) used a broadband capacitor.

The DC block capacitors needed for the input and output stages were removed to reduce the size of the phase shifter and the measurement DC block was used.

6. Measurement result

11A to 11D illustrate a measuring method using a wafer probe.

In FIGS. 11A-11D, a bias probe tip was used for the bias to measure the RF signal, and a network analyzer connected to the probe station was used for the on wafer measurement.

The probe is calibrated up to two probe tips with connected DC blocks. Through this, it is possible to measure an accurate pass phase and to measure the phase of the circuit in the reference line shown in FIGS. 11A to 11D.

Two DC probes were used, one for ground and the other for DC voltage bias.

The results obtained by measuring in this way are shown in FIGS. 12A-12C.

12A to 12C are graphs of measurement results of reflection loss S ₁₁ and insertion loss S _{21 according} to voltage Vt.

In FIGS. 12A to 12C, simulation results obtained in FIG. 8B are shown by dotted lines for 0, 3, and 5 V bias voltages, and measurement results of phase shifters manufactured according to the present invention are illustrated by solid lines.

Results similar to those obtained through simulations were obtained in FIGS. 12A to 12C. In terms of size, the insertion loss is about 1 dB larger than that of the simulation, and it is considered that the loss resistance included in the diode equivalent circuit model is considered smaller than the actual one, and thus the difference in the loss is shown.

However, we confirmed that the frequency response is constant within the frequency band.

13 is a graph of measured and simulated phase changes with supply voltage.

In FIG. 13, a straight line as an auxiliary line is simultaneously shown for easy comparison, and it can be seen that the phase shift is linear with respect to voltage. It can be seen that the measurement result of the phase is about 10 ° different from the simulation. This is considered to be due to the electrical length of the input / output line. In addition, the phase change near 0 V is slightly different from the linear auxiliary line, because the diode has a sudden change in capacitance at 0 V, which increases the nonlinearity.

However, the measured phase shifter shows the same amount of phase shift as the simulation, and the phase shift characteristic according to the supply voltage is almost linear as expected in the design, and the slopes of the two straight lines are the same.

As described above, the present invention improves the nonlinearity of the varactor diode and improves the small inductor in order to design a small analog type phase shifter having a size of 5 mm x 5 mm or less and a linear phase shift characteristic at 2 GHz. We propose and design a small phase shifter with linear phase characteristics at 2 GHz.

Accordingly, the small analog phase shifter according to the present invention satisfies the size of 4 mm x 4 mm required by the present invention, has a flat insertion loss of about 4.2 to 4.7 dB at 2 GHz, and a voltage of 0 to 5 V. The total phase shift of about 79 ° is shown, and there is a linear phase shift characteristic for this voltage.

The scope of the present invention is not limited to the embodiments described above, but is defined by the claims, and various changes and modifications can be made by those skilled in the art within the scope of the claims. It is self evident.

Claims (10)

A pair of varactor diodes connected in series,
A first inductor connected in parallel to the pair of varactor diodes,
And a global pass network having a second inductor connected between the node between the pair of varactor diodes and a ground potential line.
Inductances L ₁ and L ₂ of the first and second inductors are calculated by Equation 1,
And a series capacitor is connected between the pair of varactor diodes and the ground potential line to reduce the overall phase shift so as to have a linearity.
L ₁ = 2L ₀ , L ₂ = 1 / 2L ₀ ............... [Equation 1]
Where L ₀ is the inductance threshold set between 0.1 and 10 nH. The method of claim 1,
And said all-pass network has an all-pass characteristic in which the return loss (S ₁₁ ) is '0' and the insertion loss (S ₂₁ ) satisfies '1'. The method of claim 2, wherein the return loss (S ₁₁ ) and insertion loss (S21) is
And the return loss (S ₁₁ ) = 0 and insertion loss (S ₂₁ ) = 1 when the frequency ω ₀ = (L ₀ C ₁ ) ^-1/2 . 4. The method according to any one of claims 1 to 3,
Small analog phase shifter, characterized in that the reverse voltage is applied to the varactor diode. delete The method of claim 4, wherein
The all-pass network comprises an upper path and a lower path,
The upper path is provided with a bias resistor,
And the lower path includes a grounded second inductor, the varactor diode, and a series capacitor. The method of claim 6, wherein the lower path
Small analog phase shifter further comprises a grounding resistor. 8. The method of claim 7,
And said first and second inductors are planar circuits. The method according to claim 6,
The second inductor is a planar spiral inductor,
The series capacitor is a single layer capacitor. The method of claim 9, wherein the second inductor
2 resistors connected to the upper resistance pad in the center of the inside,
A first air bridge connecting the lower portion of the one resistance pad and the input port,
A second air bridge connecting between upper resistance pads and
Miniature analog phase shifter, characterized in that it consists of vias to external conductor pads.

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