KR101204428B1 - Fabrication method of light emitting diode LED package using SOI wafer - Google Patents

Abstract

A method of manufacturing a light emitting diode package according to the present invention includes preparing a SOI wafer having a through silicon via layer, a cup silicon layer and a junction insulating layer formed between two layers. The through silicon via layer is etched into the etch stop layer to form through silicon via holes for electrodes and through silicon via holes for heat sinks. An electrode and a heat sink conductive layer are formed in the through silicon via hole for the electrode and the through silicon via hole for the heat sink, respectively. The cup silicon layer is etched using the junction insulating layer as an etch stop layer to form a cup part. The junction insulating layer located in the cup part is etched to expose the heat sink conductive layer and the electrode. A light emitting diode chip is mounted on the exposed heat sink conductive layer in the cup part, and the light emitting diode chip is electrically connected to the electrode.

Description

Fabrication method of light emitting diode package using SOI wafer {Fabrication method of light emitting diode (LED) package using SOI wafer}

The present invention relates to a method of manufacturing a light emitting diode package, and more particularly, to a method of manufacturing a light emitting diode package of a wafer level using a silicon on insulator (SOI) wafer.

A light emitting diode (LED) is a device that generates light using an electric field emission phenomenon generated by applying a voltage to a semiconductor. The light emitting diode is an all-light conversion semiconductor device having a structure in which a p-type semiconductor crystal and an n-type semiconductor crystal are bonded to each other, and have a characteristic of converting an electrical signal into light. A light emitting diode is a compound semiconductor composed of Group III (Al, Ga, In) and Group V (As, P, N. Sb) elements on the periodic table of elements.

Light-emitting diodes are semi-permanent, environmentally friendly, and efficient compared to traditional light sources. Accordingly, the light emitting diodes are rapidly being used as backlight units of liquid crystal displays (LCDs), street lamps, traffic lights, automotive lighting, industrial lighting, home lighting, and the like. However, about 80% of the power supplied to the light emitting diode is emitted as heat. When the generated heat is not smoothly emitted, the efficiency of the light emitting diode is drastically reduced and the lifetime of the light emitting diode is also drastically reduced.

Light emitting diodes are mainly packaged and used. In other words, the LED package is packaged and used to seat the LED chip. However, the LED package should not only serve to seat the LED chip, but also to smoothly discharge heat generated from the LED chip to the outside. In addition, the light emitting diode package should be low in package cost, capable of mass production, and small in size and thin in thickness.

SUMMARY OF THE INVENTION An object of the present invention is to provide a light emitting diode package manufacturing method capable of smoothly dissipating heat generated from a light emitting diode chip at the wafer level to the outside using an SOI wafer including a silicon layer having excellent thermal conductivity.

In addition, another problem to be solved by the present invention is manufacturing a light emitting diode package that can ensure the uniformity of the position of the electrode in the wafer when forming the electrode on the SOI wafer while accurately seating the light emitting diode chip in the SOI wafer at the wafer level To provide a way.

In order to solve the above problems, a method of manufacturing a light emitting diode package according to an embodiment of the present invention includes preparing a SOI wafer having a through silicon via layer, a cup silicon layer and a junction insulating layer formed between two layers.
The through silicon via layer is etched into the etch stop layer to form through silicon via holes for electrodes and through silicon via holes for heat sinks. An electrode and a heat sink conductive layer are formed in the through silicon via hole for the electrode and the through silicon via hole for the heat sink, respectively.
The cup silicon layer is etched using the junction insulating layer as an etch stop layer to form a cup part. The junction insulating layer located in the cup part is etched to expose the heat sink conductive layer and the electrode. A light emitting diode chip is mounted on the exposed heat sink conductive layer in the cup part, and the light emitting diode chip is electrically connected to the electrode.
The electrode and the heat sink conductive layer,
Etching the through silicon via layer to form a through silicon via hole for one heat sink and two through silicon via holes for the electrode spaced apart from each other,
An insulating layer is formed on an inner wall of the two through silicon via holes for the two electrodes, an inner wall of the through silicon via hole for the one heat sink, and the through silicon via layer;
The electrode and the heat sink conductive layer may be formed on the insulating layer.
The electrode and the heat sink conductive layer may be formed by filling in the through silicon via holes for the electrode and the heat sink or on inner walls and the bottom of the through silicon via holes for the electrode and the heat sink.
The through silicon via holes and the cup part for the electrode and the heat sink are
Forming a mask layer on the through silicon via layer and the cup silicon layer;
The mask layer may be formed by wet etching the through silicon via layer and the cup silicon layer using an etch mask.
The mask layer may be formed of a silicon nitride film (Si ₃ N ₄ ), a silicon oxide film (SiO ₂ ), an aluminum nitride film (AlN), or a composite layer thereof.
A heat sink pad and an electrode pad may be further formed on the heat sink conductive layer and the electrode, and the light emitting diode chip may be mounted on the heat sink pad, and the light emitting diode chip may be electrically connected to the electrode pad.
When forming the heat sink pad and the electrode pad, a light reflection layer may be simultaneously formed on both side walls of the cup part. A fluorescent layer may be further formed inside the cup portion on which the LED chip is mounted.
The electrode and the heat sink conductive layer,
Etching the through silicon via layer to form one through silicon via hole for the electrode and one through silicon via hole for the heat sink;
The electrode and the heat sink conductive layer may be formed in the through silicon via hole for one electrode and the through silicon via hole for one heat sink, respectively.

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The light emitting diode package according to the present invention uses an SOI wafer including a through silicon via layer, a junction insulating layer, and a cup silicon layer. Accordingly, since the thicknesses of the through silicon via layer and the cup silicon layer can be arbitrarily adjusted, a light emitting diode package can be manufactured reliably while taking a manufacturing process easily.

The light emitting diode package according to the present invention can be obtained by etching a through silicon via hole or a cup part in a through silicon via layer or a cup silicon layer of an SOI wafer using a junction insulating layer as an etch stop layer in a wafer level state. As a result, the depth and arrangement of the through silicon via hole and the cup portion can be made uniform over the entire surface of the SOI wafer.

The light emitting diode package according to the present invention can be obtained by simultaneously etching the through silicon via hole or the cup part in the through silicon via layer or the cup silicon layer of the SOI wafer by the wet etching method using the junction insulating layer as the etch stop layer. Accordingly, the light emitting diode package according to the present invention can obtain a light emitting diode package in a large amount while simplifying the manufacturing process.

1 is a plan view of a light emitting diode package according to the first to fourth embodiments of the present invention.
2 is a cross-sectional view of a light emitting diode package according to a first embodiment of the present invention.
3 is a cross-sectional view of a light emitting diode package according to a second embodiment of the present invention.
4 is a cross-sectional view of a light emitting diode package according to a third embodiment of the present invention.
5 to 14 are cross-sectional views illustrating a method of manufacturing the light emitting diode package of FIG. 2.
15 to 22 are cross-sectional views illustrating a method of manufacturing the light emitting diode package of FIG. 3.
FIG. 23 is a cross-sectional view illustrating a method of manufacturing the light emitting diode package of FIG. 4.
24 is a cross-sectional view illustrating a light emitting diode package according to a fourth embodiment of the present invention.
25 and 26 are plan views and cross-sectional views illustrating a light emitting diode package according to a fifth embodiment of the present invention.
27 and 28 are plan views and cross-sectional views illustrating a light emitting diode package according to a sixth embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. The present invention is capable of various modifications and various forms, and specific embodiments are illustrated and described in detail in the drawings. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for similar elements in describing each drawing. In the accompanying drawings, the dimensions of the structures are enlarged or reduced from the actual dimensions for the sake of clarity of the present invention.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprises", "having", and the like are used to specify that a feature, a number, a step, an operation, an element, a part or a combination thereof is described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

1 is a plan view of a light emitting diode package according to the first to fourth embodiments of the present invention.

Specifically, the LED package according to the present invention is implemented using the SOI substrates 107 and 207. The light emitting diode chips 131 and 237 are positioned in the cup portions 121 and 215 formed at the central portion of the cup silicon layers 105 and 205 constituting the SOI substrates 107 and 207. The LED chips 131 and 237 form through-silicon via holes formed in the through-silicon via layers 101 and 201 constituting the SOI substrates 107 and 207, and the heat sink conductive layers 118, 225, and 325 provided therein. ) Heat sink pads 129 and 233 may be provided on the heat sink conductive layers 118, 225, and 235.

The connection pads 132 of the light emitting diode chips 131 and 237 form through silicon via holes formed in the through silicon via layers 101 and 201 and are bonded to the electrode pads 125, 127, 231 and 235 provided therein. It is electrically connected through wires 133 and 239. The electrode pads 125, 127, 231, and 235 may be distinguished into first electrode pads 125 and 231, for example, positive electrode pads and second electrode pads 127 and 235, for example, negative electrode pads.

Fluorescent layers (not shown) may be located in the cups 121 and 215 on the light emitting diode chips 131 and 237, and light reflection layers (not shown) may be formed on both side walls of the cup part. In addition, a heat sink (not shown) may be installed under the heat sink conductive layers 118, 225, and 325 in which the light emitting diode chips 131 and 237 are positioned, and may radiate heat generated from the light emitting diode chip to the outside. . Embodiments of a cross section of the LED package as shown in FIG. 1 will be described with reference to FIGS. 2 through 4.

2 is a cross-sectional view of a light emitting diode package according to a first embodiment of the present invention.

Specifically, the LED package according to the first embodiment of the present invention includes an SOI wafer 107 composed of a through silicon via layer 101, a junction insulating layer 103, and a cup silicon layer 105. The cup silicon layer 105 of the SOI wafer 107 is etched to provide a cup portion 121. The through silicon via layer 101 of the SOI substrate 107 is etched to form a plurality of through silicon via holes (not shown), and the heat sink conductive layer 118 and the inside and through the silicon via layer 101 are formed. Electrodes 115 and 116 are formed. The heat sink conductive layer 118 and the electrodes 115, 116 are insulated with the insulating layer 111, and are distinguished by the openings 117a, 117b. The electrodes 115 and 116 may be divided into a first electrode 115 such as an anode and a second electrode 116 such as a cathode. The first electrode 115 and the second electrode 116 are divided for convenience.

The junction insulating layer 103 in the cup portion 121 is etched and removed. The heat sink pad 129 is positioned on the heat sink conductive layer 118 in the cup portion 121, the first electrode pad 125 is positioned on the first electrode 115, and the second electrode is disposed on the second electrode 116. The pad 127 is located. The LED chip 131 is positioned on the heat sink pad 129.

The LED chip 131 is electrically connected to the electrode pads 125 and 127. The fluorescent layer 135 is formed in the cup 121 on the light emitting diode chip 131. The light reflection layer 123 may be formed on both side walls of the cup part 121. In addition, a heat sink (not shown) may be installed under the heat sink conductive layer 118 in which the light emitting diode chip 131 is disposed to discharge heat generated from the light emitting diode chip 131 to the outside.

3 is a cross-sectional view of a light emitting diode package according to a second embodiment of the present invention.

Specifically, in the LED package according to the second embodiment of the present invention, the heat sink conductive layer 225 and the electrodes 223 and 227 may be shaped or shaped as the heat sink conductive layer 118 and the electrodes of the first embodiment. It is substantially the same except that it is different from (115, 116).

In more detail, the SOI wafer 207 including the through silicon via layer 201, the junction insulating layer 203, and the cup silicon layer 205 is provided. The cup silicon layer 205 of the SOI wafer 207 is etched to provide a cup portion 215. The through silicon via layer 201 of the SOI substrate 207 is etched to form a plurality of through silicon via holes (not shown), and the heat sink conductive layer 225 and the inside and through the silicon via layer 201 are formed thereon. Electrodes 223 and 227 are formed.

Since the heat sink conductive layer 225 and the electrodes 223 and 227 are formed in the through silicon via hole formed by wet etching, the heat sink conductive layer 225 and the electrodes 223 and 227 are formed to have a smaller upper surface and a wider lower surface than in FIG. The heat sink conductive layer 225 and the electrodes 223, 227 are insulated with the insulating layer 221 and are distinguished by the openings 228a, 228b. The electrodes 223 and 227 may be divided into a first electrode 223 such as an anode and a second electrode 227 such as a cathode.

The junction insulating layer 203 in the cup portion 215 is etched away. The heat sink pad 233 is positioned on the heat sink conductive layer 225 in the cup part 215, the first electrode pad 231 is positioned on the first electrode 223, and the second electrode is disposed on the second electrode 227. Pad 235 is located. The light emitting diode chip 237 is positioned on the heat sink pad 233.

The light emitting diode chip 237 is electrically connected to the electrode pads 231 and 235. The fluorescent layer 241 is formed in the cup part 215 on the light emitting diode chip 237. The light reflection layer 229 may be formed on both side walls of the cup part 215. In addition, a heat sink (not shown) may be installed under the heat sink conductive layer 225 in which the light emitting diode chip 237 is positioned to discharge heat generated from the light emitting diode chip 237 to the outside.

4 is a cross-sectional view of a light emitting diode package according to a third embodiment of the present invention.

Specifically, the light emitting diode package according to the third embodiment of the present invention is almost the same as in the second embodiment. However, the first electrode 323, the heat sink conductive layer 325, and the second electrode 327 are compared with the first electrode 223, the heat sink conductive layer 225, and the second electrode 227 of the second embodiment. This is the same except that it is not filled in the through silicon via hole and is formed on the inner wall of the through silicon via hole and the second insulating layer 221.

Hereinafter, the light emitting diode package manufacturing method described above will be described. Hereinafter, the manufacturing method is manufactured at the wafer level, but for convenience, only one light emitting diode package manufacturing process will be described.

5 to 14 are cross-sectional views illustrating a method of manufacturing the light emitting diode package of FIG. 2.

Referring to FIG. 5, an SOI wafer 107 is prepared. The SOI wafer 107 has a circular shape with a (100) plane of about 6 to 12 inches in diameter and has a thickness of hundreds to thousands of micrometers. An SOI wafer is formed by bonding two sheets of silicon wafers having a (001) crystal plane. The SOI wafer 107 includes a through silicon via layer 101, a cup silicon layer 105, and a junction insulating layer 103.

The junction insulating layer 103 is positioned between the through silicon via layer 101 and the cup silicon layer 105. The junction insulating layer 103 is formed of a material in which etching is hardly performed with respect to the silicon wet etching solution. The junction insulating layer 103 is formed of a material having a very high etching selectivity with the silicon layer. The junction insulating layer 103 is formed of a silicon nitride film (Si ₃ N ₄ ), a silicon oxide film (SiO ₂ ), an aluminum nitride film (AlN), or a composite layer thereof. The junction insulating layer 103 is formed to a thickness of 0.03 to 5 mu m.

The through silicon via layer 101 is formed to have a uniform thickness over the entire surface. The through silicon via layer 101 may have a thickness of 30 to 700 μm. The cup silicon layer 105 is formed to have a uniform thickness over the entire surface. The thickness of the cup silicon layer 105 may be formed to a thickness of 100 to 800 ㎛. The individual thicknesses of the through silicon via layer 101 and the cup silicon layer 105 can be adjusted in the manufacture of the SOI wafer 107.

In the through-silicon via layer 101, the conductive layer for electrodes or heat sinks is formed in the through-silicon via hole and the through-silicon via hole in a later step. In the cup silicon layer 105, a cup part is formed and a light emitting diode chip is mounted on the cup part. As described later, the junction insulating layer 103 may be introduced to improve depth variation for each wafer position during silicon wet etching for forming through silicon via holes or cup portions.

Referring to FIG. 6, the through silicon via layer 101 is patterned to form a plurality of through silicon via holes 109a and 109b in which an electrode or a heat sink conductive layer is to be formed. After the photoresist pattern (not shown) is formed on the through silicon via layer 101, the through silicon via layer 101 is etched to form through silicon via holes 109a and 109b. The through silicon via holes 109a and 109b are formed by anisotropically etching the through silicon via layer 101 using a photoresist pattern as an etching mask. Accordingly, the through silicon via holes 109a and 109b are formed to have sidewalls vertically inward from the surface of the through silicon via layer 101.

Since the junction insulating layer 103 is used as an etch stop layer when the through silicon via holes 109a and 109b are formed, the depth or arrangement of the through silicon via holes 109a and 109b is changed over the entire surface of the SOI wafer 107. It can be made uniform. The through silicon via holes 109a and 109b may be classified into a through silicon via hole 109a for an electrode and a through silicon via hole 109b for a heat sink.

Referring to FIG. 7, an insulating layer 111 is formed on both surfaces of the SOI wafer 107. The insulating layer 111 is formed of a silicon nitride film (Si ₃ N ₄ ), a silicon oxide film (SiO ₂ ), an aluminum nitride film (AlN), or a composite layer thereof. The thickness of the insulating layer 111 is formed to a thickness of 0.03㎛ to 20㎛. The insulating layer 111 is formed on the inner wall of the through silicon via holes 109a and 109b and the through silicon via layer 101. The insulating layer 111 is formed on the cup silicon layer 105. The insulating layer formed on the through silicon via layer 101 serves to insulate the electrodes later. The insulating layer 111 formed on the cup silicon layer 105 may serve as a mask when forming the cup part for mounting the LED chip on the cup silicon layer 105.

Referring to FIG. 8, a conductive layer 113 is formed on the entire surface of the through silicon via layer 101. The conductive layer 113 is formed on the insulating layer 111 in the through silicon via holes 109a and 109b and on the insulating layer 111 on the through silicon via layer 101. The conductive layer 113 is formed to fill the through silicon via holes 109a and 109b. The conductive layer 113 can be formed using a metal film such as copper, aluminum (Al), gold (Au), silver (Ag), or an alloy film thereof.

In order to improve adhesion of the conductive layer 113 to the insulating layer 111, an adhesion improving layer such as titanium (Ti), nickel (Ni), and tantalum (Ta) may be formed between the insulating layer 111 and the conductive layer 113. More can be formed. When the conductive layer 113 is formed of a metal film, the conductive layer 113 may be formed by an electroplating method, a sputtering method, a screen printing method using a metal paste, an evaporation method, or a chemical vapor deposition method. In this embodiment, the conductive layer 113 is formed of a copper film using the electroplating method.

Referring to FIG. 9, the conductive layer 113 is patterned to form a first electrode 115, a heat sink conductive layer 118, and a second electrode 116, and these electrodes 115 and 116 or a heat sink conductive layer. Openings 117a and 117b separating 118 are formed. The heat sink conductive layer 118 is formed at the center portion of the through silicon via layer 101, and the first electrode 115 and the second electrode 116 are formed at both sides of the heat sink conductive layer 118. After forming a photoresist pattern (not shown) on the conductive layer 113, the conductive layer 113 is selectively etched to form the first electrode 115, the heat sink conductive layer 118, the second electrode 116, And openings 117a and 117b.

Referring to FIG. 10, the insulating layer 111 formed on the cup silicon layer 105 is patterned to form a mask layer 119. After forming a photoresist pattern (not shown) on the cup silicon layer 105, the insulating layer 111 is selectively etched to form a mask layer 119.

Referring to FIG. 11, the cup silicon layer 105 is etched using the mask layer 119 as an etch mask to form the cup part 121. The cup silicon layer 105 is etched using a wet etching method. When forming the cup part 121, the insulating layer 111 formed on the through silicon via layer 101 also serves as a mask layer. The wet etching of the cup silicon layer 105 may be performed by using an alkaline anisotropic etchant (KOH), tetramethyl ammonium hydroxide (TMAH), and ethylene diamine pyrocatechol (EDP).

When the silicon nitride film or the silicon oxide film is used as the mask layer 119, the etch selectivity of the etching solution is very large, about 200: 1 to 10,000: 1. In addition, in the etching selectivity ratio between the crystallographic aspects of silicon with respect to the etching solution described above, it is excellent, between 200: 1 and 30: 1, between (100) :( 111) planes. Accordingly, as shown in FIG. 11, the cup portion 121 having a lower width and a larger upper width may be formed. The inclination between the lower surface and the upper surface of the cup portion 121 is about 54.7 degrees as an angle of the (111) surface with respect to the (100) surface.

If the thicknesses of the silicon wafers constituting the through-silicon via layer 101 and the cup silicon layer 105 are different from each other, a thicker wafer may be formed because the etching selectivity between the mask layer 119, the insulating layer 111, and the silicon layer is large. The etching process may be performed as a reference. When the thicknesses of the silicon wafers constituting the through-silicon via layer 101 and the cup silicon layer 105 are significantly different, the etching process may be performed by adjusting the thickness and type of the mask layer 119 and the insulating layer 111. Can be.

When etching the cup silicon layer 105 for forming the cup part 121, the junction insulating layer 103 is used as an etch stop layer. Since the junction insulating layer 103 is used as an etch stop layer when the cup portion 121 is formed, the depth and arrangement of the cup portion 121 can be made uniform over the entire surface of the SOI wafer 107.

Referring to FIG. 12, the junction insulating layer 103 and the insulating layer 111 are etched by a wet or dry method in the cup part 121 to form a first electrode 115, a heat sink conductive layer 118, and a second electrode. Expose (116). In other words, the first insulating layer 115 and the heat sink conductive layer 118 are etched by etching the junction insulating layer 103 in the cup 121 and the insulating layer 111 formed on the inside of the through silicon via holes 109a and 109b. And expose the second electrode 116.

Referring to FIG. 13, pad electrodes 125 and 127, a heat sink pad 129, and a light reflection layer 123 are formed on the inner bottom and sidewalls of the cup part 121. The pad electrodes 125 and 127 are formed on the first electrode 115 and the second electrode 116. The pad electrodes 125 and 127 may be divided into a first pad electrode 125 and a second pad electrode 127. The heat sink pad 129 is formed on the heat sink conductive layer 118. The light reflection layer 123 is formed on both side walls of the cup portion 121 and the cup silicon layer 105.

The pad electrodes 125 and 127, the heat sink pads 129, and the light reflection layer 123 are formed by depositing a metal layer, for example, an aluminum film or a silver film on the entire surface of the cup part 121, and then forming a photoresist film, an exposure process, and a development. fair. It may be formed through a patterning process through an etching process. The pad electrodes 125 and 127, the heat sink pad 129, and the light reflection layer 123 are formed on the entire surface of the cup portion 121 by a photoresist film forming process, an exposure process, a metal layer forming process, and a photoresist film lift-off process. Can be formed.

Referring to FIG. 14, the LED chip 131 is mounted on a heat sink pad in the cup 121. Subsequently, the LED chip 131 connects the first pad electrode 125 on the first electrode 115 and the second pad electrode 127 on the second electrode with the bonding wire 133.

Subsequently, as illustrated in FIG. 2, the light emitting layer 123 and the fluorescent layer 135 are formed in the cup part 121 on both side walls of the cup part 121, thereby completing the LED package. In addition, a heat sink (not shown) may be installed under the heat sink conductive layer 118 in which the light emitting diode chip 131 is disposed to discharge heat generated from the light emitting diode chip 131 to the outside.

15 to 22 are cross-sectional views illustrating a method of manufacturing the light emitting diode package of FIG. 3.

Specifically, the method of manufacturing the LED package of FIGS. 15 to 22 is substantially the same except that the through silicon via holes 217a and 217b and the cup part 215 are simultaneously formed as compared with FIGS. 5 to 14. The method of manufacturing the LED package of FIGS. 15 to 22 is substantially the same except that the through silicon via holes 217a and 217b and the cup portion 215 are formed at the same time.

Referring to FIG. 15, an SOI wafer 207 is prepared. The SOI wafer 207 is the same as the SOI wafer 107 of FIG. 5. The SOI wafer 207 includes a through silicon via layer 201, a cup silicon layer 205, and a junction insulating layer 203. The through silicon via layer 201 is the same as the through silicon via layer 101 of FIG. 5, the cup silicon layer 205 is the same as the cup silicon layer 105 of FIG. 5, and the junction insulating layer 203 is shown in FIG. It is the same as the junction insulating layer 103 of 5.

Subsequently, the first insulating layer 209 is formed on both surfaces of the SOI wafer 207. The first insulating layer 209 is formed of a silicon nitride film (Si ₃ N ₄ ), a silicon oxide film (SiO ₂ ), an aluminum nitride film (AlN), or a composite layer thereof. The insulating layer 209 has a thickness of 0.03 µm to 20 µm.

Referring to FIG. 16, mask layers 213 and 211 are formed by patterning the first insulating layer 209 formed on the through silicon via layer 201 and the cup silicon layer 205. After forming a photoresist pattern (not shown) on the through silicon via layer 201 and the cup silicon layer 205, the first insulating layer 209 is selectively etched to form mask layers 213 and 211.

Referring to FIG. 17, through silicon via holes in which the through silicon via layer 201 and the cup silicon layer 205 are wet etched using the mask layers 213 and 211 as an etch mask to form an electrode or a heat sink conductive layer are formed. 217a and 217b and the cup part 215 on which the light emitting diode chip is to be mounted are formed at the same time. The through silicon via layer 201 and the cup silicon layer 205 are etched using a wet etching method.

Wet etching of the through silicon via layer 201 and the cup silicon layer 205 may be performed using alkaline anisotropic etchant (KOH), tetramethyl ammonium hydroxide (TMAH), and ethylene diamine pyrocatechol (EDP). . The cup part 215 is formed by the same method as the cup part 121 of FIG.

The through silicon via holes 217a and 217b are formed by wet etching the through silicon via layer 201 using the mask layer 213 as an etch mask. Accordingly, the through silicon via holes 217a and 217b are formed to have sidewalls that are not perpendicular to the inside of the surface of the through silicon via layer 201 and are inclined.

Since the junction insulating layer 203 is used as an etch stop layer when the through silicon via holes 217a and 217b and the cup portion 215 are formed, the through silicon via holes 217a and 217b and the cup portion are formed over the entire surface of the SOI wafer 207. The depth of 121 and arrangement | positioning state can be made uniform. The through silicon via holes 217a and 217b may be classified into a through silicon via hole 217a for an electrode and a through silicon via hole 217b for a heat sink.

Referring to FIG. 18, second insulating layers 219 and 221 are formed on the inner wall of the through-silicon via holes 217a and 217b, the inside of the cup part 215, and the mask layers 213 and 211. The second insulating layer 221 formed on the inner wall of the through silicon via holes 217a and 217b serves to insulate the electrodes. The second insulating layers 219 and 221 are formed of a silicon nitride film (Si ₃ N ₄ ), a silicon oxide film (SiO ₂ ), an aluminum nitride film (AlN), or a composite layer thereof.

Referring to FIG. 19, a conductive layer (not shown) is formed on top of the second insulating layer 211 in the through silicon via holes 217a and 217b and on the second insulating layer 211 on the through silicon via layer 201. Openings separating the first electrode 223, the heat sink conductive layer 225, and the second electrode 227, and the electrodes 223 and 227 or the heat sink conductive layer 225 after forming a pattern. 228a and 228b. The heat sink conductive layer 225 corresponds to the heat sink conductive layer 118 of FIG. 9, the first electrode 223 corresponds to the first electrode 115 of FIG. 9, and the second electrode 227 is illustrated in FIG. 9. It corresponds to the second electrode 116 of 9.

Referring to FIG. 20, the junction insulating layer 203 and the second insulating layer 219 are etched by a wet or dry method in the cup part 215 to form the first electrode 223, the heat sink conductive layer 225, and the first insulating layer 225. 2 electrodes 227 are exposed. In other words, the junction insulating layer 203 in the cup part 215 and the second insulating layer 219 formed above the through silicon via holes 217a and 217b are etched to etch the first electrode 223 and the heat sink conductive layer ( 225 and the second electrode 227 are exposed.

Referring to FIG. 21, pad electrodes 231 and 235, a heat sink pad 233, and a light reflection layer 229 are formed on the inner bottom and sidewalls of the cup part 215. The pad electrodes 231 and 235 are formed on the first electrode 223 and the second electrode 227. The pad electrodes 231 and 235 may be divided into a first pad electrode 223 and a second pad electrode 227. The heat sink pad 233 is formed on the heat sink conductive layer 225. The light reflection layer 229 is formed on both side walls of the cup portion 215 and the cup silicon layer 205.

The pad electrodes 231 and 235, the heat sink pads 233, and the light reflection layer 229 correspond to the pad electrodes 125 and 127, the heat sink pad 129, and the light reflection layer 123 of FIG. 13. It can form in the same way.

Referring to FIG. 22, a light emitting diode chip 237 is mounted on the heat sink pad 233 in the cup part 215. Subsequently, the LED chip 237 connects the first pad electrode 231 on the first electrode 223 and the second pad electrode 235 on the second electrode with a bonding wire 133.

Subsequently, as shown in FIG. 3, the light emitting layer 229 and the fluorescent layer 241 are formed in the cup portion 215 on both side walls of the cup portion 215 to complete the light emitting diode package. In addition, a heat sink (not shown) may be installed under the heat sink conductive layer 225 in which the light emitting diode chip 237 is positioned to discharge heat generated from the light emitting diode chip 237 to the outside.

FIG. 23 is a cross-sectional view illustrating a method of manufacturing the light emitting diode package of FIG. 4.

Specifically, the manufacturing method of the LED package of FIG. 23 is almost the same as that of FIGS. 15 to 22. However, the first electrode 323, the heat sink conductive layer 325, and the second electrode 327 formed in the through silicon via holes 217a and 217b are the first electrode 223 and the heat sink conductive layer 225 of FIG. 19. ) And the second electrode 227 are not filled in the through silicon via holes 217a and 217b and are formed on the inner wall of the through silicon via holes 217a and 217b and the second insulating layer 221. .

24 is a cross-sectional view illustrating a light emitting diode package according to a fourth embodiment of the present invention.

Specifically, in the LED package according to the fourth embodiment of the present invention, the LED chip 131 is directly formed on the heat sink conductive layer 118, and the heat sink pad 129 and the electrode pads 125 and 127 are provided. The structure and the manufacturing method of the first embodiment of FIG. The LED chip 131 is directly connected to the electrodes 115 and 116. In the LED package according to the fourth embodiment of the present invention, the heat generated from the LED chip 131 can be directly discharged to the heat sink conductive layer 118 while simplifying the manufacturing process.

25 and 26 are plan views and cross-sectional views illustrating a light emitting diode package according to a fifth embodiment of the present invention.

Specifically, in the LED package according to the fifth embodiment of the present invention, the LED chip 131a is a vertical LED chip, and the heat sink pad 129 and the electrode pads 125 and 127 are not formed. Except for the structure and manufacturing method of the first embodiment of Figs.

In the vertical LED chip 131a, a pad 132 is positioned on a chip surface, and is connected to the first electrode 115. The second electrode 116 and the heat sink conductive layer 118 simultaneously serve as an electrode and a heat sink as a body. The vertical LED chip 131a is directly connected to the electrodes 115 and 116.

In the manufacturing method of the LED package according to the fifth embodiment of the present invention, the through silicon via hole 109a of one side, for example, the left side is not formed in the manufacturing process of FIG. 6, and the openings of the conductive layer pattern of FIGS. 8 and 9 are formed. If 117b) is not formed, it is the same as the manufacturing method of the first embodiment.

In the LED package according to the fifth embodiment of the present invention, since only one pad 132 is positioned on the chip surface of the vertical LED chip 131a, the light emitting area can be increased. In addition, heat generated in the LED chip 131a may be directly discharged to the heat sink conductive layer 118.

27 and 28 are plan views and cross-sectional views illustrating a light emitting diode package according to a sixth embodiment of the present invention.

Specifically, in the LED package according to the sixth embodiment of the present invention, the LED chip 131b is connected to the heat sink conductive layer 118 and the first electrode 115 in the form of a flip chip, and the heat sink pad 129 is provided. ), Except that the electrode pads 125 and 127 are not formed, the structure and manufacturing method of the first embodiment of FIGS. 1 and 2 are almost the same.

The light emitting diode chip 131 is connected to the heat sink conductive layer 118 and the first electrode 115 in a flip chip form. The second electrode 116 and the heat sink conductive layer 118 simultaneously serve as an electrode and a heat sink as a body. The LED chip 131b is connected to the electrodes 115 and 116 through the pads 134.

In the manufacturing method of the LED package according to the sixth embodiment of the present invention, the through silicon via hole 109a of one side, for example, the left side is not formed in the manufacturing process of FIG. 6, and the openings of the conductive layer pattern of FIGS. 8 and 9 are formed. If 117b) is not formed, it is the same as the manufacturing method of the first embodiment. Since the LED package according to the sixth embodiment of the present invention does not use a bonding wire, the manufacturing process is easy and light absorption loss can be minimized.

107, 207: SOI substrate, 105, 205: cup silicon layer, 103, 203: junction insulating layer, 121, 215: cup portion, 109, 217: through silicon via hole, 118, 225, 325: heat sink conductive layer, 115, 223, 116, 227, 323, 327: electrode, 131, 131a, 131b: light emitting diode chip, 117, 228: opening

Claims (9)

Preparing an SOI wafer having a through silicon via layer, a cup silicon layer and a junction insulating layer formed between the two layers;
Etching the through silicon via layer into the etch stop layer to form through silicon via holes for electrodes and through silicon via holes for heat sinks;
Forming an electrode and a heat sink conductive layer in the through silicon via hole for the electrode and the through silicon via hole for the heat sink, respectively;
Etching the cup silicon layer using the junction insulating layer as an etch stop layer to form a cup part;
Etching the junction insulating layer positioned in the cup to expose the heat sink conductive layer and the electrode;
Mounting a light emitting diode chip on the exposed heat sink conductive layer in the cup portion; And
The method of manufacturing a light emitting diode package, characterized in that for electrically connecting the light emitting diode chip with the electrode. The method of claim 1, wherein the electrode and the heat sink conductive layer,
Etching the through silicon via layer to form a through silicon via hole for one heat sink and two through silicon via holes for the electrode spaced apart from each other;
Forming an insulating layer on an inner wall of the through silicon via holes for the two electrodes, an inner wall of the through silicon via hole for the heat sink, and the through silicon via layer;
And forming the electrode and the heat sink conductive layer on the insulating layer. The method of claim 1, wherein the electrode and the heat sink conductive layer are formed by filling the inside of the through silicon via holes for the electrode and the heat sink, or the inner wall and the bottom of the through silicon via holes for the electrode and the heat sink. Method of manufacturing a light emitting diode package. The method of claim 1, wherein the through silicon via holes for the electrode and the heat sink and the cup portion
Forming a mask layer on the through silicon via layer and the cup silicon layer;
The method of claim 1, wherein the mask layer is formed by wet etching the through silicon via layer and the cup silicon layer using an etch mask. The method of claim 4, wherein the mask layer is formed of a silicon nitride film (Si ₃ N ₄ ), a silicon oxide film (SiO ₂ ), an aluminum nitride film (AlN), or a composite layer thereof. The semiconductor device of claim 1, further comprising a heat sink pad and an electrode pad on the heat sink conductive layer and the electrode, respectively, mounting the light emitting diode chip on the heat sink pad, wherein the light emitting diode chip is connected to the electrode pad. Method of manufacturing a light emitting diode package, characterized in that electrically connected. The method of claim 6, wherein when the heat sink pad and the electrode pad are formed, a light reflection layer is simultaneously formed on both side walls of the cup part. The method of claim 1, wherein a fluorescent layer is further formed inside the cup part on which the light emitting diode chip is mounted. The method of claim 1, wherein the electrode and the heat sink conductive layer,
Etching the through silicon via layer to form one through silicon via hole for the electrode and one through silicon via hole for the heat sink;
And forming the electrode and the heat sink conductive layer in the one through silicon via hole for the one electrode and the one through silicon via hole for the heat sink, respectively.

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