KR101181244B1 - Liquid crystal display device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and in particular, to prevent failure of an outermost region of a liquid crystal panel.

The present invention is characterized in that the dummy gate and the data line which are adjacent to the outermost gate and the data line are further formed in the non-display area outside the gate and the data line disposed at the outermost side of the liquid crystal panel display area. do.

As a result, the gate and data lines disposed at the center of the display area are symmetrically disposed on both sides thereof to provide the same environment as the electrical effects of neighboring gates and data lines, and are formed in the non-display area. By not being affected by the ground wiring, problems such as edge brightness or first gate wiring brightness, which are the outermost defects of the liquid crystal panel, can be solved, and uniform luminance can be exhibited to the entire surface of the liquid crystal panel.

Description

[0001] Liquid crystal display device [0002]

1 is a schematic plan view of a general liquid crystal panel;

FIG. 2 is a schematic enlarged view of a gate and data pad part and a gate and data wiring of FIG. 1; FIG.

3 is a schematic plan view of a liquid crystal panel according to an exemplary embodiment of the present invention.

FIG. 4 is a schematic enlarged view of a gate and data pad part and a gate and data line of FIG. 3; FIG.

FIG. 5 is a cross-sectional view taken along the line VV of FIG. 4. FIG.

<Description of the symbols for the main parts of the drawings>

GPA, DPA: Gate pad section, data pad section

DL, GL: Data Wiring, Gate Wiring

AA: display area P: pixel area

111: array substrate 113: color filter substrate

115: seal pattern 117: black matrix

119: data pad 125: gate pad

151: dummy data pad 155: dummy data wiring

157: dummy gate pad 161: dummy gate wiring

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and in particular, to prevent failure of an outermost region of a liquid crystal panel.

The image realization principle of a general liquid crystal display device uses the optical anisotropy and polarization property of the liquid crystal. The liquid crystal has a thin and long molecular structure and polarization in which the direction of the molecular array changes according to its size when placed in an electric field and an anisotropy having an orientation in the array. It has a nature. The liquid crystal display is an essential component of a liquid crystal panel composed of a pair of transparent insulating substrates, each having a liquid crystal layer interposed therebetween, and having a field generating electrode formed therebetween. Various images are displayed by artificially adjusting the arrangement direction of the molecules and using the light transmittance which is changed at this time.

In general, a liquid crystal display device forms an array substrate and a color filter substrate through an array substrate manufacturing process for forming a thin film transistor and a pixel electrode, and a color filter substrate manufacturing process for forming a color filter and a common electrode, and between the two substrates. It completes through the liquid crystal cell process through a liquid crystal.

1 is a view schematically showing a plan view of a general liquid crystal panel.

In general, the liquid crystal panel includes a lower array substrate 1 and an upper color filter substrate 3, and liquid crystal is filled between the two substrates 1 and 3.

In the display area AA on the array substrate 1, data lines DL and gate lines GL cross each other to define a pixel area P, and the gate line GL and the data line DL are defined. A thin film transistor (not shown) is formed at this intersection.

Color filters (not shown) separated by cell regions are formed on the color filter substrate 3 by the black matrix 5, and a common electrode (not shown) is formed on the color filters (not shown).

In addition, the black matrix 5 is formed at an edge between the two substrates, and a seal pattern 7 is formed to prevent leakage of the liquid crystal filled between the two substrates.

In this case, gate and data pads 9 and 13 connected to the gate and data lines GL and DL are respectively disposed in a non-display area on one side of the array substrate 1 where the gate and data lines GL and DL are arranged. The formed pad portions DPA and GPA are formed.

At this time, although not shown, the gate and data lines GL and DL are connected to gate and data driving circuits, which are external circuits, to receive display control signals and data signals.

FIG. 2 is a schematic enlarged view of the gate and data pad unit and the gate and data wiring of FIG. 1.

As illustrated, the gate and data pads 9 and 13 receive a predetermined signal from the gate and data lines GL and DL and external driving circuits and apply the predetermined signals to the gate and data lines GL and DL. ) Is formed.

The data lines DL and the gate lines GL cross each other in a matrix to define red, green, and blue pixels P, and the liquid crystal cells are switched at the intersections, and the gate electrode, the source and drain electrodes, etc. The thin film transistor T is formed.

In addition, the gate and data pads 9 and 13 receive a gate and a data signal for controlling the thin film transistor T from an external driving circuit and supply the gate and data signals to the gate and data lines GL and DL. do.

The gate and data pads 9 and 13 are configured in the non-display area of the liquid crystal panel, and the gate and data wirings GL and DL are configured in the display area AA of the liquid crystal panel.

In this case, the black matrix 5 is also positioned at the red, green, and blue pixel P boundaries of the color filter substrate 3 and the edges of the color filter substrate 3.

However, the gate and data lines GL and DL disposed at the center of the liquid crystal panel display area AA are symmetrical with each other and the gates and data lines GL and DL are adjacent to each other. And maintain electrical equilibrium between the signals flowing in the data lines GL and DL, while the gate and data lines GL and DL disposed at the outermost portion of the display area AA are adjacent to the gate and data lines. Since GL and DL are not symmetrical, there is a problem in that electrical equilibrium between signals cannot be maintained.

Furthermore, the gate and data lines GL and DL disposed at the outermost portion of the display area AA are affected by the signal lines (eg, common signals) configured at the non-display area, so that the edges are bright at the outermost portion of the liquid crystal panel. Or the first gate wiring is bright.

That is, the edge area of the display area AA emits brighter light than the center part of the display area AA of the liquid crystal panel, or one edge of the display area AA shines brighter than the center part.

Therefore, a problem arises in that luminance is not uniform throughout the liquid crystal panel.

The present invention has been made to solve the above problems, and an object of the present invention is to prevent outermost defects of the liquid crystal panel and to exhibit uniform luminance as a whole.

In order to achieve the above object, the present invention provides a display device comprising: a first substrate divided into a display area and a non-display area; A gate wiring disposed in one direction of the display area on the first substrate; A data line crossing the gate line and defining a pixel area; A dummy gate line positioned in the non-display area in parallel with the gate line configured at the outermost portion of the display area; A dummy data line positioned in the non-display area in parallel with the data line configured at the outermost portion of the display area; A thin film transistor positioned at an intersection of the gate and the data line; A pixel electrode on the pixel area; A black matrix, a color filter, and a common electrode formed on one surface of the second substrate facing the first substrate; A liquid crystal layer formed in the spaced space between the first substrate and the second substrate; Provided is a liquid crystal display device including a seal pattern for preventing leakage of the liquid crystal layer.

The thin film transistor is positioned at an intersection of the gate and the data line, and includes a gate electrode, a gate insulating layer, an active layer, and a source and a drain electrode, and the drain electrode is in contact with the pixel electrode. It is done.

The black matrix may be configured between the non-display area and the color filter, and the gate and data lines and the dummy gate and data lines may receive a predetermined signal from a driving circuit.

The driving circuit may further include a dummy pin connected to the dummy gate and the data wiring.

Defining a display area and a non-display area on the first substrate; Forming gate wirings in one direction on the display area on the first substrate; Forming a dummy gate wiring adjacent to the gate wiring disposed at the outermost portion of the display area in the non-display area; Forming a data line crossing the gate line to define a pixel area; Forming dummy data wires adjacent to the data wires arranged in the outermost part of the display area in the non-display area; Forming a thin film transistor positioned at an intersection of the gate and the data line; Forming a pixel electrode on the pixel region; Forming a black matrix, a color filter, and a common electrode on one surface of the second substrate facing the first substrate; Forming a liquid crystal layer in the spaced space between the first substrate and the second substrate; It provides a liquid crystal display device manufacturing method comprising the step of forming a seal pattern to prevent leakage of the liquid crystal layer.

And a pad at each end of the gate and data lines and the dummy gate and data lines, wherein the thin film transistor comprises: forming a gate metal on a substrate; Sequentially forming a gate insulating film and an active layer on the gate metal; And forming source and drain electrodes spaced apart from each other on the active layer.

The dummy data line may be formed of the same material in the same process when the data line is formed, and the dummy gate line may be formed of the same material in the same process when the gate line is formed.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the drawings.

3 is a schematic plan view of a liquid crystal panel according to an exemplary embodiment of the present invention.

As shown, the liquid crystal panel includes a lower array substrate 111 and an upper color filter substrate 113, and the liquid crystal is filled between the two substrates 111 and 113.

In the display area AA on the array substrate 111, the data lines DL and the gate lines GL cross each other to define a pixel area P, and the gate lines GL and the data lines DL are defined. A thin film transistor (not shown) is formed at this intersection.

Color filters (not shown) separated by cell regions are formed on the color filter substrate 113 by the black matrix 115, and a common electrode (not shown) is formed on the color filter.

In addition, the black matrix 115 is formed at the edge between the two substrates, and a seal pattern 117 is formed to prevent leakage of the liquid crystal filled between the two substrates.

In this case, gate and data pads 119 and 125 connected to the gate and data lines GL and DL are formed in a non-display area on one side of the array substrate 111 having the gate and data lines GL and DL. Pad portions DPA and GPA are formed.

In addition, dummy gates and data lines 155 and 161 may be further formed outside the gates and data lines GL and DL formed at the outermost sides of the display area AA of the liquid crystal panel.

The dummy gate and the data pads 151 and 157 are formed at one end of the dummy gate and the data lines 155 and 161.

At this time, although not shown, the gate and data lines GL and DL are connected to gate and data driving circuits, which are external circuits, to receive display control signals and data signals.

In addition, the dummy gate and data lines 155 and 161 are also connected to the gate and data driving circuits, which are external circuits, to receive a predetermined signal applied to the dummy gate and data lines 155 and 161.

In this case, the dummy gate and the data wirings 155 and 161 receive a signal through an extra dummy pin of the gate and data driving circuit.

FIG. 4 is a schematic enlarged view of the gate and data pad part and the gate and data wiring of FIG. 3.

As illustrated, gate and data pads 119 and 125 are formed on the liquid crystal panel to receive a predetermined signal from an external driving circuit and apply the predetermined signal to the gate and the data lines GL and DL.

The data lines DL and the gate lines GL, which are connected to the gate and the data pads 119 and 125, cross each other in a matrix to define red, green, and blue pixels P, and the liquid crystal cell is disposed at the intersection. These transistors are formed to form a thin film transistor T composed of a gate electrode, a source and a drain electrode.

In this case, the gate and data lines GL and DL are formed in the display area AA, and dummy is formed outside the gate and data lines GL and DL formed at the outermost part of the display area AA of the liquid crystal panel. Gate and data lines 155 and 161 are formed in a non-display area that is an area other than the display area AA.

The dummy gates and the data lines 155 and 161 are connected to the dummy gates and the data pads 151 and 157, and the dummy gates and the data pads 151 and 157 connect dummy pins of external gates and data driving circuits. Through a certain signal is received.

The gate and data pads 119 and 125 and the dummy gate and data pads 151 and 157 are configured in a non-display area of the liquid crystal panel, and the gate and data wirings GL and DL are formed in the display area of the liquid crystal panel. The dummy gate and the data lines 155 and 161 are configured in the non-display area of the liquid crystal panel.

In this case, a black matrix 115 is formed on the red, green, and blue pixel P boundary of the color filter substrate 113 and the edge of the color filter substrate 113, and the dummy gate and the data wirings 155 and 161. It is also located on the pads 151 and 157.

As described above, the dummy gate and data lines 155 and 161 and the dummy gate and data pads 151 and 157 are formed to form the gate and data lines GL and DL formed at the outermost portion of the display area AA. ) Have the same environment as the gate and data lines GL and DL formed in the center of the display area AA.

That is, each of the gates and data pads 119, 125, 151, and 157 receives a gate and a data signal for controlling the thin film transistor T from an external driving circuit, and the gates and data pads 119, 125, 151, and 157 receive the gate and data signals from the external driving circuit. And a predetermined signal is supplied to the data lines GL and DL and also applied to the dummy gates and the data lines 155 and 161 formed in the non-display area.

As a result, the gate and data lines GL and DL formed at the outermost sides of the display area AA are electrically affected by the dummy gates and data lines GL and DL that are adjacent to each other symmetrically. The gate and data lines GL and DL formed at the center portion of the display area AA may have the same environment as those electrically affected by the gate and data lines GL and DL that are symmetrically adjacent to each other.

In addition, the dummy gate and data wirings 155 and 161 may be connected to the ground wirings (not shown) of the non-display area of the liquid crystal panel and the gate and data wirings GL and DL disposed at the outermost sides of the display area AA. The gate and data lines GL and DL disposed at the outermost portion of the display area AA are not affected by the ground line (not shown).

5 is a cross-sectional view taken along the line VV of FIG. 4.

As shown, the liquid crystal panel includes a display area AA in which an image is displayed and a gate connected to an external driving circuit and a data pad 129 (not shown) to apply a signal to the display area AA. And a non-display area NA having a data pad part GPA (not shown).

In the display area AA, the lower array substrate 111 forms a gate electrode 131 on a transparent substrate, and then a gate insulating layer 133 and an active layer on the substrate 111 on which the gate electrode 131 is formed. The thin film transistor T is formed by sequentially forming the 135 and 137 and the source and drain electrodes 139a and 139b.

Next, the protective layer 141 is formed on the entire surface of the substrate 111, and then the pixel electrode 143 in contact with the drain electrode 139b is formed.

A gate and a data pad 129 (not shown) connected to a gate and a data line GL (not shown) are formed in the non-display area NA of the array substrate, and a gate insulating layer formed on the gate line 125 is formed. 133, the dummy data wiring 155 is further formed.

At this time, although not shown, the dummy data wiring 155 and the pad are formed of the same material in the same process when the data wiring and the data pad are formed, and the dummy gate wiring and the pad are formed in the same process as the gate wiring and the gator pad forming process. Form the same material.

Meanwhile, a black matrix 115 having a lattice shape and a color filter 149 are formed in a region corresponding to the pixel region P on one surface of the color filter substrate 113 facing the array substrate 111. The planarization layer 147 is formed to eliminate the step between the color filter 149 and the black matrix 115.

The transparent common electrode 145 is formed on the planarization layer 147.

The black matrix 115 is formed at a position corresponding to the thin film transistor T of the array substrate 111. In addition, in the non-display area NA, the black matrix 115 is formed of the gate and data pad units GPA (not shown). It is located in the upper portion, the dummy gate and data wiring (not shown, 155), the dummy gate and the data pad unit (not shown).

A gap for forming liquid crystal is formed between the array substrate 111 and the color filter substrate 113 of the non-display area NA, and a seal pattern 117 is formed to prevent leakage of the injected liquid crystal. The color filter substrate 113 is disposed to face the array substrate 111 and the two substrates are bonded to each other.

Next, the liquid crystal layer 200 is formed in the spaced space between the array substrate 111 and the color filter substrate 113.

As described above, the dummy gate and the data line (not shown) 155 are disposed in the non-display area NA that is outside the gate and the data line GL (not shown) disposed at the outermost portion of the display area AA of the liquid crystal panel. By further arranging, it is possible to solve the problem that the luminance of the entire liquid crystal panel is not uniform due to defects such as edge brightness, which is the outermost defect of the liquid crystal panel, and brightness of the first gate wiring.

The present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention.

As described above, according to the present invention, the dummy gate and the data wiring which are adjacent to the outermost gate and the data wiring are formed in the non-display area that is outside the gate and the data wiring disposed in the outermost of the liquid crystal panel display region. By doing so, there is an effect that can solve the problems such as the edge bright or the first gate wiring bright that is the outermost defective liquid crystal panel.

In addition, this has the effect of making the light uniform throughout the liquid crystal panel.

Claims (11)

A first substrate divided into a display area and a non-display area; A gate wiring disposed in one direction of the display area on the first substrate; A data line crossing the gate line and defining a pixel area; A dummy gate line in the non-display area, the dummy gate line being positioned in parallel with the gate line formed at the outermost portion of the display area; A dummy data line in the non-display area, parallel to the data line configured at the outermost portion of the display area and defining a dummy pixel area crossing the dummy gate line; A thin film transistor positioned at an intersection of the gate and the data line; A pixel electrode on the pixel area; A black matrix, a color filter, and a common electrode formed on one surface of the second substrate facing the first substrate; A liquid crystal layer formed in the spaced space between the first substrate and the second substrate; Seal pattern to prevent leakage of the liquid crystal layer And a thin film transistor is not formed in the dummy pixel region. The method of claim 1, The thin film transistor is positioned at the intersection of the gate and the data line, and includes a gate electrode, a gate insulating layer, an active layer, and a source and a drain electrode. The method of claim 2, And the drain electrode is in contact with the pixel electrode. The method of claim 1, And the black matrix is arranged between the non-display area and the color filter. The method of claim 1, And the gate and data lines and the dummy gate and data lines receive a predetermined signal from a driving circuit. 6. The method of claim 5, The driving circuit may further include a dummy pin connected to the dummy gate and the data line. Defining a display area and a non-display area on the first substrate; Forming gate wirings in one direction on the display area on the first substrate; Forming a dummy gate wiring adjacent to the gate wiring disposed at the outermost portion of the display area in the non-display area; Forming a data line crossing the gate line to define a pixel area; Forming a dummy data line in the non-display area, the dummy data line being adjacent to the data line disposed at the outermost portion of the display area and crossing the dummy gate line to define a dummy pixel area; Forming a thin film transistor positioned at an intersection of the gate and the data line; Forming a pixel electrode on the pixel region; Forming a black matrix, a color filter, and a common electrode on one surface of the second substrate facing the first substrate; Forming a liquid crystal layer in the spaced space between the first substrate and the second substrate; Forming a seal pattern to prevent leakage of the liquid crystal layer; Wherein the thin film transistor is not formed in the dummy pixel region. The method of claim 7, wherein And a pad at each end of the gate and data lines and the dummy gate and data lines. The method of claim 7, wherein The thin film transistor may include forming a gate metal on a substrate; Sequentially forming a gate insulating film and an active layer on the gate metal; And forming source and drain electrodes spaced apart from each other on the active layer. The method of claim 7, wherein And the dummy data wirings are formed of the same material in the same process when the data wirings are formed. The method of claim 7, wherein And the dummy gate wirings are formed of the same material in the same process when the gate wirings are formed.

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