KR101171184B1 - Display device - Google Patents

Abstract

According to an aspect of the present invention, a display device including a plurality of pixels arranged in a matrix form and including first and second subpixels, respectively, is connected to the first and second subpixels. A plurality of first and second connection lines connected to the first and second gate lines and the first and second gate lines, respectively, having a first portion and a second portion;

And wiring resistances of the plurality of first connection lines are the same, and wiring resistances of the plurality of second connection lines are the same.

As described above, when the resistances of the wirings of the pair of two connection lines are different, the odd-numbered connection lines are the same in the odd-numbered connection lines and the even-numbered connection lines are made the same in the even-numbered connection lines to make the resistance of the wiring the same.

Display, sub-pixel, fan-out, etc.

Description

Display device {DISPLAY DEVICE}

With reference to the accompanying drawings will be described in detail the embodiments of the present invention to make the present invention clear.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2A and 2B are equivalent circuit diagrams of one pixel of the liquid crystal display according to the exemplary embodiment of the present invention.

3 is an equivalent circuit diagram of one subpixel of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a schematic layout view of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 5 is an enlarged layout view of a part of the connecting line illustrated in FIG. 4.

<Description of Drawing>

3: liquid crystal layer 100: lower display panel

200: upper panel 300: liquid crystal panel assembly

400: gate driver 410: gate FPC

420: gate lead line 430a, 430b: connecting line

440: gate driver IC 500: data driver

510: data FPC 520: data leader

550: PCB 600: signal control unit

R, G, B: Input image data DE: Data enable signal

MCLK: Main Clock Hsync: Horizontal Sync Signal

Vsync: Vertical Sync Signal CONT1: Gate Control Signal

CONT2: data control signal DAT: digital video signal

PX: Pixel PXa, PXb: Subpixel

Clc: Liquid Crystal Capacitor Cst: Keeping Capacitor

Q: switching element SL: sustain electrode wire

DL, 171: data line GL, 121: gate line

PE: pixel electrode CF: color filter

CE: common electrode

The present invention relates to a display device.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two display panels on which field generating electrodes such as a pixel electrode and a common electrode are formed, and a liquid crystal layer interposed therebetween. Is applied to generate an electric field in the liquid crystal layer, thereby determining the orientation of liquid crystal molecules in the liquid crystal layer and controlling the polarization of incident light to display an image.

Meanwhile, the liquid crystal display includes a display panel including a pixel including a switching element and a display signal line, a gray voltage generator to generate a gray reference voltage, and a plurality of gray voltages by using the gray reference voltages. And a data driver for applying a gray scale voltage corresponding to the video signal to the data lines of the display signal lines.

In addition, among the liquid crystal display devices, the vertical alignment mode liquid crystal display in which the long axes of the liquid crystal molecules are arranged perpendicular to the upper and lower display panels without an electric field applied to the liquid crystal display device has a high contrast ratio and is easy to implement a wide reference viewing angle. Here, the reference viewing angle refers to a viewing angle having a contrast ratio of 1:10 or a luminance inversion limit angle between gray levels.

Means for implementing a wide viewing angle in a vertical alignment mode liquid crystal display include a method of forming a cutout in the field generating electrode and a method of forming a protrusion on the field generating electrode. Since the inclination and the projection can determine the direction in which the liquid crystal molecules are tilted, the reference viewing angle can be widened by using these to disperse the oblique directions of the liquid crystal molecules in various directions.

However, the liquid crystal display of the vertical alignment type has a problem in that the side visibility is inferior to the front visibility. For example, in the case of a patterned vertically aligned (PVA) type liquid crystal display device having an incision, the image becomes brighter toward the side, and in a severe case, the luminance difference between the high grays disappears and the picture may appear clumped.

To solve this problem, one pixel is divided into two subpixels, two subpixels are capacitively coupled, and one subpixel is directly applied with voltage, and the other subpixel causes voltage drop due to capacitive coupling. A method of changing the transmittances by changing the voltages of the two subpixels has been proposed.

On the other hand, the driving circuit is positioned near the edge of the display device and is connected to the end of the signal line. For this connection, the end of the signal line is concentrated in a narrow area (hereinafter referred to as a connection area). On the other hand, in an area where pixels are located (hereinafter referred to as a display area), signal lines need to maintain intervals determined according to pixel sizes, and thus, line intervals are larger than those of ends connected to the driving circuit. Therefore, in the area between the display area and the connection area, there is a fan-out area in which the distance between the signal lines is gradually widened (or narrowed) in the shape of a side chatter.

The signal lines located near the center of the fan out area are almost straight without changing direction, but the angle at which the signal lines are bent increases toward the edge of the fan out area. Due to this structure, the signal lines have different lengths, and thus the resistance values of the signal lines are also different, thereby degrading the image quality.

In addition, as described above, when one pixel includes two subpixels, two gate lines are connected to one pixel, and the thicknesses and widths of the two gate lines may be different so that the resistance of the gate lines positioned above and below may be different. .

Accordingly, an object of the present invention is to provide a display device that can solve the problems of the prior art.

According to an aspect of the present invention, a display device including a plurality of pixels arranged in a matrix form and including first and second subpixels, respectively, is connected to the first and second subpixels, respectively. First and second gate lines, and a plurality of first and second connection lines respectively connected to the first and second gate lines and having a first portion and a second portion, wherein the plurality of first connection lines are connected to each other. Wiring resistance is the same, and wiring resistance of said 2nd some connection line is the same.

In this case, the first portion of the first and second connection lines may have a curved shape, and the second portion may have a straight shape.

The display device may include a connection area in which the first and second connection lines are located and a display area in which the first and second gate lines are located, and the connection area includes the first and second subpixels. The gate driving integrated circuit may be disposed to generate a gate signal applied to the gate signal.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

Next, the gray voltage generator and the display device including the same according to the exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings. The liquid crystal display will be described as an example.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, FIGS. 2A and 2B are equivalent circuit diagrams of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. An equivalent circuit diagram of one subpixel of a liquid crystal display according to an exemplary embodiment is shown.

Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver 500 connected thereto. And a gray voltage generator 800 connected to the signal, and a signal controller 600 for controlling the gray voltage generator 800.

The liquid crystal panel assembly 300 includes a plurality of display signal lines and a plurality of pixels PX connected to the display signal lines and arranged in a substantially matrix form when viewed in an equivalent circuit. In contrast, in the structure shown in FIG. 3, the liquid crystal panel assembly 300 includes a lower and upper panel 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The display signal line is provided in the lower panel 100, and includes a plurality of gate lines G _1a -G _nb transmitting the gate signals (also called “scan signals”) and data lines D ₁ -D transferring the data signals. _m ). The gate lines G _1a -G _nb extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

2A and 2B show an equivalent circuit of a display signal line and a pixel. In addition to the gate line indicated by reference numerals GLa and GLb and the data line indicated by reference numeral DL, the display signal lines are substantially parallel to the gate lines G ₁ -G _2b . The extended sustain electrode line SL is included.

Referring to FIG. 2A, each pixel PX includes a pair of subpixels PXa and PXb, and each of the subpixels PXa and PXb has a corresponding gate line GLa and GLb and a data line DL. Switching elements Qa and Qb connected thereto and liquid crystal capacitors Clca and Clcb connected thereto, and storage capacitors connected to switching elements Qa and Qb and sustain electrode lines SL. (Csta, Cstb). The storage capacitors Csta and Cstb may be omitted as necessary, and in this case, the storage electrode line SL is also unnecessary.

Referring to FIG. 2B, each pixel PX includes a pair of subpixels PXa and PXb and coupling capacitors Ccp connected therebetween, and each subpixel PXa and PXb has a corresponding gate line. And switching elements Qa and Qb connected to the GLa and GLb and data lines DL, and liquid crystal capacitors Clca and Clcb connected thereto. One of the two subpixels PXa and PXb includes a storage capacitor Csta connected to the switching element Qa and the storage electrode line SL.

Referring to FIG. 3, the switching elements Q of each of the subpixels PXa and PXb are formed of a thin film transistor or the like provided on the lower panel 100, and each of the control terminals connected to the gate line GL; A three-terminal device having an input terminal connected to the data line DL and an output terminal connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

The liquid crystal capacitor Clc has two terminals, the subpixel electrode PE of the lower panel 100 and the common electrode CE of the upper panel 200, and the liquid crystal layer 3 between the two electrodes PE and CE It functions as a dielectric. The subpixel electrode PE is connected to the switching element Q, and the common electrode CE is formed on the entire surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 3, the common electrode CE may be provided in the lower panel 100. In this case, at least one of the two electrodes PE and CE may be formed in a linear or bar shape.

The storage capacitor Cst serving as an auxiliary role of the liquid crystal capacitor Clc is formed by overlapping the storage electrode line SL and the pixel electrode PE provided in the lower panel 100 with an insulator interposed therebetween. ), A predetermined voltage such as the common voltage Vcom is applied. However, the storage capacitor Cst may be formed by the subpixel electrode PE overlapping the front gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel uniquely displays one of the primary colors (spatial division) or each pixel alternately displays three primary colors over time (time division) so that the spatial and temporal combinations of these three primary colors can be achieved. To recognize the desired color. Examples of primary colors include red, green and blue. 3 illustrates an example of spatial division, in which each pixel includes a color filter CF representing one of primary colors in an area of the upper panel 200. Unlike FIG. 3, the color filter CF may be formed above or below the subpixel electrode PE of the lower panel 100.

Referring to FIG. 1, the gate driver 400 is connected to the gate lines G _1a -G _nb to receive a gate signal formed by a combination of a gate on voltage Von and a gate off voltage Voff from the outside. G _1a -G _nb ).

The gray voltage generator 800 generates two sets of gray reference voltages related to the transmittance of the pixel. Two sets of gray reference voltages may be independently provided to two subpixels constituting one pixel, and each set of gray reference voltages includes a positive value and a negative value with respect to the common voltage Vcom. However, instead of two reference gray voltage sets, only one gray reference voltage set may be generated.

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 to divide the gray reference voltage from the gray voltage generator 800 to generate gray voltages for the entire gray levels. Select the data voltage from the list.

The signal controller 600 controls operations of the gate driver 400 and the data driver 500.

Each of the driving devices 400, 500, 600, and 800 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or may be a flexible printed circuit film (not shown). It may be mounted on the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP) or mounted on a separate printed circuit board (not shown). In contrast, these driving devices 400, 500, 600, and 800 are connected to the liquid crystal panel assembly 300 together with the signal lines G _1a -G _nb , D ₁ -D _m and the thin film transistor switching elements Qa and Qb. It may be integrated. In addition, the driving devices 400, 500, 600, and 800 may be integrated into a single chip, in which case at least one of them or at least one circuit element constituting them may be outside the single chip.

The display operation of such a liquid crystal display device will now be described in detail.

The signal controller 600 is configured to control the input image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical synchronization signal Vsync and a horizontal synchronization signal ( Hsync, main clock MCLK, and data enable signal DE are provided. Based on the input image signals R, G and B of the signal controller 600 and the input control signals, the image signals R, G and B are properly processed according to the operating conditions of the liquid crystal panel assembly 300, and the gate control signal After generating the CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver 500. Export to

The gate control signal CONT1 includes a scan start signal STV indicating the start of scanning and a clock signal CPV controlling the output time of the gate-on voltage Von.

The data control signal CONT2 is a horizontal synchronization start signal STH for transmitting data to a group of pixels PX and a load signal LOAD for applying a corresponding data voltage to the data lines D ₁ -D _m . And a data clock signal HCLK. The data control signal CONT2 may also include an inversion signal RVS that inverts the polarity of the data voltage relative to the common voltage Vcom (hereinafter referred to as the polarity of the data voltage by reducing the polarity of the data voltage for the common voltage). Can be.

In response to the data control signal CONT2 from the signal controller 600, the data driver 500 receives the digital image data DAT for the bundle of subpixels PX, and applies the digital image data DAT to each digital image signal DAT. By selecting the corresponding gray voltage, the digital image signal DAT is converted into an analog data signal, and then applied to the corresponding data lines D ₁ -D _m .

The gate driver 400 applies the gate-on voltage Von to the gate lines G _1a -G _nb in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G _1a -G _nb . Turns on the switching elements Qa and Qb connected thereto, so that the data voltages applied to the data lines D ₁ -D _m are applied to the corresponding subpixels PXa and PXb through the turned-on switching elements Qa and Qb. Is approved.

The difference between the data voltage applied to the subpixels PXa and PXb and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitor Clc, that is, the pixel voltage. The liquid crystal molecules have different arrangements according to the magnitude of the pixel voltage, and thus the polarization of light passing through the liquid crystal layer 3 changes. The change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the display panels 100 and 200.

The data driver 500 and the gate driver 400 perform the same operation in units of 1/2 horizontal periods (or "1/2 H") (one period of the horizontal sync signal Hsync and the gate clock CPV). Repeat. In this manner, the gate-on voltages Von are sequentially applied to all the gate lines G _1a -G _nb during one frame to apply data voltages to all the pixels. At the end of one frame, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each pixel is opposite to that of the previous frame ("frame inversion). "). In this case, the polarities of the data voltages flowing through one data line change according to the characteristics of the inversion signal RVS within one frame (eg, row inversion and point inversion), or polarities of data voltages flowing through adjacent data lines at the same time. Can be different (eg invert columns, invert points).

Next, a display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 4 and 5.

4 is a schematic diagram of a display device according to an exemplary embodiment of the present invention, and FIG. 5 is an enlarged layout view of the fan out area illustrated in FIG. 4.

In FIG. 4, gate lines G _1a -G _nb are denoted by reference numeral '121', and data lines D ₁ -D _m are denoted by reference numeral '171'.

As shown in FIG. 4, the display device according to an exemplary embodiment includes a display panel 300, a plurality of gate FPC substrates 410 and a plurality of data FPC substrates 510 attached thereto. And a printed circuit board (PCB) 550 attached to the data FPC board 510.

A gate driver integrated circuit (IC) 440 and a data driver integrated circuit 540 are mounted in the form of a chip on the gate FPC board 410 and the data FPC board 510, respectively. , 540 and leader lines 420 and 520 for electrical connection with the outside are formed. The FPC substrates 410 and 510 are made of polyimide or polyester.

The printed circuit board 550 includes various circuit elements for driving and controlling the liquid crystal panel assembly 300. For example, the signal controller 600 and the gray voltage generator 800 illustrated in FIG. 1 are mounted on the PCB 550. These circuit elements are connected to the data driving integrated circuit 540 through a signal line (not shown) provided on the printed circuit board 550 and a lead line 520 and a connection line of the data FPC board 510. The electrical connection between the integrated circuit 440 and the printed circuit board 550 may include a signal line (not shown) separately provided on the data FPC board 510 and the lower panel 100 and a lead line of the gate FPC board 410. 420 and connecting lines 430a and 430b, and the leader lines 420 and 520 are made of a material such as copper having a relatively low resistance. Alternatively, the driving integrated circuits 440 and 550 may be directly mounted on the lower panel 100 of the display panel unit 300, in which case the gate FPC substrate 410 is not necessary.

The lower panel 100 of the display panel unit 300 is positioned on and outside the display area D in which the array of pixel electrodes 190 is disposed, and the display signal lines 121 and 171 and the FPC substrates 410 and 510. Or a peripheral area in which physical and electrical connections with the driving integrated circuits 440 and 540 are made.

The display signal lines 121 and 171 are connected to the pixel electrode 190 through the switching element Q in the display area D, and are substantially parallel to each other, and the ends of the signal lines 121 and 171 positioned in the peripheral area. The portion is connected to the FPC substrates 410 and 510 or the drive integrated circuits 440 and 540. However, in the case of the display device illustrated in FIG. 4, the gap between the lead lines 420 of the FPC boards 410 and 510 for the connection between the driving integrated circuits 440 and 540 and the display signal lines 121 and 171 is represented in the display area. Since the distance between the signal lines 121 and 171 in the peripheral area is gradually changed as compared with the interval between the display signal lines 121 and 171 in (D), an area in which the signal lines 121 and 171 are arranged in a fan shape (hereinafter, referred to as &quot; a &quot; (F) is called a fan-out area.

5 illustrates a final region of the fan out region in which the gate driving integrated circuit 440 is located.

The fan out area includes a pair of connection lines 430a and 430b connected to a pair of gate lines Gia, Gib, ... Gna, and Gnb, respectively, and each of the connection lines 430a and 430b is a gate FPC. A front connection line 430p connected to the substrate 410 and a rear connection line 430q connected to the gate line Gia-Gnb of the display area D are included. At this time, the front end connection line (430p) is repeated in a curved shape and the rear end connection line (430q) extends in a straight line, the curved shape increases toward the center of the front connection line (430p), while the straight distance of the rear connection line (430q) Decreases. In this way, the lengths of the connection lines 430a and 430b can be compensated for to some extent as the lengths of the connection lines 430a and 430b go to the edges due to the fan out, and the resistances of the wirings can be made the same by making the overall lengths of the connection lines 430a and 430b the same.

In this case, the connecting line 430a is represented by a thin solid line, and the connecting line 430b is represented by a thick solid line, which is considered in view of the difference in voltage applied to the two subpixels PXa and PXb. Since the width and the thickness of the two pairs of wires (430a, 430b) indicates that the wiring resistance may be different. In this case, the connection lines 430a connected to the gate lines Gia, Gja, .., Gna connected to the subpixel PXa are connected to the connection lines 430a, and the gate lines Gib, Gjb, connected to the subpixel PXb. The connecting line 430b connected to the Gnb) may be made to match the resistance of the wiring to the connecting line 430b. In other words, the odd-numbered connecting lines 430a may have the same length as the odd-numbered connecting lines and the even-numbered connecting line 430b may have the same length between the even-numbered connecting lines.

As described above, when the resistances of the wirings of the pair of two connection lines 430a and 430b are different, the odd-numbered connection lines have the same length and the even-numbered connection lines have the same length. do.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (6)

A display device including a plurality of pixels arranged in a matrix and each including first and second subpixels. A plurality of first and second gate lines respectively connected to the first and second subpixels, and A plurality of first and second connection lines respectively connected to the first and second gate lines and having a first portion and a second portion; / RTI &gt; The first portion of the first and second connecting line has a curved shape of different lengths, The second portion of the first and second connecting line has a straight shape of different lengths, The wiring resistances of the plurality of first connection lines are the same, and the wiring resistances of the plurality of second connection lines are the same. Display device. delete delete In claim 1, And a display area in which the first and second connection lines are located, and a display area in which the first and second gate lines are located. In claim 4, And a gate driving integrated circuit configured to generate gate signals applied to the first and second subpixels in the connection region. In claim 1, As the first portion of the first and second connection lines is located at the center of the plurality of first and second connection lines, the curved shape increases. The second portion of the first and second connecting line is shorter in length as it is located in the center of the plurality of first and second connecting lines, Display device.

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