KR101137848B1 - Apparatus and method for driving flat panel dispaly device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving apparatus and a driving method of a flat panel display apparatus which can control image quality by recognizing image information according to pixel positions of an image displayed on a display apparatus and correcting an image signal input to the display apparatus. According to an aspect of the present invention, there is provided a driving apparatus of a flat panel display, comprising: a display unit which displays an image by using a scan pulse supplied to a gate line and a video data signal supplied to a data line; A data driver for supplying the video data signal to the data lines; A gate driver for supplying the scan pulses to the gate lines; A timing controller for aligning input source data and generating data and gate control signals for controlling the data driver and the gate driver; A memory matrix for storing the aligned data according to an address signal and supplying the stored data to the timing controller according to a pixel read signal; The timing controller generates the address signal using the data control signal and the gate control signal, and corrects the data supplied from the memory matrix according to the pixel read signal to supply the data driver.

Memory Matrix, Registers, SSP, SOE, GSP, GSC, Address Signals

Description

Driving apparatus and driving method of flat panel display device {APPARATUS AND METHOD FOR DRIVING FLAT PANEL DISPALY DEVICE}

1 is a view schematically showing a driving device of a liquid crystal display according to the related art.

FIG. 2 shows the timing controller shown in FIG. 1; FIG.

FIG. 3 is a waveform diagram illustrating source data input to the timing controller shown in FIG. 1. FIG.

FIG. 4 is a waveform diagram illustrating a data signal input to a data driver from the timing controller shown in FIG. 1. FIG.

5 is a schematic view of a driving device of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 6 illustrates the timing controller shown in FIG. 1; FIG.

FIG. 7 is a diagram illustrating an address signal generator shown in FIG. 6; FIG.

8 is a diagram illustrating a data correction unit illustrated in FIG. 6.

FIG. 9 is an illustration of the memory matrix shown in FIG. 5; FIG.

FIG. 10 is a block diagram illustrating the gate driver shown in FIG. 5. FIG.

FIG. 11 is a waveform diagram showing driving waveforms of the gate driver shown in FIG. 10; FIG.

FIG. 12 is a block diagram showing a data driver shown in FIG. 5; FIG.

FIG. 13 is a waveform diagram showing drive waveforms of the data driver shown in FIG. 12; FIG.

FIG. 14 is a waveform diagram illustrating driving waveforms supplied to the liquid crystal panel illustrated in FIG. 5.

<Explanation of Signs of Major Parts of Drawings>

2, 102 liquid crystal panel 4, 104 data driver

6, 106: gate driver 8, 108: timing controller

10, 110: voltage generator 20, 120: data processor

30, 130: data control signal generator 40, 140: gate control signal generator

109: memory matrix 122: data alignment unit

124: data correction unit 126: address signal generation unit

200: storage unit 202, 252: register

240: data conversion unit 242: selection unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display device, and more particularly, to a device for driving a flat panel display device by recognizing image information according to pixel positions of an image displayed on a display device to correct image signals input to the display device. And a driving method.

Recently, various flat panel display devices that can reduce weight and volume, which are disadvantages of cathode ray tubes, have emerged. Examples of such flat panel display devices include a liquid crystal display, a field emission display, a plasma display panel, and a light emitting display.

Among the flat panel displays, the liquid crystal display displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel having a liquid crystal cell and a driving circuit for driving the liquid crystal panel. The driving circuit drives the liquid crystal cell so that the image information is displayed on the liquid crystal panel.

1 is a view showing a driving device of a liquid crystal display according to a related art.

Referring to FIG. 1, a driving apparatus of a liquid crystal display according to a related art is a liquid crystal including a liquid crystal cell formed for each pixel region defined by n gate lines GL1 to GLn and m data lines DL1 to DLm. A panel 2, a data driver 4 for supplying a video data signal to the data lines DL1 to DLm, a gate driver 6 for supplying scan pulses to the gate lines GL1 to GLn, and The input source data RGB is arranged and supplied to the data driver 4, the data control signal DCS is generated to control the driving timing of the data driver 4, and the gate control signal GCS is generated. A timing controller 8 for controlling the drive timing of the gate driver 6; A voltage generator 10 for generating a voltage required for driving the liquid crystal panel 2 and various driving voltages is provided.

The liquid crystal panel 2 includes a thin film transistor TFT formed in a region defined by n gate lines GL1 through GLn and m data lines DL1 through DLm, and liquid crystal cells connected to the thin film transistor TFT. Equipped. The thin film transistor TFT supplies a data signal from the data lines DL1 to DLm to the liquid crystal cell in response to a scan pulse from the gate lines GL1 to GLn. The liquid crystal cell is composed of a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to the thin film transistor TFT, so that the liquid crystal cell may be equivalently represented as a liquid crystal capacitor Clc. The liquid crystal cell includes a storage capacitor Cst connected to the previous gate line to maintain the data signal charged in the liquid crystal capacitor Clc until the next data signal is charged.

The voltage generator 10 uses a voltage inputted from the outside to drive the liquid crystal panel 2, that is, a common voltage Vcom, a gate high voltage VGH, and a gate low voltage VGL. And so on. In addition, the voltage generator 10 generates a driving voltage VCC for driving the data driver 4, the gate driver 6, and the timing controller 8 by using an input power source Vin from the outside.

The timing controller 8 aligns the source data RGB supplied from the outside into a data signal Data suitable for driving the liquid crystal panel 2, and supplies the aligned data signal Data to the data driver 4. . In addition, the timing controller 8 uses the main clock MCLK, the data enable signal DE, and the horizontal and vertical synchronization signals Hsync and Vsync, which are input from the outside, to the data control signal DCS and the gate control signal ( GCS) is generated to control the driving timing of each of the data driver 4 and the gate driver 6.

To this end, as shown in FIG. 2, the timing controller 8 includes a data processor 20 for aligning source data RGB from the outside so as to be suitable for driving the liquid crystal panel 2, and a main clock from the outside. A data control signal generator 30 generating a data control signal DCS using the MCLK, the data enable signal DE, and the horizontal and vertical synchronization signals Hsync and Vsync, and a main clock input from the outside. And a gate control signal generator 40 for generating a gate control signal GCS using the MCLK and the horizontal and vertical synchronization signals Hsync and Vsync.

The gate control signal generator 40 uses a data enable signal DE, horizontal and vertical synchronization signals Hsync and Vsync, and includes a gate start pulse (GSP) and a gate shift clock (GSC). ) And a gate control signal GCS including a gate output enable (GOE) is supplied to the gate driver 6.

The data control signal generator 30 uses a main clock MCLK, a data enable signal DE, and horizontal and vertical synchronization signals Hsync and Vsync to generate a source start pulse SSP and a source shift clock. A data control signal DCS including a source shift clock SSC, a polarity signal POL, and a source output enable signal SOE is generated and supplied to the data driver 4.

The data processor 20 aligns the source data RGB from the outside to be suitable for driving the liquid crystal panel 2, and supplies the aligned data signal Data to the data driver 4 through a bus line.

In detail, the data processor 20 illustrates source data RGB input from the outside for each rising period of the main clock MCLK, as shown in FIG. 3, in order to reduce the driving frequency and reduce the power consumption. As shown in Fig. 4, the sample is divided into even data and odd data. The data processing unit 20 simultaneously outputs sampled even data and odd data to the data driver 4. Accordingly, the source shift clock SSC supplied from the data control signal generator 30 to the data driver 4 becomes half of the input main clock MCLK and at the same time the data signal supplied to the data driver 4 Data width is twice as large as the input source data RGB.

The gate driver 6 sequentially shifts the scan pulse, that is, the gate high pulse, in response to the gate start pulse GSP and the gate shift clock GSC among the gate control signals GCS from the timing controller 8. It includes. In response to this scan pulse, the thin film transistor TFT is turned on.

The data driver 4 converts even data and odd data from the timing controller 8 into a video data signal which is an analog signal according to the data control signal DCS supplied from the timing controller 8 to the gate lines GL1 through. A horizontal data line for one horizontal line is supplied to the data lines DL1 to DLm every one horizontal period in which the scan pulse is supplied to GLn. That is, the data driver 4 selects a gamma voltage having a predetermined level according to the gray value of the data signal Data, and supplies the selected gamma voltage to the data lines DL1 to DLm.

As described above, the driving device of the liquid crystal display according to the related art controls the video data signal supplied to the liquid crystal panel 102 by supplying the data signal Data to the data driver 104 directly from the timing controller 108. It becomes impossible.

The driving device of the flat panel display device according to the related art including the liquid crystal display device is an effective image because the characteristics of the data signal (Data) displayed for each display device such as a liquid crystal display device, a plasma display panel and a light emitting display device are all different. For display, correction of the data signal Data input to the display device is required.

Accordingly, in order to solve the above problems, the present invention is to provide a flat panel display device that can control image quality by recognizing image information according to pixel position of an image displayed on a display device and correcting an image signal input to the display device. It is to provide a driving device and a driving method.

According to an aspect of the present invention, there is provided a driving apparatus of a flat panel display, including: a display unit configured to display an image by using a scan pulse supplied to a gate line and a video data signal supplied to a data line; A data driver for supplying the video data signal to the data lines; A gate driver for supplying the scan pulses to the gate lines; A timing controller for aligning input source data and generating data and gate control signals for controlling the data driver and the gate driver; A memory matrix for storing the aligned data according to an address signal and supplying the stored data to the timing controller according to a pixel read signal; The timing controller generates the address signal using the data control signal and the gate control signal, and corrects the data supplied from the memory matrix according to the pixel read signal to supply the data driver.

A driving method of a flat panel display device according to an exemplary embodiment of the present invention includes a display unit for displaying an image using a scan pulse supplied to a gate line and a video data signal supplied to a data line; A data driver for supplying the video data signal to the data lines; A method of driving a flat panel display device including a gate driver for supplying the scan pulses to the gate lines, the method comprising: generating data and gate control signals for controlling the data driver and the gate driver; Arranging source data to be suitable for driving the display unit, generating the address signal using the data control signal and the gate control signal, and storing the aligned data according to the address signal in a memory matrix. And reading data from the memory matrix according to the pixel read signal, correcting the read data, and supplying the read data to the data driver.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings and embodiments.

5 is a diagram illustrating a driving device of a liquid crystal display among flat panel displays according to an exemplary embodiment of the present invention.

Referring to FIG. 5, a driving device of a liquid crystal display according to an exemplary embodiment of the present invention may include a liquid crystal cell formed for each pixel area defined by n gate lines GL1 to GLn and m data lines DL1 to DLm. A liquid crystal panel (or display portion) 102 including; A data driver 104 for supplying a video data signal to the data lines DL1 to DLm; A gate driver 106 for supplying scan pulses to the gate lines GL1 through GLn; The input source data RGB is arranged and supplied to the data driver 104, the data control signal DCS is generated to control the driving timing of the data driver 104, and the gate control signal GCS is generated. A timing controller 108 for controlling the drive timing of the driver 106; A memory matrix 109 for storing data CData arranged according to the address signal AS and supplying data CData of an address value corresponding to the pixel read signal PRS to the timing controller 108; A voltage generator 110 for generating a voltage necessary for driving the liquid crystal panel 102 and various driving voltages; The timing controller 108 generates an address signal AS using the gate control signal GCS and the data control signal DCS to store the aligned source data RGB in the memory matrix 109. The data CData stored in the address value corresponding to the read signal PRS may be supplied from the memory matrix 109 to be corrected and supplied to the data driver 104.

The liquid crystal panel 102 includes a thin film transistor TFT formed in a region defined by n gate lines GL1 through GLn and m data lines DL1 through DLm, and a liquid crystal connected to the thin film transistor TFT. With cells. The thin film transistor TFT supplies a data signal from the data lines DL1 to DLm to the liquid crystal cell in response to a scan pulse from the gate lines GL1 to GLn. The liquid crystal cell is composed of a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to the thin film transistor TFT, so that the liquid crystal cell may be equivalently represented as a liquid crystal capacitor Clc. The liquid crystal cell includes a storage capacitor Cst connected to the previous gate line to maintain the data signal charged in the liquid crystal capacitor Clc until the next data signal is charged.

The voltage generation unit 110 uses a voltage required for driving the liquid crystal panel 102 using the input power Vin input from the outside, that is, the common voltage Vcom, the gate high voltage VGH, and the gate low voltage VGL. And so on. In addition, the voltage generator 110 generates a driving voltage VCC for driving the data driver 104, the gate driver 106, and the timing controller 108 by using an input power source Vin from the outside.

The timing controller 108 stores the source data RGB supplied from the outside in the memory matrix 109 in alignment with the driving of the liquid crystal panel 102 and uses the stored data from the memory matrix 109. Correction is performed according to the pixel position of 102 to supply to the data driver 104. In addition, the timing controller 108 uses the main clock MCLK, the data enable signal DE, and the horizontal and vertical synchronization signals Hsync and Vsync, which are input from the outside, to control the data control signal DCS and the gate control signal ( GCS) is generated to control driving timing of each of the data driver 104 and the gate driver 106.

To this end, as shown in FIG. 6, the timing controller 108 aligns and corrects the source data RGB from the outside so as to be suitable for driving the liquid crystal panel 102, and from the outside. A data control signal generator 130 for generating a data control signal DCS using a main clock MCLK, a data enable signal DE, and horizontal and vertical synchronization signals Hsync and Vsync. The gate control signal generator 140 generates a gate control signal GCS using the main clock MCLK and the horizontal and vertical synchronization signals Hsync and Vsync.

The gate control signal generator 140 uses a gate signal, a gate start pulse (GSP), and a gate shift clock (GSC) using a data enable signal DE, horizontal and vertical synchronization signals Hsync, and Vsync. ) And a gate control signal GCS including the gate output enable (GOE) is supplied to the gate driver 106. In this case, the gate control signal generator 140 generates a gate start pulse GSP indicating the start of a frame based on the vertical synchronization signal Vsync, and generates a gate shift clock GSC based on the horizontal synchronization signal Hsync. Will be generated.

The data control signal generator 130 uses a main clock (MCLK), a data enable (DE) signal, horizontal and vertical synchronization signals (Hsync, Vsync), and a source start pulse (SSP) and a source shift clock. (Source Shift Clock: SSC), Polarity (POL) and Source Output Enable (SOE) signals (or Data Control Signals (DCS) including Load signal (Gen) to generate a data driver ( In this case, the data control signal generation unit 130 generates a source start pulse SSP indicating a start of a line based on a data enable signal indicating a valid data period among all the lines. In addition, a source output enable (SOE) signal for informing the output of the data driver 104 is generated based on the horizontal synchronization signal Hsync.

The data processing unit 120 includes a data alignment unit 122 for aligning source data RGB from the outside to be suitable for driving the liquid crystal panel 102; Using the gate control signal GCS and the data control signal DCS, an address signal AS for storing the data AData aligned by the data alignment unit 122 at a designated position of the memory matrix 109 is generated. An address signal generator 124; And a data corrector 126 that receives and corrects data CData stored in the memory matrix 109 and supplies one of the corrected data and the aligned data to the data driver 104.

In order to reduce the driving frequency and reduce power consumption, the data aligning unit 122 receives even and odd data from the source data RGB input from the outside for each rising period of the main clock MCLK. Divide by and sample and sort. Accordingly, the source shift clock SSC supplied from the data control signal generator 130 to the data driver 104 becomes half of the input main clock MCLK and at the same time the data signal supplied to the data driver 104 Data width is twice as large as the input source data RGB.

As illustrated in FIG. 7, the address signal generator 124 sequentially stores the gate control signal GCS and the data control signal DCS to sequentially store the storage 200 and an output signal from the storage 200. A logic product gate 210 for performing AND logic operation on Vreg and the reference signal Vref, and a counter 220 for generating an address signal AS by counting an output signal from the AND gate 210. ).

The storage unit 200 receives one of the gate control signal GCS and the data control signal DCS and stores them sequentially to form one register 202. In this case, the data control signal DCS supplied to the storage 200 is a source output enable signal SOE and a source shift clock SSC. The gate control signal GCS supplied to the storage 200 is a gate output signal GOE and a gate shift clock GSC. Accordingly, the storage unit 200 outputs the output signal Vreg of '1111' when the source output enable signal SOE, the source shift clock SSC, the gate output signal GOE, and the gate shift clock GSC are normally supplied. ) Is supplied to the AND gate 210.

The AND gate 210 performs an AND operation on the output signal Vreg from the storage 200 and the reference signal Vref of '1111' and outputs the AND to the counter 220.

The counter 220 counts the output signal from the AND gate 210 according to the counter signal CS input from the outside to generate the address signal AS. At this time, the counter signal CS drives the counter 220 and controls on / off of the memory matrix 109. The address signal AS generated by the counter 220 becomes an address value of the memory matrix 109.

As illustrated in FIG. 8, the data correction unit 126 converts a data that receives and corrects data CData stored at an address value corresponding to the pixel read signal PRS among data CData stored in the memory matrix 109. A selection unit for selecting one of the unit 240 and the alignment data (AData) from the data alignment unit 122 and the corrected data (MData) from the data conversion unit 240 to supply the data driver 104 to the data driver 104. 242.

The data converter 240 corrects the gray value of the data CData supplied from the memory matrix 109 according to the pixel read signal PRS and supplies it to the selector 242. That is, the data converter 240 stores the data stored in the memory matrix 109 so as to correspond to the address value of the pixel read signal PRS in order to change the luminance value of the pixel position corresponding to the pixel position on the liquid crystal panel 102. The correction data MData is generated by increasing or decreasing the gray scale value of the CData.

The selector 242 includes a first input terminal through which the alignment data AData is supplied from the data aligning unit 122, and a second input terminal through which the correction data MData is supplied from the data converter 240, and a pixel read signal ( And a control terminal to which the selection signal SS corresponding to the PRS is supplied. Accordingly, when the selector 242 corrects the data signal supplied to the liquid crystal panel 102 by the pixel read signal PRS according to the selection signal SS, the selector 242 selects the correction data MData and the data driver 104. ), Otherwise, the alignment data (AData) is selected and output to the data driver 104.

Meanwhile, as illustrated in FIG. 9, the memory matrix 109 includes a plurality of registers 252 for storing alignment data AData of one frame. Here, the memory matrix 109 may be embedded in the timing controller 108.

The plurality of registers 252 are turned on / off by the counter signal CS, and the alignment data from the data sorting unit 122 according to the address value corresponding to the address signal AS from the address signal generating unit 124. Stores (AData) sequentially. The memory matrix 109 supplies the storage data CData corresponding to the address value of the pixel read signal PRS to the data corrector 126. That is, the memory matrix 109 converts the stored data CData stored in the register 252 of the address value corresponding to the pixel read signal PRS according to the pixel read signal PRS. Supply to 240.

As such, the timing controller 108 corrects the gray value of the stored data CData supplied from the memory matrix 109 according to the pixel read signal PRS, thereby correcting the data signal corresponding to the pixel position of the liquid crystal panel 102. The luminance value is changed.

As illustrated in FIG. 9, the gate driver 106 includes a shift register 310 for generating a shift signal using a gate start pulse GSP and a gate shift clock GSC, and a gate from the voltage generator 110. The scan pulse is generated using the high voltage VGH, the gate low voltage VGL, and the shift signal from the shift register 310, and the generated scan pulse is converted into a scan pulse of the liquid crystal panel 102 according to the gate output signal GOE. And a level shifter 320 for outputting to the gate line GL.

The shift register 310 generates a sequential shift signal by shifting the gate start pulse GSP according to the gate shift clock GSC to supply the level shifter 320.

The level shifter 320 generates a scan pulse by level shifting the shift signal from the shift register 310 using the gate high voltage VGH and the gate low voltage VGL from the voltage generator 110. The scanned pulse is sequentially supplied to the gate line GL of the liquid crystal panel 102 according to the gate output signal GOE.

The gate driver 106 includes the gate control signal GCS from the timing controller 108, the gate high voltage VGH and the gate low voltage VGL from the voltage generator 110, as shown in FIG. 10. The scan pulse SP is generated by using and the generated scan pulse SP is sequentially supplied to the gate lines GL.

As illustrated in FIG. 11, the data driver 104 includes a shift register 350 for generating a sampling signal using the source shift clock SSC and the source start pulse SSP, and a timing controller 108 according to the sampling signal. Sampling by the first latch 360 sequentially sampling the even and odd data of one line supplied from the first latch 360 and the first latch 360 according to the source output enable signal SOE. Data line of the liquid crystal panel 102 by converting the second latch 370 for simultaneously outputting one line of data and the one line of digital data supplied from the second latch 370 into analog video data signals. And a digital-analog converter 380 for supplying to the DL.

The shift register 350 shifts the source start pulse SSP according to the source shift clock SSC to generate a sampling signal, and sequentially supplies the sampling signal to the first latch 360.

The first latch 360 sequentially samples the even and odd data of one line input through the bus line according to a sampling signal sequentially supplied from the shift register 350 to the second latch. Supply to 360. In this case, the even data and the odd data supplied to the first latch 360 may be any one of correction data MData and alignment data AData under the control of the timing controller 108.

The second latch 370 stores digital data sampled and supplied by the first latch 360 in units of one line and digitally stores one line of digital data stored in synchronization with the source output enable signal SOE. Outputs simultaneously to the analog converter 380.

The digital-analog converter 380 converts the digital data supplied from the second latch 370 into a video data signal using a plurality of input gamma voltages GMA, and converts the converted video data signal for one line. At the same time, it is output to the data line DL. That is, the digital-to-analog converter 380 selects any one of the plurality of gamma voltages GMA corresponding to the digital data in response to the polarity signal POL from the timing controller 108 to display the positive polarity (+) or the like. A negative video data signal is generated.

The data driver 104 uses the data control signal DCS from the timing controller 108 and the plurality of gamma voltages GMA as shown in FIG. 13 to output digital data from the timing controller 108. ) Is generated to supply the positive (+) or negative (-) video data signal to the data line DL.

Accordingly, as shown in FIG. 14, the liquid crystal panel 102 receives the data line DL from the data driver 104 to be synchronized with the scan pulse SP supplied from the gate driver 106 to the gate line GL. By adjusting the light transmittance of the liquid crystal cell according to the video data signal ADS supplied to the image, a desired gray level image is displayed.

The driving device and driving method of the liquid crystal display according to the exemplary embodiment of the present invention will be described as follows.

First, the alignment data AData is generated by aligning source data RGB from the outside to be suitable for driving the liquid crystal panel 102 using the data alignment unit 122 of the timing controller 108.

In addition, the data control signal generator 130 of the timing controller 108 generates the data control signal DCS and the gate control signal generator 140 generates the gate control signal GCS. .

The address signal generator 124 of the timing controller 108 generates an address signal AS according to the data control signal DCS and the gate control signal GCS.

Then, the data AData arranged according to the address signal AS is stored in the address value designated in the memory matrix 109.

Subsequently, the data CData stored in the memory matrix 109 is supplied to the timing controller 108 (data converter 240) according to the pixel read signal PRS, and the stored data CData read from the memory matrix 109 is then supplied. ) Is corrected and supplied to the data driver 104.

Accordingly, the data driver 104 converts the data Data corrected by the timing controller 108 into a video data signal ADS and supplies the scan pulse SP supplied from the gate driver 106 to the gate line GL. Is supplied to the data line DL so as to be synchronized with the.

Therefore, the driving apparatus and driving method of the liquid crystal display according to the exemplary embodiment of the present invention correct the gray value of the data Data supplied to the data driver 104 according to the pixel read signal PRS. The video data signal ADS is applied to the pixel at a specific position of.

As a result, the driving apparatus and driving method of the liquid crystal display according to the exemplary embodiment of the present invention can control image quality by recognizing image information according to pixel position of an image displayed on the display device and correcting an image signal input to the display device. It becomes possible.

Meanwhile, in the driving apparatus of the liquid crystal display according to the exemplary embodiment of the present invention, the memory matrix 109 and the timing controller 108 may be applied to a flat panel display including not only the above-described liquid crystal display but also a plasma display panel and a light emitting display. Can be used in the same manner as the above-described driving method.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is to be understood that various substitutions, modifications and changes can be made within the scope without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in the art.

The driving apparatus and driving method of the flat panel display device according to the embodiment of the present invention as described above generate an address signal according to a gate and data control signal, store the aligned data in the memory matrix, and then store the aligned data in the memory matrix according to the pixel read signal. The data signal supplied to the display device can be controlled by correcting the gradation value of the data stored in the display device. Accordingly, the present invention can control image quality by recognizing image information according to pixel positions of an image displayed on a display device and correcting an image signal input to the display device. Therefore, the present invention can improve the image quality of the display device.

Claims (15)

A display unit for displaying an image by using a scan pulse supplied to a gate line and a video data signal supplied to a data line; A data driver for supplying the video data signal to the data lines; A gate driver for supplying the scan pulses to the gate lines; A timing controller for aligning input source data and generating data and gate control signals for controlling the data driver and the gate driver; And a memory matrix including a plurality of registers for storing alignment data from the data alignment unit according to the address value designated by the address signal, and supplying the data stored at the address value designated by the pixel read signal to the timing controller. To; The timing controller generates the address signal using the data control signal and the gate control signal, and corrects the data supplied from the memory matrix according to the pixel read signal to supply the data driver to the data driver. Drive of display device. The method of claim 1, The timing controller, A data processor for aligning the source data, generating the address signal, and correcting a gray value of data supplied from a memory matrix; A data control signal generator for generating the data control signal by using the vertical and horizontal synchronization signals and the data enable signal; And a gate control signal generator configured to generate the gate control signal by using the data enable signal and vertical and horizontal synchronization signals. The method of claim 2, The data processing unit, A data alignment unit for aligning the source data with driving of the display unit; An address signal generator for generating the address signal using the data control signal and the gate control signal; And a data correction unit for correcting data supplied from the memory matrix. delete The method of claim 3, wherein The address signal generator, A storage unit for sequentially storing the data control signal and the gate control signal; An AND gate for performing an AND operation on the output signal and the reference signal from the storage unit; And a counter for counting an output signal from the AND gate to generate the address signal and supply the address signal to the memory matrix. The method of claim 5, And the data control signal is a source output enable signal and a source shift clock, and the gate control signal is a gate output signal and a gate shift clock. The method of claim 3, wherein The data correction unit, A data converter to correct data supplied from the memory matrix; And a selection unit for selecting one of correction data from the data conversion unit and alignment data from the data alignment unit in accordance with a selection signal and supplying the selected data to the data driver. The method of claim 7, wherein And the data converter generates the correction data by raising or lowering a gray value of data supplied from the memory matrix. The method of claim 1, And the memory matrix is embedded in the timing controller. A display unit for displaying an image by using a scan pulse supplied to a gate line and a video data signal supplied to a data line; A data driver for supplying the video data signal to the data lines; A driving method of a flat panel display device comprising a gate driver for supplying the scan pulses to the gate lines. Generating data and gate control signals for controlling the data driver and the gate driver; Arranging input source data to be suitable for driving the display unit; Generating an address signal using the data control signal and the gate control signal; Storing the sorted data in a memory matrix according to the address signal; Reading data from the memory matrix according to a pixel read signal, correcting the read data, and supplying the read data to the data driver; And the memory matrix stores the alignment data according to the address value designated by the address signal, and outputs the data stored at the address value designated by the pixel read signal. 11. The method of claim 10, Generating the address signal, Sequentially storing the data control signal and the gate control signal in a register; Performing an AND operation on the output signal and the reference signal from the register; And counting the output signal by the AND operation to generate the address signal and supply the generated address signal to the memory matrix. delete The method of claim 11, And the data control signal is a source output enable signal and a source shift clock, and the gate control signal is a gate output signal and a gate shift clock. 11. The method of claim 10, Correcting the data and supplying the data driver, Correcting data output from the memory matrix to generate correction data; And selecting one of the correction data and the alignment data according to a selection signal corresponding to the pixel read signal and supplying the selected data to the data driver. The method of claim 14, The generating of the correction data may include generating the correction data by increasing or decreasing a gray value of data output from the memory matrix.

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