KR101127228B1 - Method for forming junction of vertical cell in semiconductor device - Google Patents

Abstract

The present invention can easily control the doping concentration of the junction formed on the sidewall portion of the active region, can form a shallow depth of the junction, unnecessarily diffuse the dopant to the region other than the junction formed on the sidewall portion of the active region To provide a method for manufacturing a semiconductor device that can be prevented, the method of manufacturing a semiconductor device of the present invention comprises the steps of etching the substrate to form an active region separated by a trench; Forming an insulating film having an opening that exposes a portion of a sidewall of the active region; Forming an anti-doping film on the surface of the insulating film; Forming a junction on a portion of the exposed sidewall, and the present invention described above forms an anti-doping film on a surface of an insulating layer having an opening, thereby preventing the dopant from diffusing into a region other than the junction during subsequent annealing. It can work. In addition, the present invention can shallowly control the depth of bonding by applying the barrier film and the anti-doping film simultaneously.

Description

Method for forming junction of vertical cell of semiconductor device {METHOD FOR FORMING JUNCTION OF VERTICAL CELL IN SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a junction of vertical cells of a semiconductor device.

An ion beam implant method is mainly used as a method of forming a junction by doping a specific region in a semiconductor device manufacturing process. Ion beam ion implantation is also referred to as beam line implantation.

However, as semiconductor devices have recently been highly integrated, a more complex vertical cell having a minimum feature size (4F ² ) structure must be formed, and thus, there is a limit to doping using an ion beam ion implantation method. The vertical cell includes a pillar-shaped active region having sidewalls. The pillar-type active region is called an 'active pillar', and a three-dimensional vertical cell is manufactured using the pillar-type active region.

For example, in order to selectively dope a specific region of the pillar-type active region by using an ion beam ion implantation method, it may be forced to give a predetermined angle. This is called a tilt implant.

1 is a view for explaining a method for forming a junction of a semiconductor device according to the prior art.

Referring to FIG. 1, the substrate 11 is etched using the hard mask layer 14 as an etch barrier to form a pillar-shaped active region 13 separated by the trench 12.

An insulating film 15 having an opening that exposes a portion of one sidewall of the active region 13 is formed.

In order to form the junction 17 by doping a portion of the sidewall exposed by the opening, the interval between the active regions 13 is narrow and the active regions 13 are formed to have a certain height. 16) apply.

Tilt ion implantation 16 requires a tilt angle. Therefore, when the tilt ion implantation 16 proceeds, there is a problem that doping does not proceed to a desired position due to a shadow effect 16A. That is, when the tilt ion implantation 16 is performed, the doping may not be performed at a desired position due to the shadow effect of the hard mask layer 14 on the adjacent active region 13.

In addition, even when the tilt ion implantation 16 is used, since the height of the active region 13 is high and the spacing between the active regions 13 is small, it has a required level of doping concentration and doping depth. It is difficult to form the joint 17 easily.

delete

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device which can easily control the doping concentration of a junction formed on a portion of the sidewall of the active region and can form a shallow depth of the junction.

In addition, another object of the present invention is to provide a method of manufacturing a semiconductor device that can prevent the dopant from unnecessarily diffused into a region other than the junction formed on a part of the sidewall of the active region.

A semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of forming an active region separated by a trench by etching a substrate; Forming an insulating film having an opening that exposes a portion of a sidewall of the active region; Forming an anti-doping film on the surface of the insulating film; Forming a junction on a portion of the exposed sidewall. Forming the anti-doping film may include nitriding a portion of the surface of the insulating film.

In addition, the semiconductor device manufacturing method of the present invention comprises the steps of etching the substrate to form an active region separated by a trench; Forming an insulating film having an opening that exposes a portion of a sidewall of the active region; Forming an anti-doping film on the surface of the insulating film; Forming a barrier film on the entire surface including the anti-doping film; Forming a junction on a portion of the sidewall. Forming the anti-doping film may include nitriding a portion of the surface of the insulating film. The barrier film is formed by stacking a titanium film and a titanium nitride film.

The present invention described above has an effect of preventing the dopant from diffusing to a region other than the junction when forming the junction by subsequent annealing by forming the anti-doping layer in advance on the surface of the insulating film on which the opening is formed.

In addition, the present invention can shallowly control the depth of bonding by applying the barrier film and the anti-doping film simultaneously.

As a result, the present invention can easily control the depth and dose of the junction when forming the three-dimensional vertical cell, it is possible to manufacture a reliable vertical cell.

1 is a view for explaining a method for forming a junction of a semiconductor device according to the prior art.
2A to 2E illustrate a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.
3A to 3F illustrate a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.
4A to 4K are diagrams illustrating an example for forming an opening according to the first and second embodiments.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

2A to 2E illustrate a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

As shown in FIG. 2A, a plurality of active regions 203 is formed on the substrate 201 by the trench 202. The substrate 201 includes a silicon substrate. The active region 203 is formed by etching the substrate 201. Since the substrate 201 includes a silicon substrate, the active region 203 includes silicon. The active region 203 extends vertically from the surface of the substrate 201. The active region 203 includes pillars. As is well known, the active region 203 is a region where a channel region, a source region and a drain region of a transistor are formed. The source and drain regions are also called junctions. The active region 203 has a plurality of side walls. It has at least two side walls. The active region 203 includes pillar-shaped active regions. The pillar-type active region is called an 'active pillar'.

The hard mask layer 204 is formed on the active region 203. The hard mask layer 204 serves as an etch barrier when the active region 203 is formed. The hard mask layer 204 may include an insulating material such as an oxide layer and a nitride layer. In the first embodiment, a nitride film is used as the hard mask film 204. The hard mask film 204 includes a silicon nitride film.

An insulating film is formed on both sidewalls of the active region 203, the surface of the substrate 201 between the active regions 203, and the surface of the hard mask film 204. The insulating film includes a liner oxide film 205 and a liner nitride film 206. The liner oxide film 205 is formed on both sidewalls of the active region 203 and the surface of the substrate 201. The liner nitride film 206 is formed on a portion of the surface of the liner oxide film 205.

A portion of the insulating film is removed to form an opening 207. The opening 207 is a one-side-opening (OSO) structure for selectively exposing a portion of one sidewall of the active region 203. The opening 207 includes a line type opening.

An opening 207 is provided that exposes a portion of the sidewall of the active region 203 by the insulating film described above. A method of forming the opening 207 will be described with reference to FIGS. 4A to 4K described later.

As shown in FIG. 2B, plasma doping (208) is performed. As a result, part of the insulating film is nitrided. Preferably, a part of the liner oxide film 205 is nitrided. The nitrided liner oxide film 205 is denoted by reference numeral 209, and the non-nitridated liner oxide film is denoted by reference numeral 205A.

Hereinafter, the nitrided liner oxide film is abbreviated as an anti-doping film 209. The anti-doping film 209 prevents the dopant of the doped film from diffusing to the substrate surface and to a region other than the junction during the subsequent annealing process.

Plasma nitridation (208) proceeds at a power of 100 to 2500 W, a pressure of 5 to 40 mTorr, and a temperature of room temperature to 600 ° C., and is carried out for 1 to 300 seconds while flowing nitrogen (N ₂ ) gas at a flow rate of 50 to 1000 sccm. .

As shown in FIG. 2C, a doped film 210 gap-filling the trench 202 between the active regions 203 is formed. At this time, the doped film 210 is doped with a dopant for forming a junction. For example, the doped film 210 may include a doped polysilicon film. The doped polysilicon film is excellent in step coverage and enables void free gapfill of the trench 202 without voiding, and thus the uniformity of the subsequent bonding is good. The dopant doped in the doped film 210 may include N-type impurities such as phosphorous (Ph). The doped film 210 may be formed to a thickness of 50 to 1000 GPa by using chemical vapor deposition (CVD). The dopant doped in the doped film 210 contains a dose of 1 × 10 ¹⁵ to 1 × 10 ¹⁷ atoms / cm ² .

The doped film 210 is planarized and etched back. Accordingly, the doped film 210 may be formed to partially fill the trench 202, and may have at least a height in contact with the opening. As such, by lowering the height by performing planarization and etchback, the dopant may be prevented from diffusing into the remaining region except for the opening during the subsequent annealing process.

Next, Anneal 211 is performed. At this time, the dopant doped in the doped film 210 is diffused into one sidewall of the active region 203 exposed by the opening 207 to form a junction 212. When the dopant doped in the doped film 210 is an N-type impurity, the junction 212 becomes an N-type junction.

Preferably, the anneal 211 applies either a furnace anneal or a rapid thermal anneal method or both. Annealing temperature shall be 750-1200 degreeC. Junction 212 has a doping concentration of at least 1 × 10 ²⁰ atoms / cm ³ or greater.

In this manner, by forming the doped film 210 and forming the junction 212 by thermal diffusion through the annealing 211, the depth of the junction 212 can be controlled to be shallow, and the concentration of the dopant can be controlled. This is easy. The dopant is prevented from diffusing to the bottom of the trench 202 and the region other than the junction 212 by the anti-doping film 209 during the annealing process 211. Dopant diffusion is prevented by the liner nitride layer 206 toward the remaining sidewall of the active region 203 except for the junction 212.

On the other hand, in the absence of the anti-doping film 209, the dopant passes through the liner oxide film and diffuses to the bottom of the trench and to areas other than the junction. As such, unnecessarily diffusion of the dopant causes a bridge between neighboring junctions 212.

As shown in FIG. 2D, the doped film 210 is removed. In this case, the doped film 210 may be removed by wet or dry etching. When the doped film 210 is a doped polysilicon film, dry etching may be performed using HBr and Cl ₂ series compounds, and may further include O ₂ , N ₂ , He, Ar, and the like. When wet etching is used, a cleaning solution using a nitride film, an oxide film and a high selectivity is used.

Subsequently, after forming a barrier metal 213 which serves to prevent diffusion, a bit line conductive layer 214 is formed. In this case, the bit line conductive layer 214 is formed on the entire surface to gap-fill the active regions 203. The bit line conductive film 214 includes a metal film such as a titanium nitride film (TiN) or a tungsten film (W). For example, the bit line conductive film 214 may be formed by stacking a titanium nitride film and a tungsten film (TiN / W). When the bit line conductive layer 214 is a metal layer, ohmic contact between the junction 212 made of silicon and the metal layer is required. The ohmic contact (not shown) is formed by performing a series of processes after the barrier film 213 is formed. Ohmic contacts include metal silicides such as titanium silicide. In order to form an ohmic contact, the barrier film 213 includes a titanium film, and preferably, a titanium film and a titanium nitride film are stacked. Thereafter, heat treatment is performed to form titanium silicide. The titanium film used as the barrier film 213 is formed to a thickness of 10 to 200 Å using chemical vapor deposition (CVD). The titanium nitride film is formed to a thickness of 10 ~ 200Å by chemical vapor deposition (CVD) or atomic layer deposition (ALD).

As shown in FIG. 2E, the bit line conductive film 214 and the barrier film 213 are removed to a height in contact with the junction 212. As a result, a buried bit line is electrically connected to the junction 212. The buried bit line may include a barrier layer pattern 213A and a bit line conductive layer pattern 214A.

3A to 3F illustrate a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

As shown in FIG. 3A, a plurality of active regions 303 separated by trenches 302 are formed on the substrate 301. The substrate 301 includes a silicon substrate. The active region 303 is formed by etching the substrate 301. Since the substrate 301 includes a silicon substrate, the active region 303 includes silicon. The active region 303 extends in the vertical direction from the surface of the substrate 301. The active region 303 includes pillars. As is well known, the active region 303 is a region where a channel region, a source region and a drain region of a transistor are formed. The source and drain regions are also called junctions. The active region 303 has a plurality of side walls. It has at least two side walls. The active region 303 includes a pillar-type active region. The pillar-type active region is called an 'active pillar'.

A hard mask film 304 is formed on the active region 303. The hard mask layer 304 serves as an etch barrier when the active region 303 is formed. The hard mask layer 304 may include an insulating material such as an oxide film and a nitride film. In the second embodiment, a nitride film is used as the hard mask film 304. The hard mask film 304 includes a silicon nitride film.

An insulating film is formed on both sidewalls of the active region 303, the surface of the substrate 301 between the active regions 303, and the surface of the hard mask film 304. The insulating film includes a liner oxide film 305 and a liner nitride film 306. The liner oxide film 305 is formed on both sidewalls of the active region 303 and the surface of the substrate 301. The liner nitride film 306 is formed on a portion of the surface of the liner oxide film 305.

A portion of the insulating film is removed to form an opening 307. The opening 307 is a one-side-opening (OSO) structure for selectively exposing a portion of one sidewall of the active region 303. The opening 307 includes a line type opening.

An opening 307 is provided that exposes a portion of the sidewall of the active region 303 by the insulating film described above. A method of forming the opening 307 will be described later with reference to FIGS. 4A to 4K.

As shown in FIG. 3B, plasma doping (308) is performed. As a result, part of the insulating film is nitrided. Preferably, a part of the liner oxide film 305 is nitrided. The nitrided liner oxide film 305 is referred to as '309', and the non-nitrided liner oxide film is referred to as '305A'.

Hereinafter, the nitrided liner oxide film is abbreviated as an anti-doping film 309. The anti-doping film 309 prevents the dopant of the doped film from diffusing to the substrate surface and the non-bonding region in a subsequent annealing process.

Plasma nitriding 308 proceeds at a power of 100 to 2500 W, a pressure of 5 to 40 mTorr, and a temperature of room temperature to 600 ° C., and is carried out for 1 to 300 seconds while flowing nitrogen (N 2) gas at a flow rate of 50 to 1000 sccm.

As shown in FIG. 3C, a barrier metal 310 serving to prevent diffusion is formed. The barrier film 310 includes a titanium film. In addition, the barrier film 310 is formed by stacking a titanium film Ti and a titanium nitride film TiN. The titanium film used as the barrier film 310 is formed to a thickness of 10 ~ 200Å by chemical vapor deposition (CVD). The titanium nitride film is formed to a thickness of 10 ~ 200Å by chemical vapor deposition (CVD) or atomic layer deposition (ALD).

Next, a doped film 311 is formed to gap fill the trench 302 between the active regions 303. At this time, the doped film 311 is doped with a dopant for forming a junction. For example, the doped film 311 includes a doped polysilicon film. The doped polysilicon film is excellent in step coverage, and enables void free gapfill of the trench 302 without voiding, and thus the uniformity of the subsequent bonding is good. The dopant doped in the doped film 311 may include N-type impurities such as phosphorus (Ph). The doped film 311 may be formed to a thickness of 50 to 1000 GPa by using chemical vapor deposition (CVD). The dopant doped in the doped film 311 contains a dose of 1 × 10 ¹⁵ to 1 × 10 ¹⁷ atoms / cm ² .

As shown in Fig. 3D, the doped film 311 is planarized and etched back. Accordingly, the doped film 311A is formed to partially fill the trench 302 and has a height in contact with the opening at least. As such, by lowering the height by performing planarization and etchback, the dopant may be prevented from diffusing into the remaining region except for the opening during the subsequent annealing process.

Next, Anneal 312 is performed. At this time, the dopant doped in the doped film 311A is diffused into one sidewall of the active region 303 exposed by the opening 307 to form a junction 313. When the dopant doped in the doped film 311A is an N type impurity, the junction 313 becomes an N type junction.

Preferably, the anneal 312 applies either a furnace anneal or a rapid thermal anneal method or both. Annealing temperature shall be 750-1200 degreeC. The junction 313 has a doping concentration of at least 1 × 10 ²⁰ atoms / cm ³ or greater.

In this manner, by forming the doped film 311A and forming the junction 313 by thermal diffusion through the annealing 312, the depth of the junction 313 can be controlled to be shallow, and the concentration of the dopant can be controlled. This is easy. The dopant is prevented from diffusing to the bottom of the trench 302 and the region other than the junction 313 by the anti-doping film 309 during the annealing 312 process. In addition, the depth of the junction 313 can be controlled even more shallowly by the barrier film 310.

On the other hand, in the absence of the anti-doping film 309, the dopant passes through the liner oxide film and diffuses to the bottom of the trench and the region other than the junction. As such, unnecessarily diffusion of the dopant causes a bridge between neighboring junctions 313.

And although the barrier film 310 plays a role of controlling the depth of the junction 313 shallowly, when the barrier film 310 includes a titanium film, the titanium film is likely to react with the liner oxide film 305A. Accordingly, a parasitic oxide such as 'Ti _x Si _y O _z ' is formed at the interface between the titanium film and the liner oxide film, and the dopant can pass through the liner oxide film by the parasitic oxide to diffuse to the bottom of the trench and the region other than the junction. have. In the second embodiment, the anti-doping film 309 is formed in advance through plasma nitridation so that parasitic oxides such as Ti _x Si _y O _z 'are not formed when the barrier film is formed. That is, when nitrides such as 'SiON' are formed through plasma nitridation, dopants do not diffuse to the bottom of the trench 302 and regions other than the junction 313 during the annealing process for forming the junction 313.

As shown in Fig. 3E, the doped film 311A is removed. In this case, the doped film 311A may be removed by wet or dry etching. When the doped film 311A is a doped polysilicon film, dry etching may be performed using HBr and Cl ₂ series compounds, and may further include O ₂ , N ₂ , He, Ar, and the like. In the case of using wet etching, a cleaning solution using a nitride film, an oxide film and a high selectivity is used.

 Subsequently, a bit line conductive film 314 is formed. In this case, the bit line conductive layer 314 is formed on the front surface to gap-fill the active regions 303. The bit line conductive film 314 includes a metal film such as a titanium nitride film (TiN), a tungsten film (W), or the like. For example, the bit line conductive film 314 may be formed by stacking a titanium nitride film and a tungsten film (TiN / W). When the bit line conductive layer 314 is a metal layer, ohmic contact is required between the junction 313 made of silicon and the metal layer. Before the bit line conductive film 314 is formed, a series of processes are performed on the barrier film 310 connected to the junction 313 to form an ohmic contact (not shown). Ohmic contacts include metal silicides such as titanium silicide. The barrier layer 310 is heat treated to form an ohmic contact. When the barrier layer 310 includes a titanium film, titanium silicide is formed by heat treatment.

As shown in FIG. 3F, the bit line conductive layer 314 and the barrier layer 310 are removed to a height in contact with the junction 313. As a result, a buried bit line is electrically connected to the junction 313. The buried bit line includes a barrier layer pattern 310A and a bit line conductive layer pattern 314A.

4A to 4K are diagrams illustrating an example for forming an opening according to the first and second embodiments.

As shown in FIG. 4A, a hard mask film 22 is formed on the substrate 21. The substrate 21 includes a silicon substrate. The hard mask film 22 includes a nitride film. In addition, the hard mask film 22 may have a multilayer structure including an oxide film and a nitride film. For example, the hard mask layer 22 may be stacked in the order of the hard mask nitride layer (HM Nitride) and the hard mask oxide layer (HM Oxide). In addition, the hard mask layer 22 may be laminated in the order of a hard mask nitride film, a hard mask oxide film, a hard mask silicon oxynitride film (HM SiON), and a hard mask carbon film (HM Carbon). In the case of including the hard mask nitride layer, a pad oxide layer may be further formed between the substrate 21 and the hard mask layer 22. The hard mask film 22 is formed using a photosensitive film pattern (not shown).

As shown in FIG. 4B, a trench etch process is performed using the hard mask layer 22 as an etch barrier. For example, the active region 23 is formed by etching the substrate 21 by a predetermined depth using the hard mask layer 22 as an etch barrier. The active regions 23 are separated from each other by trenches 24. The active region 23 includes an active region in which a transistor is formed. The active region 23 has two side walls. Trench etching processes include anisotropic etch. When the substrate 21 is a silicon substrate, the anisotropic etching may include plasma dry etching using Cl ₂ or HBr gas alone, or using a mixture of these gases. The plurality of active regions 23 are formed on the substrate 21 by the trench 24 described above. The active region 23 comprises a linear pillar, in particular a linear active pillar. The active pillar refers to a pillar type active region.

The liner oxide film 25 is formed as an insulating film. The liner oxide film 25 includes an oxide film such as a silicon oxide film.

A first gap fill layer 26 is formed on the liner oxide layer 25 to gap fill the trench 24 between the active regions 23. The first gap fill layer 26 may include undoped polysilicon or amorphous silicon.

As shown in FIG. 4C, the first gap fill layer 26 is planarized until the surface of the hard mask layer 22 is exposed. The planarization of the first gap fill film 26 may include a chemical mechanical polishing (CMP) process. The etch-back process is performed continuously. After the etch back process, the first gap fill pattern 26A provides the first recess R1. In the chemical mechanical polishing process, the liner oxide layer 25 on the hard mask layer 22 may be polished. As a result, a liner oxide film pattern 25A covering both sidewalls of the hard mask film 22 and the trench 24 is formed. The liner film oxide film pattern 25A also covers the bottom of the trench 24. In addition, the liner oxide layer pattern 25A may be slimmed on the sidewall of the active region 23 during the etch back process.

As shown in FIG. 4D, a liner nitride film 27 is formed as an insulating film on the entire surface including the first gap fill film pattern 26A. The liner nitride film 27 includes a nitride film such as a silicon nitride film.

As shown in FIG. 4E, the liner nitride film 27 is etched. Accordingly, the liner nitride film pattern 27A is formed. Subsequently, the first gap fill film pattern 26A is recessed to a predetermined depth using the liner nitride film pattern 27A as an etch barrier. As a result, the second recess R2 is formed. The first gap fill pattern formed with the second recess R2 is denoted by reference numeral 26B.

As shown in FIG. 4F, a metal nitride film is conformally formed on the entire surface including the second recess R2. Thereafter, spacers are etched to form spacers 28. Spacers 28 are formed on both sidewalls of the active region 23. The spacer 28 includes a titanium nitride film TiN.

A second gap fill layer 29 is formed to gap fill the second recess R2 having the spacer 28 formed therein. The second gap fill film 29 includes an oxide film. The second gap fill layer 29 may include a spin on dielectric (SOD).

As shown in FIG. 4G, the second gap fill layer 29 is planarized and then etched back. As a result, the recessed second gap fill pattern 29A is formed.

An etch barrier film 30 is formed on the entire surface including the second gap fill film pattern 29A. The etch barrier 30 includes undoped polysilicon.

As shown in FIG. 4H, the tilt ion implantation 31 is performed.

Tilt ion implantation 31 implants a dopant (Dopnat) by giving a tilt at a predetermined angle. Dopants are injected into a portion of the etching barrier layer 30.

The tilt ion implantation 31 is performed at a predetermined angle. The predetermined angle includes about 5-30 degrees. The ion beam is partially shadowed by the hard mask film 22. Thus, part of the etch barrier 30 is doped but the rest remains undoped. For example, the dopant to be ion implanted is a P-type dopant, preferably Boron, and the dopant source uses BF ₂ to ion implant boron. As a result, a part of the etch barrier film 30 remains undoped, which is a portion adjacent to the left side of the hard mask film 22.

The portion of the etching barrier layer formed on the upper surface of the hard mask layer 22 and the portion adjacent to the right side of the hard mask layer 22 by the tilt ion implantation 31 of the dopant are doped etch barriers doped with the dopant. It becomes a doped etch barrier (30A). The etch barrier film into which the dopant is not injected becomes the undoped etch barrier film 30B.

As shown in FIG. 4I, the undoped etch barrier film 30B is removed. Here, the polysilicon used as an etching barrier has a difference in etching speed depending on whether dopants are doped or not. In particular, the undoped polysilicon without dopants has a high wet etching rate. Therefore, the undoped polysilicon is selectively removed using a high selectivity chemical capable of wet etching only the undoped polysilicon. The undoped etch barrier film 30B is removed using wet etching or wet cleaning.

When the undoped etch barrier 30B is removed as described above, only the dope etch barrier 30A remains.

As shown in FIG. 4J, one of the spacers 28 is removed. As a result, a gap 32 is formed. The spacer 28 is removed using wet etching. As a result, one spacer 28A remains.

As shown in FIG. 4K, the doped etch barrier layer 30A is removed, and then a cleaning process is performed to expose a portion of the sidewall of the active region 23.

The cleaning process includes wet cleaning. Wet cleaning uses hydrofluoric acid (HF) and BOE (Buffered Oxide Etchant). When wet cleaning is used, part of the liner oxide film pattern 25A is removed to form an opening 33. Similarly to the liner oxide film pattern 25A, the second gap fill film pattern 29A is also removed.

As described above, the hard mask film 22, the liner oxide film pattern 25A, and the liner nitride film pattern 27A are collectively referred to as an 'insulation film'. Thus, the insulating film provides an opening 33 exposing a portion of either sidewall of the active region 23.

Next, the spacer 28A is removed.

The opening 33 corresponds to the opening 207 of the first embodiment and the opening 307 of the second embodiment. In addition, the liner oxide film pattern 25A corresponds to the liner oxide film 205 of the first embodiment and the liner oxide film 305 of the second embodiment. The liner nitride film pattern 27A corresponds to the liner nitride film 206 of the first embodiment and the liner nitride film 306 of the second embodiment. The active area 23 corresponds to the active area 203 of the first embodiment and the active area 303 of the second embodiment.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

201: substrate 202: trench
203: active area 204: hard mask film
205A: liner oxide film 206: liner nitride film
209: anti-doping film 212: bonding

Claims (19)

Etching the substrate to form an active region separated by a trench;
Forming an insulating film having an opening that exposes a portion of a sidewall of the active region;
Forming an anti-doping film on the surface of the insulating film; And
Forming a junction on a portion of the exposed sidewall
≪ / RTI >
Claim 2 has been abandoned due to the setting registration fee. The method of claim 1,
Forming the anti-doping film,
And nitriding a portion of the surface of the insulating film.
Claim 3 was abandoned when the setup registration fee was paid. The method of claim 2,
The nitriding step,
A semiconductor device manufacturing method comprising plasma nitriding.
Claim 4 was abandoned when the registration fee was paid. The method of claim 3,
The plasma nitriding is performed at a power of 100 to 2500 W, a pressure of 5 to 40 mTorr, and is carried out for 1 to 300 seconds while flowing nitrogen (N ₂ ) gas at a flow rate of 50 to 1000 sccm.
Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1,
And the anti-doping film comprises a nitride film.
Claim 6 was abandoned when the registration fee was paid. The method of claim 1,
And the insulating film comprises an oxide film, and the anti-doping film comprises a film obtained by nitriding the oxide film.
Claim 7 was abandoned upon payment of a set-up fee. The method of claim 1,
Forming the junction,
Gap-filling the trench and forming a doped film doped with a dopant; And
Annealing
≪ / RTI >
Claim 8 was abandoned when the registration fee was paid. The method of claim 7, wherein
And the doped film comprises doped polysilicon.
Etching the substrate to form an active region separated by a trench;
Forming an insulating film having an opening that exposes a portion of a sidewall of the active region;
Forming an anti-doping film on the surface of the insulating film;
Forming a barrier film on the entire surface including the anti-doping film; And
Forming a junction in a portion of the sidewall
≪ / RTI >
Claim 10 was abandoned upon payment of a setup registration fee. 10. The method of claim 9,
Forming the anti-doping film,
And nitriding a portion of the surface of the insulating film.
Claim 11 was abandoned upon payment of a setup registration fee. The method of claim 10,
The nitriding step,
A semiconductor device manufacturing method comprising plasma nitriding.
Claim 12 was abandoned upon payment of a registration fee. The method of claim 11,
The plasma nitriding is performed at a power of 100 to 2500 W, a pressure of 5 to 40 mTorr, and is carried out for 1 to 300 seconds while flowing nitrogen (N ₂ ) gas at a flow rate of 50 to 1000 sccm.
Claim 13 was abandoned upon payment of a registration fee. 10. The method of claim 9,
And the anti-doping film comprises a nitride film.
Claim 14 was abandoned when the registration fee was paid. 10. The method of claim 9,
And the insulating film comprises an oxide film, and the anti-doping film comprises a film obtained by nitriding the oxide film.
Claim 15 was abandoned upon payment of a registration fee. 10. The method of claim 9,
Forming the junction,
Gap-filling the trench and forming a doped film doped with a dopant; And
Annealing
≪ / RTI >
Claim 16 has been abandoned due to the setting registration fee. 16. The method of claim 15,
And the doped film comprises doped polysilicon.
Claim 17 has been abandoned due to the setting registration fee. 10. The method of claim 9,
And the barrier film comprises a titanium film.
Claim 18 was abandoned upon payment of a set-up fee. 10. The method of claim 9,
And the barrier film is formed by stacking a titanium film and a titanium nitride film.
Claim 19 was abandoned upon payment of a registration fee. The method according to any one of claims 1 to 18,
After forming the junction,
And forming a bit line connected to the junction and partially filling the trench.

Images