KR101116336B1 - Method for fabricating semiconductor device - Google Patents

Abstract

The present invention is to prevent the facet generated by the spacer loss, and to solve the difficulty in securing the ion implantation depth and side profile during subsequent ion implantation by the thick spacer, forming a gate pattern on the substrate; Forming a first spacer on a sidewall of the gate pattern to define an LDD region; Etching the substrate between the first spacers to a predetermined depth to form a recess pattern; Forming a selective epitaxial thin film on the recess pattern; Forming a second spacer closer to the channel, thereby increasing the channel strain to improve the operating current, and shortening the channel effect as the dopant diffusion is reduced. By forming a stressor before forming the second spacer to prevent facet generation due to the loss of the spacer, and forming a stressor before forming the second spacer to secure ion implantation depth and side profile by the thick spacer. Difficulty also prevents the effect.

Facet, channel, LDD

Description

Semiconductor device manufacturing method {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly to a method of manufacturing a semiconductor device having strained channels.

As the semiconductor devices become more integrated, the channel length of the gate and the thickness of the insulating film continue to decrease. As the channel length of the gate and the thickness of the insulating layer decrease, it is expected that the mobility of electrons or holes serving as carriers increases to increase the speed and operating current of the device.

However, reducing the channel length has a problem of causing a short channel effect, and decreasing the gate insulating film increases the gate leakage current. In addition, when increasing the channel doping to improve the short channel effect, it is difficult to improve the expected carrier mobility despite the reduction in the channel length by disturbing the movement of the carrier.

In order to improve the operating speed and operating current of the device, various methods of increasing carrier mobility by inducing strain in the channel have been proposed. In particular, recess etch of the source / drain region near the gate sidewall is performed. After that, a method of forming strained channels by selectively depositing epitaxial thin films of group 4 elements having different lattice constants from silicon and applying stress to the channels has been studied.

In the case of DRAM devices, there is a need to increase and improve the operating current of the peripheral circuit area as the size is reduced. Selective epitaxial silicon-germanium (SiGe) or silicon-carbon (SiC) is applied to the recess source / drain as described above. Attempts have been made to apply a method of growing DRAM to form a DRAM device having a strained channel.

1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device having a strained channel according to the prior art.

As shown in FIG. 1A, an isolation layer 12 is formed on a substrate 11 having a cell region and a peripheral region.

Subsequently, a gate pattern 13 is formed on the substrate 11 including the device isolation film 12.

Next, although not shown, a pocket / halo / LDD ion implantation is performed using a mask.

As shown in FIG. 1B, a spacer nitride film 14 is formed along a step of the entire structure including the gate pattern 13. In this case, the spacer nitride layer 14 is formed to have a thickness capable of securing a space between the gate patterns 13 adjacent to each other in the cell region.

As shown in FIG. 1C, a spacer oxide film is formed on the spacer nitride film 14.

Subsequently, a mask pattern (not shown) for opening the peripheral region is formed to etch the spacer oxide film formed in the peripheral region to form the spacer 15B. At this time, the spacer nitride film 14 in the peripheral region is also etched to open the substrate 11 between the gate patterns 13.

The spacer oxide film 15A in the cell region remains in the state of filling the gate pattern 13.

As shown in FIG. 1D, the substrate 11 exposed between the spacers 15A in the peripheral region is recessed to a predetermined depth.

As shown in FIG. 1E, pretreatment is performed in the recess 16 region, followed by the formation of an optional epitaxial thin film 17. The selective epitaxial thin film 17 is formed of a material having a different lattice constant from the substrate 11.

As described above, according to the related art, after the spacer 15B is formed on the sidewall of the gate pattern 13, the substrate 11 exposed between the spacers 15B is recessed 16, and thus the region of the recess 16 is formed. An optional epitaxial thin film 17 is formed.

However, in the prior art, the spacer 15B is easily lost in the pretreatment of the recess 16 before the selective epitaxial thin film 17 is formed, so that a large facet is generated, and the ion is subsequently implanted. There is a problem that the injection depth and side profile cannot be kept constant.

In the case of forming the spacer only with the nitride film in order to prevent the loss of the spacer 15B in the pretreatment process, since the thickness of the nitride film must be several hundred microns, it is disadvantageous to secure the bottom side depth by the thick spacer as in the prior art. Since all of the gate patterns of the cell region are filled and the source / drain portions are also filled with the nitride film, a cell cannot be implemented, and therefore, there is a problem in that DRAM devices cannot be integrated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems of the prior art, and an object thereof is to provide a method for manufacturing a semiconductor device which prevents facet generation due to spacer loss.

Another object of the present invention is to provide a method of manufacturing a semiconductor device that can solve the difficulty of securing the ion implantation depth and the side profile during subsequent ion implantation by a thick spacer.

A semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of forming a gate pattern on a substrate; Forming a first spacer on a sidewall of the gate pattern to define an LDD region; Etching the substrate between the first spacers to a predetermined depth to form a recess pattern; Forming a selective epitaxial thin film on the recess pattern; And forming a second spacer on the first spacer.

In particular, the first spacer is characterized in that it is formed in a thickness of 10 ~ 300Å.

In addition, before the forming of the first spacer, a pocket / halo / LDD ion implantation is performed on the substrate between the gate patterns, or after the formation of the first spacer, the recess pattern is formed. Before the step, it characterized in that the pocket / halo / LDD ion implantation.

In addition, the forming of the first spacer and the forming of the recess pattern may be performed in situ in the same chamber.

In addition, the depth of the recess pattern is characterized in that the 100 ~ 1000Å.

In addition, before the step of forming the selective epitaxial thin film, further comprising the step of performing a pre-treatment to the recess pattern, the pre-treatment proceeds in-situ, the temperature proceeds from room temperature to 600 ℃ Characterized in that.

In addition, the selective epitaxial thin film may be a single layer of silicon germanium or silicon carbon, or the selective epitaxial thin film may be a laminated structure of silicon / silicon germanium / silicon or a stacked structure of silicon / silicon carbon / silicon. It is done.

In addition, the substrate is NMOS, the selective epitaxial thin film is a single layer of silicon carbon or silicon / silicon carbon / silicon laminated structure, or the substrate is a PMOS, the selective epitaxial thin film is a single layer of silicon germanium or It is characterized in that the laminated structure of silicon / silicon germanium / silicon.

In addition, the selective epitaxial thin film is characterized in that it is formed by undoping.

Further, the germanium concentration in the selective epitaxial thin film is 5% to 50%, and the carbon concentration in the selective epitaxial thin film is 0.1% to 10%.

In addition, the selective epitaxial thin film is characterized in that formed in a thickness of 100 ~ 2000Å.

The spacer oxide film may be formed to a thickness of 10 kPa to 1000 kPa.

In addition, after the step of forming the selective epitaxial thin film, it characterized in that it further comprises the step of proceeding pocket / halo / LDD ion implantation.

Another semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of forming a gate pattern on a substrate; Forming a first spacer on a sidewall of the gate pattern to define an LDD region; Etching the substrate between the first spacers to a predetermined depth to form a recess pattern; Forming a selective epitaxial thin film on the recess pattern; Performing pocket / halo / LDD ion implantation on the selective epitaxial thin film; And forming a second spacer on the first spacer.

Another semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of forming a gate pattern on a substrate having a cell region and a peripheral region; Forming a spacer nitride film along a step of the entire structure including the gate pattern; Etching the spacer nitride film of the peripheral region to form a first spacer defining an LDD region on a sidewall of the gate pattern of the peripheral region; Etching the substrate between the first spacers of the peripheral area to a predetermined depth to form a recess pattern; Forming a selective epitaxial thin film on the recess pattern; Forming a spacer oxide film thicker than the spacer nitride film along a step of the entire structure including the selective epitaxial thin film of the peripheral region and the spacer nitride film of the cell region; And etching a spacer oxide film in the peripheral area to form a second spacer on the first spacer.

The semiconductor device manufacturing method of the present invention described above has the effect of increasing the channel strain by forming the strainer closer to the channel, thereby improving the operating current.

In addition, as the dopant diffusion is reduced, the short channel effect may be improved.

In addition, there is an effect of preventing the occurrence of facets due to the loss of the spacer by forming a stressor before forming the second spacer. In addition, by forming the stressor before forming the second spacer, the difficulty of securing the ion implantation depth and the side profile by the thick spacer is also prevented in advance.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention.

2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 2A, the device isolation layer 22 is formed on the substrate 21 having the cell region and the peripheral region. The device isolation layer 22 is used to define an active region and is formed by a shallow trench isolation (STI) process.

Subsequently, a gate pattern 23 is formed on the substrate 21 including the device isolation layer 22. The gate pattern 23 may be formed as a stacked structure of a polysilicon electrode, a metal electrode, and a gate hard mask. In addition, the pattern density of the gate pattern 23 is formed in the cell region and the peripheral region, respectively. That is, the cell region has a narrow space between the gate patterns 23, and the peripheral region has a wide space between the gate patterns 23.

As shown in FIG. 2B, the spacer nitride film 24 is formed along a step of the entire structure including the gate pattern 23. The spacer nitride layer 24 is formed to have a thickness that does not fill between the gate patterns 23 of the cell region, and the stressor of the peripheral region is preferably formed to have a predetermined thickness as close to the channel as possible.

The spacer nitride film 924 defines the LDD region of the peripheral region, and determines the distance between the channel and the stressor, and is preferably formed to a thickness of 10 kPa to 300 kPa.

As shown in FIG. 2C, after forming a mask pattern (not shown) to open the peripheral region, the spacer nitride layer 24 of the peripheral region is etched to form the first spacer 24A on the sidewall of the gate pattern 23. Form. Therefore, the substrate 21 is exposed between the gate patterns 23 in the peripheral region.

The spacer nitride film 24 in the unopened cell region remains unetched.

As illustrated in FIG. 2D, a recess pattern 25 is formed by etching a predetermined depth of the substrate 21 exposed between the first spacers 24A in the peripheral area. At this time, the recess pattern 25 is formed by isotropic or anisotropic etching, but adjusts the profile near the channel.

The etching process for forming the first spacer 24A and the etching process for forming the recess pattern 25 may be continuously performed in-situ in the same chamber, or may be performed in different chambers. Ex-Situ).

The depth of the recess pattern 25 is determined according to the amount of stress to be applied to the channel, which is required for the required device characteristics, but is preferably formed to a depth of 100 kPa to 1000 kPa. In addition, the side etching distance of the recess pattern 25 may be adjusted to be as deep as possible in consideration of the thickness of the first spacer 24A, the channel length, the height of the gate pattern 23, and the like.

As shown in FIG. 2E, the recess pattern 25 is subjected to preprocessing. Pretreatment can be either wet or dry, or both wet and dry. In particular, the pretreatment proceeds in-situ to remove all of the natural oxide film and other surface materials, and to use a gas or a solution having a good selectivity to minimize the loss of the first spacer 24A. desirable.

Moreover, it is preferable to advance pretreatment at the comparatively low temperature of normal temperature-600 degreeC.

Subsequently, an optional epitaxial thin film 26 is formed on the recess pattern 25. In this case, the selective epitaxial thin film 26 is formed of a material having a different lattice constant from the substrate 21, but preferably formed of silicon germanium (SiGe) or silicon carbon (SiC). In particular, the selective epitaxial thin film 26 may be formed of a single layer of silicon germanium or silicon carbon, or may be formed of a stacked structure of silicon / silicon germanium (or silicon carbon) / silicon.

In addition, the selective epitaxial thin film 26 may be formed in-situ and may be formed as undoped.

In addition, the selective epitaxial thin film 26 may include low pressure chemical vapor deposition (LPCVD), very low pressure CVD (VLPCVD), plasma enhanced-CVD (PE-CVD), ultrahigh vacuum CVD (UHVCVD), and rapid thermal CVD (RTCVD). , At least one device selected from the group consisting of APCVD (Atmosphere Pressure CVD) and MBE (Molecular Beam Epitaxy) is formed at a temperature of 400 ℃ ~ 800 ℃.

The concentration of germanium or carbon in the selective epitaxial thin film 26 is determined according to the characteristics of the device, and in the case of germanium, the concentration is preferably 5% to 50%, and in the case of carbon, preferably 0.1% to 10 Has a concentration of%.

In addition, the thickness of the selective epitaxial thin film 26 is determined according to the depth of the recess pattern 25 and the device characteristics, and is preferably formed to a thickness of 100 kPa to 2000 kPa.

On the other hand, the peripheral region has an NMOS and a PMOS, and in the case of PMOS, a selective epitaxial that has a lattice constant larger than that of the silicon substrate 21 in order to increase the mobility of holes, which are carriers, causing compressive stress. The thin film 26 is used, and in the case of NMOS, a selective epitaxial thin film 26 is used in order to increase the mobility of electrons, which are carriers, so that the lattice constant is smaller than that of a silicon substrate to induce tensile stress. It is desirable to.

Therefore, the selective epitaxial thin film 26 of PMOS is formed of a single layer of silicon germanium or a stacked structure of silicon / silicon germanium / silicon and doped boron, and the selective epitaxial thin film 26 of NMOS is It is preferable to form a single layer of silicon carbon or a laminated structure of silicon / silicon carbon / silicon and to dope phosphorus (P) or arsenic (As).

The selective epitaxial thin film 26 may be undoped and then doped by subsequent ion implantation methods.

Since the selective epitaxial thin film 26 acts as a stressor, the selective epitaxial thin film 26 is hereinafter referred to as the 'stresser 26'.

Subsequently, pocket / halo / LDD ion implantation (not shown) is performed on the stressor 26. In particular, a buffer oxide film (not shown) may be formed on the stressor 26 before the ion implantation is performed to prevent damage caused by ion implantation. The buffer oxide film may be formed through a deposition or an oxidation process.

As described above, when ion implantation is performed in the stressor 26, the LDD is located in the silicon germanium or silicon carbon region having less dopant diffusion, thereby improving short channel effect and simultaneously accumulating the cell region and the peripheral region. This has a possible advantage.

Next, the mask pattern (not shown) is removed. When the mask pattern is a photoresist film, the mask pattern may be removed using a dry strip, and the oxygen strip process may be performed.

As shown in FIG. 2F, a spacer oxide film 27 is formed over the entire structure including the spacer nitride film 24 in the cell region and the stressors 26 in the peripheral region.

The spacer oxide layer 27 is formed of a material having a low thermal budget, and is removed in a subsequent cell open process to be formed of a material capable of simultaneous integration of the cell region, for example, a TEOS oxide layer.

In addition, the spacer oxide film 27 is formed to an appropriate thickness defining a source / drain region, but is preferably formed to a thickness of 10 kPa to 1000 kPa.

As shown in FIG. 2G, after forming a mask pattern (not shown) to open the peripheral region, the spacer oxide layer 27 of the peripheral region is etched to form a second spacer 27A on the sidewall of the gate pattern 23. Form. The etching of the spacer oxide layer 27 may be performed under a condition of minimizing the loss of the lower stressor 26.

Subsequently, source / drain ion implantation is performed to form source / drain. Since the source / drain ion implantation proceeds on the stressor 26, diffusion is suppressed, and the ion implantation damage formed on the surface is recrystallized and dopant activated by subsequent heat treatment.

As described above, if the stressors 26 are formed after the first spacers 24A are formed, the stressors 26 are formed close to the channels, thereby increasing the channel strain effect, thereby contributing to the improvement of the operating current, and the lightly doped drain. ) Is formed in the stressor 26 material having a low dopant diffusion coefficient, thereby improving the short channel effect.

Meanwhile, in the present invention, the pocket / halo / LDD ion implantation was performed after the formation of the stressors 26. However, the embodiment of the present invention is not limited thereto, but before the recess pattern 25 is formed to optimize device characteristics, Ion implantation may be performed before the spacer nitride layer 24 is deposited, or ion implantation may be performed after the formation of the first spacer 24A.

Although the technical spirit of the present invention has been described in detail according to the above embodiments, it should be noted that the above embodiments are for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device having a strained channel according to the prior art;

2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* Explanation of symbols for important parts of the drawings

21 substrate 22 device isolation film

23 gate pattern 24 spacer nitride film

25 recess pattern 26 stressor

27: spacer oxide film

Claims (21)

Forming a gate pattern on the substrate; Forming a first spacer defining an LDD region on both sidewalls of the gate pattern; Etching the substrate between the first spacers to a predetermined depth to form a recess pattern; Forming a selective epitaxial thin film on the recess pattern; Forming a second spacer on the first spacer; And Implanting ions into the selective epitaxial thin film to form a source / drain A semiconductor device manufacturing method comprising a. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, The first spacer is a semiconductor device manufacturing method of forming a thickness of 10 ~ 300Å. Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1, Before forming the first spacer, A pocket device implantation, a halo ion implantation, and an LDD ion implantation method are performed on the substrate between the gate patterns. Claim 4 was abandoned when the registration fee was paid. The method of claim 1, After forming the first spacer, and before forming the recess pattern, A semiconductor device manufacturing method for performing pocket ion implantation, halo ion implantation, and LDD ion implantation. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1, Forming the first spacer and forming the recess pattern, A semiconductor device manufacturing method that proceeds in situ in the same chamber. Claim 6 was abandoned when the registration fee was paid. The method of claim 1, The recess pattern has a depth of 100 kV to 1000 kV. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 1, Before forming the selective epitaxial thin film, And preprocessing the recess pattern. Claim 8 was abandoned when the registration fee was paid. The method of claim 7, wherein The pretreatment is a semiconductor device manufacturing method that proceeds in-situ. Claim 9 was abandoned upon payment of a set-up fee. The method of claim 7, wherein The said pretreatment is a semiconductor device manufacturing method which advances to the temperature of normal temperature-600 degreeC. Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 1, The selective epitaxial thin film, A method for manufacturing a semiconductor device, which is a single film of silicon germanium or silicon carbon. Claim 11 was abandoned upon payment of a setup registration fee. The method of claim 1, The selective epitaxial thin film, A method for manufacturing a semiconductor device, which is a lamination structure of silicon / silicon germanium / silicon or a lamination structure of silicon / silicon carbon / silicon. Claim 12 was abandoned upon payment of a registration fee. Wherein said substrate is an NMOS and said selective epitaxial thin film is a single layer of silicon carbon or a stacked structure of silicon / silicon carbon / silicon. Claim 13 was abandoned upon payment of a registration fee. The method of claim 1, Wherein said substrate is a PMOS and said selective epitaxial thin film is a single layer of silicon germanium or a stacked structure of silicon / silicon germanium / silicon. Claim 14 was abandoned when the registration fee was paid. The method of claim 1, The selective epitaxial thin film, The semiconductor device manufacturing method formed by undoping. Claim 15 was abandoned upon payment of a registration fee. The method according to any one of claims 10 or 11 or 13, The germanium concentration in the selective epitaxial thin film is 5% to 50%. Claim 16 was abandoned upon payment of a setup registration fee. The concentration of carbon in the selective epitaxial thin film is 0.1% to 10%. Claim 17 has been abandoned due to the setting registration fee. The method of claim 1, The selective epitaxial thin film is a semiconductor device manufacturing method to form a thickness of 100 ~ 2000Å. Claim 18 was abandoned upon payment of a set-up fee. The method of claim 1, The second spacer is a semiconductor device manufacturing method for forming a thickness of 10 ~ 1000Å. Claim 19 was abandoned upon payment of a registration fee. The method of claim 1, After forming the selective epitaxial thin film, before forming the second spacer, A semiconductor device manufacturing method further comprising the step of proceeding pocket ion implantation, halo ion implantation and LDD ion implantation. Forming a gate pattern on the substrate; Forming a first spacer defining an LDD region on both sidewalls of the gate pattern; Etching the substrate between the first spacers to a predetermined depth to form a recess pattern; Forming a selective epitaxial thin film on the recess pattern; Performing pocket ion implantation, halo ion implantation, and LDD ion implantation on the selective epitaxial thin film; Forming a second spacer on the first spacer; And Implanting ions into the selective epitaxial thin film to form a source / drain A semiconductor device manufacturing method comprising a. Forming a gate pattern on a substrate having a cell region and a peripheral region; Forming a spacer nitride film along a step of the entire structure including the gate pattern; Etching the spacer nitride film of the peripheral region to form a first spacer defining an LDD region on both sidewalls of the gate pattern of the peripheral region; Etching the substrate between the first spacers of the peripheral area to a predetermined depth to form a recess pattern; Forming a selective epitaxial thin film on the recess pattern; Forming a spacer oxide film thicker than the spacer nitride film along a step of the entire structure including the selective epitaxial thin film of the peripheral region and the spacer nitride film of the cell region; Etching a spacer oxide layer in the peripheral region to form a second spacer on the first spacer; And Implanting ions into the selective epitaxial thin film to form a source / drain A semiconductor device manufacturing method comprising a.

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