KR101101595B1 - Signal interface conversion converter, Signal interface conversion receiver and Signal interface conversion transceiver - Google Patents

Abstract

The present invention relates to a signal interface conversion transmission and reception apparatus that adopts a multiplexer structure when converting a serial or parallel interface signal into a parallel or serial interface signal to reduce a clock frequency or a division ratio. A first multiplexer unit having a plurality of multiplexers that receive two bits of data each having a different order and sequentially output the same according to a control signal, and output a one-to-one correspondence to each of the plurality of multiplexers of the first multiplexer unit A transmission device having a first logic circuit portion having a plurality of logic circuit elements for logically calculating the data, a second multiplexer portion for sequentially outputting output data from the logic circuit portion in accordance with the clock signal, and the clock signal in accordance with the clock signal. From the transmitting device A logic circuit section for sequentially outputting data of a serial interface signal, a buffer section for outputting output data from the logic circuit section as a parallel interface system signal satisfying a preset number of bits, and a division for controlling the output of the buffer section The present invention provides a signal interface type transceiving device including a divided signal generator for providing a signal.

Interface, Serializer, and Deserializer

Description

Signal interface type conversion transmitter, signal interface type conversion receiver and signal interface type conversion transceiver

The present invention relates to a signal interface conversion transmission and reception apparatus, and more particularly, to adopt a multiplexer structure when converting a serial or parallel interface signal into a parallel or serial interface signal, thereby reducing a clock frequency or division ratio. Relates to a device.

Recently, due to the ease of use, a mobile device or a mobile communication terminal for transmitting and receiving information wirelessly has been widely used.

Such mobile devices and mobile communication terminals process data in a parallel manner.

However, in order to send the noise problem and high-speed data to the transmission line, data must be sent on one line. Therefore, the data of the parallel interface with multiple lines must be changed to the serial interface method. The data of the method should be changed to the data of the parallel interface method.

Recently, as the resolution and speed of transmission data increase, a conversion between the serial interface method and the parallel interface method is required, but the clock frequency used for the conversion must also vary.

However, in order to convert 8-bit parallel interface data into a serial interface method, for example, using a clock frequency of 10 MHz per 1-bit data requires a total clock frequency of 80 MHz, and vice versa. There is a problem in that the power consumption is increased because the rate is required.

In order to solve the above problems, an object of the present invention is to provide a signal interface conversion transmission and reception apparatus that reduces the clock frequency or frequency division ratio by adopting a multiplexer structure when converting a serial or parallel interface signal into a parallel or serial interface signal. will be.

In order to achieve the above object, one technical aspect of the present invention is a plurality of multiplexers that receive at least two bits of data of different order from each other of the data of the parallel interface signal and sequentially output according to the control signal. A first logic circuit section having a first multiplexer section having a plurality of logic circuit elements, and a plurality of logic circuit elements corresponding to each of the plurality of multiplexers of the first multiplexer section one-to-one to logically output data according to a clock signal; And a second multiplexer unit for sequentially outputting output data from the logic circuit unit.

According to one technical aspect of the present invention, the plurality of logic circuit elements may be a plurality of D flip flops.

According to one technical aspect of the present invention, the plurality of multiplexers may sequentially select and output data to the rising edge and the falling edge of the clock signal.

According to one technical aspect of the invention, the clock signal may be a differential signal.

According to one technical aspect of the present invention, the controller may further include a control unit for providing a control signal for controlling the operation of the multiplexers at a preset timing.

According to one technical aspect of the present invention, the control unit includes a count unit for outputting the control signal by counting data in a ripple carry method, and receiving a plurality of multiplexers by receiving the control signal from the count unit, respectively. A second logic circuit portion having a third far multiplexer portion having a plurality of D flip-flops for logically calculating an output of each of the multiplexers, one-to-one correspondence with a plurality of multiplexers of the third multiplexer portion, respectively; If the output of the D flip-flop is a preset count may include a count reset unit for resetting the output of the plurality of multiplexer of the third multiplexer unit.

In order to achieve the above object, another technical aspect of the present invention is to provide a logic circuit section for sequentially outputting data of a serial interface signal according to a clock signal, and the number of bits previously set to output data from the logic circuit section. It may include a buffer unit for outputting a parallel interface signal that satisfies the, and the divided signal generator for providing a divided signal for controlling the output of the buffer unit.

According to another technical aspect of the present invention, the logic circuit unit has a first logic circuit having a plurality of logic circuit elements for logically calculating even-numbered data of data of the serial interface signal according to the rising edge of the clock signal. And a second logic circuit block having a plurality of logic circuit elements for performing logical operation on odd-numbered data of the data of the serial interface signal according to the falling edge of the clock signal.

According to another technical aspect of the present invention, the logic circuit element may be a D flip flop.

According to another technical aspect of the present invention, the clock signal may be a differential signal.

According to another technical aspect of the present invention, the divided signal generation unit may provide the divided signal obtained by dividing the clock signal by half of the number of bits of the parallel interface signal.

According to another technical aspect of the present invention, the buffer unit corresponds one-to-one to each logic circuit element of the first and second logic circuit blocks, respectively, so that each logic of the first and second logic circuit blocks according to the division signal is provided. It may include a plurality of D flip pulls for outputting the output data of the circuit element at the same time.

In order to achieve the above object, another technical aspect of the present invention is a plurality of multi-output each of which receives at least two bits of data of different order from each other of the data of the parallel interface method signal sequentially according to the control signal A first logic circuit portion having a first multiplexer portion having a multiplexer, a plurality of logic circuit elements corresponding to each of a plurality of multiplexers of the first multiplexer portion to logically output data according to a clock signal, and the clock signal A transmission device having a second multiplexer section for sequentially outputting output data from the logic circuit section, a logic circuit section for sequentially outputting data of a serial interface system signal from the transmission device in accordance with a clock signal, and the logic circuit section. The output data from the device satisfies the preset number of bits. It may include a buffer unit for outputting a parallel signal interface system, a generator busy signal to provide a divided signal for controlling the output of the buffer unit.

According to the present invention, when converting a serial or parallel interface signal into a parallel or serial interface signal, the multiplexer structure is adopted to reduce the clock frequency or the division ratio, thereby reducing power consumption.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic configuration diagram of a signal interface conversion transceiver device of the present invention.

Referring to FIG. 1, the apparatus for translating a signal interface method according to the present invention may include a signal interface method converting transmission apparatus 100 and a signal interface method converting receiving apparatus 200.

The signal interface conversion converter 100 may convert the parallel interface signal into a serial interface signal and wirelessly transmit the converted signal.

2 is a schematic configuration diagram of a signal interface conversion transmission device of the present invention.

Referring to FIG. 2, the apparatus 100 for converting signal interface type may include a first multiplexer unit 110, a first logic circuit unit 120, and a second multiplexer unit 120.

The first multiplexer unit 110 may include a plurality of multiplexers 111 and 112.

The plurality of multiplexers 111-11N may sequentially output the input data according to the control signals S0, S1, and S2, respectively. Parallel data may be input to each of the multiplexers 111 and 112, and the parallel data input to each of the multiplexers 111 and 112 may have a different bit order.

For example, when 10 bits of parallel data are input, the first multiplexer unit 110 may include two multiplexers, and each of the multiplexers may receive 5 bits of parallel data. The 5 bits of parallel data input to the two multiplexers have different bit orders. That is, data of the 0th, 2nd, 4th, 6th, and 8th (D0, D2, D4, D6, D8) bits may be input to the first multiplexer 111, and the second multiplexer may be input. Data 112 may include first, third, fifth, seventh, and ninth (D1, D3, D5, D7, D9) bits.

At least two or more multiplexers may be included in the first multiplexer unit 110, and at least two bits of parallel data may be input to each of the two or more multiplexers. That is, the multiplexer unit 110 of the present invention may be used when converting parallel data of 4 bits or more into serial data. Accordingly, in order to convert 10-bit parallel data into serial data, when a clock signal having a frequency of 10 MHz per one bit of data is required, a clock signal having a frequency of 50 MHz may be used instead of a clock signal having a frequency of 100 MHz. Therefore, power consumption for clock signal generation can be reduced.

The multiplexers 111 and 112 of the first multiplexer unit 110 may output parallel data received in bit order according to the control signal.

The first logic circuit unit 120 may include a plurality of logic circuits 121 and 122, and the above-described logic circuit may be a D flip flop.

The plurality of D flip-flops 121 and 122 may correspond to the plurality of multiplexers 111 and 112 of the first multiplexer unit 110 one-to-one, respectively, and may logically perform output data from each of the multiplexers 111 and 112. .

The plurality of D flip flops 121 and 122 may operate by receiving clock signals CLK and CLKb, the clock signals CLK and CLKb described above may be differential signals, and the plurality of D flip flops 121 and 122 may be clock signals. Data can be selected and saved at the rising and falling edges of (CLK, CLKb), respectively.

The second multiplexer 130 may include a single multiplexer, and the second multiplexer 130 selects output data of the plurality of D flip-flops 121 and 122 according to the clock signals CLK and CLKb. Can be output sequentially.

The controller 140 may provide the control signal to control the output data of the first multiplexer 110 to be reset at every preset clock period.

3 is a schematic configuration diagram of a control unit employed in the signal interface type conversion transmission apparatus of the present invention.

Referring to FIG. 3, the control unit 140 employed in the signal interface type conversion transmission apparatus of the present invention includes a ripple carry counter 141, a third multiplexer unit 142, a second logic circuit unit 143, and a count reset unit. 144 may include.

Ripple Carry Counter (Ripple Carry Counter) (141) is a circuit that sequentially raises the seat and its operation and function is well known, so detailed description thereof will be omitted.

The third multiplexer unit 142 may include at least three multiplexers 142a to 142c, and the control signals S0, S1, and S2 of the ripple carry counter 141 are each set of three multiplexers ( 142a to 142c. In addition, the output of the counter reset 144 may also be input to each of the multiplexers 142a to 142c.

The second logic circuit unit 143 may include at least three D flip flops 143a to 143c, and the third multiplexer unit 142 corresponds to the at least three multiplexers 142a to 142c, respectively. .

The third multiplexer unit 142 outputs the three multiplexers 142a to 142c to the three D flip flops 143a to 143c, respectively, and the three D flip flops 143a to 143c are clock signals ( It can operate in synchronization with CLK, CLKb).

The outputs of the three D flip flops 143a to 143c are fed back to the ripple carry counter 141 and the count reset unit 144.

The counter reset unit 144 may be formed of an inverter and an AND element. For example, when converting 10 bits of parallel data into serial data, the counter reset unit 144 may reset the count by setting one cycle every 5 bits of the clock signal. Can be.

Accordingly, the controller 140 may control the output data of the first multiplexer 110 to be reset at every clock signal cycle of 5 bits.

4 is a schematic structural diagram of a signal interface type conversion receiving apparatus of the present invention.

Referring to FIG. 4, the apparatus 200 for receiving and converting a signal interface method may include a third logic circuit 210, a buffer 220, and a divided signal generator 230.

The third logic circuit unit 210 may include a first logic circuit block 211 and a second logic circuit block 212.

The first logic circuit block 211 may include a plurality of D flip flops 211a to 211N, and the second logic circuit block 212 may also include a plurality of D flip flops 212a to 212N.

The first logic circuit block 211 may receive data of odd bit positions among the received serial interface signal, and the second logic circuit block 212 may receive data of even bit positions.

The odd bit bit data of the received serial interface method signals is input to the plurality of D flip flops 211a to 211N, respectively, and logically operated. The even bit bit data is input to the plurality of D flip flops 212a to 212N. Each is input and logically operated.

For example, when a 10-bit serial interface signal is input, data of the first, third, fifth, seventh, and ninth bit positions are respectively provided in the plurality of D flip-flops 211a to 211N of the first logic circuit block 211. Data of the second, fourth, sixth, eighth, and tenth bit positions are input to the plurality of D flip-flops 212a to 212N of the second logic circuit block 212, respectively.

The clock signals CLK are input to the plurality of D flip flops 211a to 211N of the first logic circuit block 211 described above, and the plurality of D flip flops 212a to the second logic circuit block 212 described above. The inverted clock signal CLKb is input to 212N.

Accordingly, the plurality of D flip-flops 211a to 211N of the first logic circuit block 211 may operate at the rising edge of the clock signal CLK, and the plurality of D flips of the second logic circuit block 212 may be operated. The flops 212a-212N may operate at the falling edge of the clock signal CLKb.

The outputs of the plurality of D flip flops 211a to 211N of the first logic circuit block 211 and the outputs of the plurality of D flip flops 212a to 212N of the second logic circuit block 212 are buffer units 220. Is delivered).

The buffer unit 220 may include first to Nth D flip flops 221 to 22N, and the first to Nth D flip flops 221 to 22N may respectively include first logic circuit blocks 211. The outputs of the plurality of D flip flops 211a to 211N and the outputs of the plurality of D flip flops 212a to 212N of the second logic circuit block 212 are input.

Accordingly, data included in the received serial interface signal may be buffered.

For example, when a 10-bit serial interface signal is inputted, data of odd bit positions and even bit positions are logically operated, respectively, and its output is output to the first to Nth D flip flops 221 to 22N. Since the data of the first and second bit positions are input to the first and second D flip flops 221 and 222 almost simultaneously, the data of the third and fourth bit positions are likewise followed by the third and fourth D flip flops (not shown). ) Can be entered almost simultaneously.

Accordingly, data of the 10-bit serial interface signal can be buffered. In this case, when the data of the serial interface signal fills 10-bit positions, the buffer unit 220 may output the same and convert the data into a parallel interface signal. In this case, the divided signal generator 230 may transfer the divided signal to the buffer 220 to control the output after the buffering.

The divided signal may be generated by a clock signal CLK. In general, when the 10-bit serial interface signal is converted into a parallel interface signal, the clock signal should be divided by 10, but according to the present invention, the divided signal may be divided according to the differential signal of the clock signal. Since the first logic circuit block 211 and the second logic circuit block 212 operate, the clock signal is divided by five and the divided signal is transmitted to the buffer unit 220 to reduce the power consumption by reducing the division ratio.

5 is a schematic configuration diagram of a divided signal generation unit employed in the signal interface type conversion receiver according to the present invention.

Referring to FIG. 5, the divided signal generator 230 includes a plurality of flip-flops and logic elements to divide a clock signal, and for example, three D flip-flops 231, 233, and 234 to divide a clock signal. It may include a NAND logic element 232.

As shown, the first D flip-flop 231 performs a logic operation on the clock signal CLK and the divided signal CLK_Div, and outputs the same to the NAND logic device 232, which is then supplied by the NAND logic device 232 to the divided signal CLK_Div. ) And logically transfers the same to the second D flip-flop 233, and the second D flip-flop 233 logically transfers the same to the third D flip-flop 234 by performing a logical operation with the clock signal CLK. The D flip-flop 234 performs a logic operation with the clock signal CLK to output the divided signal CLK_Div.

6 is a diagram illustrating a clock count of the signal interface type conversion receiving apparatus of the present invention.

Referring to FIG. 6, the control signals S1, S2, and S3 of the apparatus 100 for receiving and converting a signal interface method convert a 10-bit parallel interface signal into a serial interface signal. You can see that it is reset every cycle.

7 is a diagram showing parallel data conversion of the signal interface conversion transmitter according to the present invention.

Referring to FIG. 7, the apparatus 200 for converting a signal interface type according to the present invention may divide a clock signal into 5 and convert a 10 bit serial interface type signal into a 10 bit parallel interface type signal and output the converted signal.

As described above, according to the present invention, by adopting a multiplexer structure in which data bits are separately input when converting a serial or parallel interface signal into a parallel or serial interface signal, power consumption can be reduced by reducing clock frequency or frequency division ratio. .

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not intended to limit the invention to the particular forms disclosed. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

1 is a schematic configuration diagram of a signal interface type transceiving apparatus of the present invention.

2 is a schematic configuration diagram of a signal interface type conversion transmission apparatus of the present invention.

3 is a schematic configuration diagram of a control unit employed in the signal interface type conversion transmission apparatus of the present invention.

4 is a schematic configuration diagram of a signal interface type conversion receiving apparatus of the present invention.

5 is a schematic configuration diagram of a divided signal generation unit employed in the signal interface type conversion receiving apparatus of the present invention.

Fig. 6 is a diagram showing a clock count of the signal interface type conversion receiving apparatus of the present invention.

Fig. 7 is a diagram showing parallel data conversion of the signal interface type conversion transmitting apparatus of the present invention.

<Detailed Description of Major Symbols in Drawing>

100 ... Signal Interface Conversion Transmitter

110 ... 1st multiplexer

120 first logic circuit

130 ... 2nd Multiplexer

140 ... control unit

200 ... signal interface conversion receiver

210 ... second logic circuit

220.Buffer part

230 ... division signal generator

Claims (23)

delete delete delete delete delete delete delete A logic circuit unit sequentially outputting data of a serial interface signal according to a clock signal; A buffer unit for outputting the output data from the logic circuit unit as a parallel interface scheme signal satisfying a preset number of bits; And A division signal generator for providing a division signal for controlling the output of the buffer unit; The logic circuit portion A first logic circuit block having a plurality of logic circuit elements for performing logical operation on even-numbered data among the data of the serial interface signal according to the rising edge of the clock signal; And A second logic circuit block having a plurality of logic circuit elements for performing logical operation on odd-numbered data among the data of the serial interface signal according to the falling edge of the clock signal; Signal interface type conversion receiving apparatus comprising a. The method of claim 8, And the logic circuit element is a D flip flop. The method of claim 8, And the clock signal is a differential signal. The method of claim 8, And the divided signal generator provides the divided signal obtained by dividing the clock signal by half of the number of bits of the parallel interface signal. The method of claim 8, The buffer units correspond to each logic circuit element of the first and second logic circuit blocks one-to-one, respectively and simultaneously output the output data of each logic circuit element of the first and second logic circuit blocks according to the division signal. Signal interface type conversion receiver comprising a flip pull. A first multiplexer unit having a plurality of multiplexers which receive at least two bits of data of a parallel interface type signal different from each other and sequentially output the data according to a control signal, and each of the plurality of multiplexers of the first multiplexer unit A first logic circuit portion having a plurality of logic circuit elements corresponding to the one-to-one correspondence to the clock signal, and a second multiplexer portion sequentially outputting output data from the logic circuit portion in accordance with the clock signal. A transmission device; And A logic circuit section for sequentially outputting data of a serial interface signal from the transmitter in accordance with a clock signal, a buffer section for outputting output data from the logic circuit section as a parallel interface signal satisfying a preset number of bits; And a divided signal generator for providing a divided signal for controlling the output of the buffer unit. The second logic circuit portion A first logic circuit block having a plurality of logic circuit elements for performing logical operation on even-numbered data among the data of the serial interface signal according to the rising edge of the clock signal; And And a second logic circuit block having a plurality of logic circuit elements for performing logical operation on odd-numbered data among the data of the serial interface signal in accordance with the falling edge of the clock signal. The method of claim 13, And the plurality of logic circuit elements of the first logic circuit unit are a plurality of D flip flops. The method of claim 13, And a plurality of multiplexers of the first multiplexer unit sequentially select and output data to the rising edge and the falling edge of the clock signal, respectively. The method of claim 15, And the clock signal is a differential signal. The method of claim 13, The transmitting device further includes a control unit for providing a control signal for controlling the operation of the multiplexer at the predetermined timing. The method of claim 17, wherein the control unit A counting unit for counting data in a ripple carry method and outputting the control signal; A third multiplexer unit which receives the control signal from the count unit and has a plurality of multiplexers; A third logic circuit unit having a plurality of D flip-flops for logically calculating an output of each of the multiplexers in a one-to-one correspondence to the plurality of multiplexers of the third multiplexer unit; And A count reset unit for resetting outputs of the plurality of multiplexers of the third multiplexer unit when the outputs of the plurality of D flip flops are preset Signal interface method transceiving apparatus comprising a. delete The method of claim 13, And the plurality of logic circuit elements of the first and second logic circuit blocks are D flip flops. The method of claim 13, And the clock signal is a differential signal. The method of claim 13, And the divided signal generator provides the divided signal obtained by dividing the clock signal by half of the number of bits of the parallel interface signal. The method of claim 13, The buffer units correspond to each logic circuit element of the first and second logic circuit blocks one-to-one, respectively and simultaneously output the output data of each logic circuit element of the first and second logic circuit blocks according to the division signal. Signal interface conversion transceiver device comprising a flip-flop.

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