KR101100714B1 - Burn-in board interface unit - Google Patents

Abstract

The present invention relates to an interface device for a burn-in board, which connects a driver between a driver and a burn-in board with a serial channel and transmits and receives data, and adjusts the idle time of the demultiplexer using preset dummy data to the terminal of the chip. It is an object of the present invention to provide a burn-in-board interface device for adjusting the timing between data to be transferred.
To this end, the burn-in-board interface apparatus of the present invention receives a bit value of a test pattern generated by the signal pattern generator through a parallel channel, converts it into a sequence of sequence data, and outputs it through a serial channel. A conversion unit; A second channel converter for dividing the sequence data input through the serial channel of the first channel converter into operation data for a test operation and outputting the same through a parallel channel; And a demultiplexer for processing the operation data according to the start bit of the operation data inputted from the second channel converter.

Description

Burn-in board interface device {INTERFACE APPARATUS FOR BURN­IN BOARD}

The present invention relates to an interface device for a burn-in board, and more particularly, to transmit and receive data by connecting a driver of a burn-in system and a burn-in board with a serial channel, and to adjust the down time of the demultiplexer using preset dummy data. The present invention relates to an interface device for a burn-in board for adjusting timing between data to be transmitted to a terminal of a chip.

The semiconductor manufacturing process is divided into a fabrication process (FAB) for processing wafers and a post-processing (testing / testing) for cutting chips on the wafer individually, assembling them into finished products and checking whether the finished product works properly. . Specifically, the entire process is to be manufactured by various processes (diffusion, photo, etching, ion implantation, thin film, etc.) on a silicon oxide thin film called a wafer. It is a process of mounting a circuit element. The post-process is completed after a specific test (probe / test) for each individual device on the wafer manufactured through the previous process, sawing and assembling each device (bonding, molding, etc.) It is a process to perform burn-in test and final test for individual devices.

In particular, the burn-in test in the post process is a process for detecting and dealing with premature failure by applying a high temperature and a high pressure for a predetermined time in relation to the life and reliability of the chip. Using to raise the temperature up to 125 ℃ to perform the test for the operation of the chip. In this case, the burn-in time may be set differently according to the use. Such burn-in test semiconductor equipment is classified into first generation memory burn-in test (MBT), second generation MBT, and third generation MBT. At this time, the first generation MBT is a monitoring burn-in test equipment capable of monitoring the burn-in result, the second generation MBT is a burn-in test equipment with faster processing speed and signal management capability than the first generation, and the third generation MBT is the first generation and second generation Burn-in test equipment that is functional and can test the characteristics of the device itself. In this case, the third generation MBT is commonly referred to as TDBI (Test During Burn-In).

1 is a block diagram of a conventional burn-in test apparatus.

As shown in FIG. 1, the conventional burn-in test apparatus is a TDBI, and includes a signal pattern generator 110 generating a test pattern for burn-in test and a signal for testing the chip 150 from the signal pattern generator 110. Receives the signal transmitted to each chip 150 through the connector (connector, 130) and receives a signal for the output result of the chip 150 through the connector 130 to determine the pass (pass) or failure (fail) It consists of a driver (driver, 120), burn-in board (Burn In Board: BIB, 140) on which the burn-in test chip 150 is disposed. In general, the burn-in test apparatus performs a test by mounting a chip-mounted burn-in board 140 on a furnace to test the operation of the chip in a high temperature environment of 125 ° C. Typically, the furnace can carry burn-in boards 140 of approximately 60 slots, and one burn-in board 140 can contain 480 chips.

FIG. 2A illustrates a delay time for a burn-in board and a write signal in a parallel structure, and FIG. 2B illustrates a delay time for a burn-in board and a read signal in a parallel structure.

In the burn-in board 140 of the parallel structure as shown in FIGS. 2A and 2B, the chips 150 are connected in parallel. In this case, when the signal is a write signal for inputting a signal to the chip 150, the signals are simultaneously written to the chip 150 at the same time, whereas when the signal is a read signal that the signal is output from the chip 150, The chips 150 are individually selected to read the corresponding signals.

Since most of these burn-in test apparatuses are manufactured at an inspection speed of 10 MHz, an efficient burn-in test process can be performed on chips (eg, DDR2, DDR3, etc.) requiring high-speed operating environments of about 150 MHz to 200 MHz. it's difficult.

This means that in the conventional burn-in test apparatus, when the burn-in test signal pattern is limited to an inspection speed of 10 MHz, it is possible to provide a signal pattern in which a burn-in test can be performed (see FIG. 3 (a)). . That is, the conventional burn-in test apparatus cannot perform the burn-in test itself because the signal pattern appears to be incapable of performing the burn-in test when the signal pattern for the burn-in test is set at an inspection speed of 200 MHz (FIG. 3B). ) Reference]. 3 is an explanatory diagram for a signal pattern for each inspection speed in a conventional burn-in test apparatus.

For the above reason, even in the case of a chip requiring a high speed operating environment, when performing a burn-in test using a conventional test apparatus, a signal pattern must be provided at an inspection speed of 10 MHz. , 200MHz), which not only greatly reduces the reliability of the test, but also means that it is only a performance test that opens or shorts a voltage, rather than a burn-in test that checks the actual operating state at high temperature. .

As described above, conventional burn-in test apparatus is difficult to perform burn-in tests (i.e., burn-in tests at 200MHz operating speed) for chips requiring a high speed operating environment, which is a propagation delay present in the signal path. This is because a signal pattern for a high speed operating environment of a desired form (i.e., a signal pattern having 1V) cannot be generated at a desired time (i.e., 2.5 mu s) by the delay (see FIG. 3 (b)).

Therefore, in order to perform burn-in test on a chip operating at high speed, it is necessary to reduce a propagation delay in the burn-in test apparatus to provide a desired signal pattern at a desired time.

In general, the propagation delay is related to the resistance (R) and capacitance (C), as shown in Equation 1 below.

Here, the resistance is mainly determined by the wiring resistance, and the capacitance is determined by the pin capacitance by the cap of the connector and the chip. The resistance is constant because it is a wiring resistance, but the capacitance depends on the number of chips connected in parallel to the connector connected to the burn-in board and the burn-in board. 4 is an explanatory diagram of resistance and capacitance related to propagation delay.

Referring to FIG. 4, the resistance may be constant as the wiring resistance R, and the capacitance may be represented as the sum C _total of the pin capacitances of the connector and the chip. Here, C _total may be represented as the sum of the pin capacitances of the connector and the chip, so C _total = C ₁ + C ₂ +. This can be confirmed by + C _N.

As such, the capacitance increases as the number of connectors and chips increases, and for this reason, the propagation delay in Equation 1 also increases as the number of connectors and chips increases. This indicates that it is difficult to perform burn-in tests on chips operating at high speed in the conventional burn-in test apparatus because of the large number of connectors and chips. However, the burn-in test apparatus is required to be able to process a large capacity chip at high speed.

In order to meet these demands, a method of grouping chips (ie, grouping methods) has been conventionally proposed to reduce the number of chips connected in parallel. This grouping method performs burn-in tests on each of 48 groups by grouping 10 groups on a burn-in board having 480 chips.

In this grouping method, a signal pattern generator and a driver must be connected to the burn-in board for each of the 48 groups, and thus a connector for each connection is required. In this case, a total of 48 connectors are required. By the way, one connector has essentially a plurality of channels for performing a test on a chip. For example, one connector is formed of 32 channels (i.e., 8 channels for clock CLK and control, 8 channels for address, 16 channels for data). The bus structure is adopted. These connectors have a large area of interface between the driver and the burn-in board.

As such, the grouping method is not feasible because the interface area between the driver and the burn-in board is extremely limited due to the characteristics of the connector employing a plurality of channels, and even if it is possible, the grouping method depends on the number of signal pattern generators and drivers connected to each connector. The cost also increases.

In addition, since the connector transmits signals through a plurality of channel paths as described above, differences in timing between channels may occur due to interference or distortion between adjacent channels.

Accordingly, the present invention was devised to solve the above problems, and an object thereof is to connect and transmit data between a driver of a burn-in system and a burn-in board through a serial channel, and to transmit and receive data, and to set a demultiplexer using preset dummy data. An interface device for a burn-in board is provided for adjusting the timing between data to be transmitted to a terminal of a chip by adjusting an idle time.

In order to achieve the above object, the burn-in-board interface device of the present invention receives a bit value of a test pattern generated by a signal pattern generation unit through a parallel channel, converts it into a series of sequence data, and outputs it through a serial channel. A first channel converter for; A second channel converter for dividing the sequence data input through the serial channel of the first channel converter into operation data for a test operation and outputting the same through a parallel channel; And a demultiplexer for processing the operation data according to the start bit of the operation data inputted from the second channel converter.

As described above, the present invention has an effect of efficiently utilizing the interface area between the limited driver and the burn-in board by transmitting and receiving data by connecting the burn-in system driver and the burn-in board to each other through a serial channel.

In addition, the present invention has the effect of reducing the cost by the signal pattern generation unit and the driver by using a single signal pattern generation unit and a plurality of burn-in boards through the signal distributor.

In addition, the present invention has the effect of accurately adjusting the timing between the data to be transmitted to the terminal of the chip by adjusting the idle time of the demultiplexer using the preset dummy data.

1 is a block diagram of a conventional burn-in test apparatus,
FIG. 2A illustrates a delay time for a burn-in board and a write signal having a parallel structure; FIG.
2b is a diagram illustrating a delay time of a burn-in board and a read signal of a parallel structure;
3 is an explanatory diagram for a signal pattern for each inspection speed in a conventional burn-in test apparatus;
4 is an explanatory diagram of resistance and capacitance related to propagation delay;
5 is a configuration diagram of a burn-in system to which an interface device for a burn-in board according to the present invention is applied;
6 is an exemplary diagram for a data format applied to the present invention;
7A is an explanatory diagram for a test pattern for timing of operation data;
7B is an exemplary diagram of the sequence data of FIG. 7A;
7C is an exemplary diagram of sequence data whose timing using dummy data is adjusted;
8 is an exemplary view of a burn-in board to which the burn-in board interface apparatus according to the present invention is applied.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings, It can be easily carried out. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 5 is a configuration diagram of a burn-in system to which a burn-in board interface device according to the present invention is applied, and FIG. 6 is an exemplary view of a data format applied to the present invention.

As shown in FIG. 5, the burn-in system according to the present invention includes a signal pattern generator 110, a driver 120, burn-in boards 140 to 143, and an interface device 200 for a burn-in board. Here, the signal pattern generator 110, the driver 120, the burn-in board 140, and the chip 150 are given the same reference numerals as in FIG. 1 for convenience of description.

The burn-in system of the present invention performs a write operation for inputting data to the chip 150 which is a device under test (DUT) for testing, and then performs a read operation for outputting data.

Here, the chip 150 includes a clock / control terminal CLK / Control, an address terminal, a data terminal, and the like. That is, the clock / control terminal and the address terminal are connected to a unidirectional channel that receives only a signal from the burn-in board interface device 200, thereby receiving a signal necessary to maintain a write and read operation state. In addition, the data terminal is connected to the burn-in board interface device 200 through a bidirectional channel capable of transmitting and receiving signals, thereby receiving and storing data during a write operation, and reading and transmitting previously stored data during a read operation.

The signal pattern generator 110 generates a test pattern of a signal for performing a burn-in test, and the driver 120 receives a test pattern of a signal for testing the chip 150 from the signal pattern generator 110. The binary value corresponding to the test pattern is transferred to the chip 150. In this case, the signal pattern generator 110 generates a test pattern, and accordingly, the driver 120 transmits a binary value corresponding to the test pattern through the 32 parallel channels to the burn-in board interface 200.

Hereinafter, in the present invention, the data format will be collectively described as follows for convenience of description (see FIG. 6).

In the present invention, it is assumed that a total of 32 bits is configured by sequentially enclosing a test pattern in a unit of 1 bit unit such as '0' or '1'. Herein, data of one bit unit such as '0' or '1' is collectively referred to as " single data " below, and data of 32 bit units which enumerate a series of single data and grouped together is referred to as " sequence data " Collectively. In particular, 8-bit data is divided into units that generate the operation of the chip 150 in order to allocate sequence data to each terminal of the chip 150 (ie, the clock / control terminal, the address terminal, and the data terminal). These are referred to as "clock / control data", "address data" and "execution data" and collectively referred to as "operation data".

This operation data has a start bit 301 in the most significant two bits and an information bit 302 of the remaining six bits. At this time, the start bit 301 has values of '11', '10', '01', and '00', and is used as control information of the demultiplexer 230 to be described later. That is, the demultiplexer 230 outputs the operation data to the corresponding terminal of the chip 150 according to the start bit 301 of the operation data. However, when the demultiplexer 230 checks any one of the start bits 301 of the operation data, the demultiplexer 230 has a predetermined idle time (for example, one clock) without outputting the operation data. Here, the operation data including the start bit 301 indicating the predetermined idle time is distinguished from other operation data, and is referred to as "dummy data". The information bit 302 has a value for a test operation corresponding to a corresponding terminal of the chip 150 and represents information of any one of clock / control, address, and data for the test of the chip 150.

In particular, the signal pattern generator 210 inserts a data pattern corresponding to at least one dummy data into data patterns corresponding to a plurality of operation data, thereby adjusting timing between operation data during a test operation on the chip 150. do. That is, the signal pattern generator 210 delays the timing by transferring dummy data until the clock / control terminal and the address terminal simultaneously reach the activation state, and when the clock / control terminal and the address terminal reach the activation state. The operation data is transferred to the data terminal to adjust the timing between the operation data. Detailed description thereof will be described in detail with reference to FIGS. 7A and 7B.

Burn-in-board interface device 200 is the data between the driver 120 and the burn-in board 140, serial data through a single channel instead of an interface environment in which data is transferred in parallel through multiple channels Provides the interface environment to be delivered. That is, the burn-in board interface device 200 converts the data transferred in parallel through the multiple channels from the driver 120 and transmits the data to the burn-in board 140 in serial through a single channel (ie, parallel to serial). Data transmitted in serial through a single channel is converted and transmitted to the chip 150 in parallel through multiple channels (ie, serial to parallel).

To this end, the burn-in-board interface device 200 includes a first channel converter 210, a second channel converter 220, a demultiplexer 230, and a signal distributor 240.

The first and second channel converters 210 and 220 are located at the drive 120 and the burn-in board 140, respectively, to form a single channel as a data transmission path between the driver 120 and the burn-in board 140. . In this case, the first and second channel converters 210 and 220 may be connected by a conventional wired or wireless communication method, and specifically, an optical communication method, a low voltage differential signaling method (LVDS), and an RF ( Radio Frequency) method may be used.

First, the first channel converter 210 converts multiple parallel channels (32 channels) into a single serial channel (one channel) as a data transfer path. In this case, as the data transfer path is converted from the parallel channel to the serial channel, the first channel converter 210 converts single data input through each channel of the parallel channel into sequence data and outputs the sequence data. For example, the first channel converter 210 may store "1,1,0,1,1,0,0,1,1,0,1,1,0,0" through each channel of 32 parallel channels. , 0,1,0,0,0,0,0,0,0,0,0,1,0,0,1,1,1,0 ", when single data is entered It converts into sequence data like "11011001101100010000000001001110" which is a set of data and outputs it through one serial channel.

Next, the second channel converter 220 converts a single serial channel (one channel) into a plurality of parallel channels (eight channels) as a data transfer path. In this case, as the data transfer path is converted from the serial channel to the parallel channel, the second channel converter 220 converts the sequence data input through the serial channel into motion data and outputs the same through the parallel channel. For example, when the sequence data is input such as "11011001101100010000000001001110" through one serial channel, the second channel converter 220 may read "1,1,0,1,1,0,0,1", "1. , 0,1,1,0,0,0,1 "," 0,0,0,0,0,0,0,0 "," 0,1,0,0,1,1,1,0 The input sequence data is converted into motion data divided into semantic units (here 8 bits) according to a preset data format and output through 8 parallel channels. Here, assuming that the most significant bit of the sequence data is input to the second channel converter 220 first, the second channel converter 220 may determine the operation data divided by the semantic unit from the most significant bit of the sequence data. Output sequentially. That is, the second channel converter 220 firstly “1,1,0,1,1,0,0,1” and secondly “1,0,1,1,0,0,0, 1 ", third" 0,0,0,0,0,0,0,0 ", fourth," 0,1,0,0,1,1,1,0 "are sequentially output.

The demultiplexer 230 is located at the burn-in board 140 side like the second channel converter 220.

The demultiplexer 230 selects one of a plurality of outputs and connects the inputs according to the start bit 301 of the operation data transmitted from the second channel converter 220. At this time, since the demultiplexer 230 is previously given control information for selecting each output, the demultiplexer 230 connects an output corresponding to the control information to the input. Here, the demultiplexer 230 checks the start bit 301 of the operation data as the control information and selects a corresponding output for transmitting the operation data.

In the present invention, in the demultiplexer 230, the start bit 301 of the operation data is '11' (ie, clock / control data), '10' (ie, address data), and '01' (ie, In the case of the execution data, the operation data is output to the corresponding terminal of the chip 150, and the demultiplexer 230 is the start bit 301 of the operation data is '00' (that is, the dummy data Will be described on the assumption that there is a pause time of one clock (1 CLK).

The demultiplexer 230 is a 1 × 4 demux (DEMUX), in which one input including eight parallel channels is connected to the second channel converter 220 and four including eight parallel channels. Outputs are connected to corresponding terminals of the chip 150, respectively. In this case, since the start bit 301 must distinguish four outputs, it is represented as '11', '10', '01', and '00' as 2-bit data. Specifically, the demultiplexer 230 connects the corresponding output to the clock / control terminal of the chip 150 in the case of the start bit 301 '11', and the corresponding output in the case of the start bit 301 '10'. Is connected to the address terminal of the chip 150, and in the case of the start bit 301 '01', the corresponding output is connected to the data terminal of the chip 150. In particular, the demultiplexer 230 does not perform a separate operation by setting an idle time in the case of the start bit 301 '00'.

As such, when the operation data is transferred from the second channel converter 220, the demultiplexer 230 checks the start bit 301 of the operation data and selects a terminal of the chip 150 to output the operation data. Output operation data to the corresponding terminal.

The signal distributor 240 may provide the sequence data output from the first channel converter 210 to the plurality of burn-in boards 140 to simultaneously perform the test. For example, when 10 chips 150 are mounted on one burn-in board 140, the signal distributor 240 may be connected to 480 chips 150 in one furnace through a total of 48 channels. Test can be performed (see FIG. 8 below). In this case, 48 connectors having 32 channels are conventionally required. For this reason, when the signal distribution unit 240 may be mounted 120 chips 150 on one burn-in board 140, as shown in FIG. Test can be performed on the 480 chips 150.

Additionally, as the second channel converter 220 and the demultiplexer 230 are mounted on the burn-in board 140, a material having a durability against a high temperature test environment of the furnace (for example, silicon carbide (Bill: Silicon Carbide: SiC) and silicon on insulator (SOI).

7A is an explanatory diagram for a test pattern for timing of operation data, and FIG. 7B is an exemplary diagram for the sequence data of FIG. 7A.

As illustrated in FIG. 7A, the clock / control terminal, the address terminal, and the data terminal of the chip 150 adjust timing after all of the operation data corresponding to each of the chip 150 is transferred. At this time, the operation data arriving at the corresponding terminal shows a transmission delay. That is, clock / control data is input when the clock / control terminal is ⓐ and address data is input when the address terminal is ⓑ.

However, in consideration of the transmission delay, the execution data should be input at ⓒ, but the execution data is input at ⓓ after a predetermined delay amount (ie, 1 CLK) has elapsed. This is because the execution data may be transferred before the clock / control data and the address data because the difference in the transmission delay between each operation data is weak, so that the execution data may be delivered only after the clock / control data and the address data are transferred. .

Accordingly, the burn-in system of the present invention adjusts the timing for the test when the clock / control data, the address data, and the execution data are all delivered (that is, when ⓓ) to perform the test on the chip 150.

7B illustrates an example of a test pattern generated by the signal pattern generator 210 in the case of FIG. 7A.

As described above, each operation data is distinguished according to the start bit 301. That is, the clock / control data has a start bit 301 of '11' 401 and the address data has a start bit 301 of '10' 402. The dummy data has a start bit 301 of '00' 403. The execution data has a start bit 301 of '01' 404. Therefore, the clock / control data is input to the clock / control terminal in FIG. 7A, the address data is input to the address terminal in FIG. 7A, and the execution data is data after one clock (1 CLK) by the operation data C in FIG. 7A. It is input to the terminal. When the dummy data is transferred to the demultiplexer 230, the demultiplexer 230 does not perform a separate operation for one clock.

7C is an exemplary diagram of sequence data whose timing using dummy data is adjusted.

As illustrated in FIG. 7C, the signal pattern generator 210 may generate a test pattern whose timing is adjusted using the dummy data 501. That is, the signal pattern generator 210 may adjust the timing delay time in clock units by forming a test pattern in which at least one dummy data 501 is inserted between the operation data.

Here, the signal pattern generator 210 needs to generate sequence data additionally when inserting the plurality of dummy data 501 by generating and transferring a test pattern with 32 bits of sequence data.

Specifically, when the execution data 505 is delayed by two clocks after the clock / control data 503 and the address data 504, second sequence data is generated in addition to the first sequence data. That is, two dummy data 501 are inserted between the clock / control data 503, the address data 504, and the execution data 505 for two clock delays. Since this forms 32 bits of first sequence data, execution data 505 is included in the second sequence data. In this case, since the second sequence data does not need to perform a separate operation after the execution data 505, the dummy data 502 is additionally inserted to configure 32 bits. Through this, the burn-in system of the present invention may insert at least one dummy data into the test pattern to adjust the timing delay between the operation data by at least one clock unit.

8 is an exemplary view of a burn-in board to which the burn-in board interface apparatus according to the present invention is applied.

In the burn-in system of FIG. 8, burn-in boards 140a to 140c are mounted inside the furnace to perform burn-in tests on a total of 480 chips 150. Here, the reference numerals of the second channel converter 220, the demultiplexer 230, and the signal distributor 240 mounted on the burn-in board 140a are the same as in FIG. 5.

At this time, one burn-in board 140a may mount a maximum of 10 chips 150 when the chips 150 are arranged in test units satisfying capacitance requirements required for a high speed operating environment. Such a burn-in system may perform a test on a total of 480 chips 150 by connecting a single signal distribution unit 240 to the burn-in boards 140a to 140c through a total of 48 channels.

Therefore, in the burn-in system, as the number of chips 150 mounted on a board increases while satisfying a capacitance condition required for a high speed operating environment, the number of channels for connection between the signal distributor 240 and the board decreases.

In the above, the present invention has been illustrated and described with reference to specific preferred embodiments, but the present invention is not limited to the above-described embodiments, and the present invention is not limited to the spirit of the present invention. Various changes and modifications will be possible by those who have the same.

110: signal pattern generation unit 120: driver
140, 141, 142, 143: Burn-in board 150: Chip
200: burn-in board interface device 210: first channel conversion unit
220: second channel converter 230: demultiplexer
240: signal distribution unit

Claims (7)

A first channel converter for receiving a bit value of the test pattern generated by the signal pattern generator through a parallel channel, converting the bit value into a series of sequence data, and outputting the sequence data;
A second channel converter for dividing the sequence data input through the serial channel of the first channel converter into operation data for a test operation and outputting the same through a parallel channel; And
A demultiplexer for processing the corresponding operation data according to the start bit of the operation data inputted from the second channel converter
Burn-in board interface device comprising a. The method of claim 1,
The operation data,
Burn-in-board interface device, characterized in that any one of the clock / control data, the address data, the execution data and the dummy data according to the start bit. The method of claim 2,
The demultiplexer,
When the operation data is any one of clock / control data, address data, and execution data, the operation data is output to a corresponding terminal of the chip under test,
If the operation data is dummy data, the burn-in-board interface device having a pause time in clock units without performing an operation. The method of claim 3, wherein
The signal pattern generation unit,
And adjusting the timing between each operation data to generate the test pattern by inserting at least one dummy data between the clock / control data, the address data, and the execution data. The method of claim 4, wherein
Timing between the operation data,
And the clock / control data, the address data and the execution data are all adjusted as they are input to each terminal of the chip. 6. The method according to any one of claims 1 to 5,
A signal distributor for providing sequence data output through the serial channel of the first channel converter to a plurality of burn-in boards
Burn-in board interface device further comprising. The method according to claim 6,
The first channel converter is disposed on the driver side,
The second channel converter and the demultiplexer are disposed on the burn-in board side.

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