KR101097601B1 - Liquid Crystal Display device - Google Patents

Abstract

As the resolution is increased, a liquid crystal display including a gate driver corresponding to pixels is disclosed.

A liquid crystal display of the present invention includes a plurality of pixel stages arranged along a plurality of gate lines;

A first gate driver in which odd shift registers are arranged on one side of the pixel terminal; And a second gate driver in which even-numbered shift registers are arranged on the other side of the pixel terminal.

High Resolution, Gate Driver, Shift Register, Level Shifter

Description

Liquid crystal display device

1 is a detailed block diagram showing a conventional liquid crystal display device.

2 is a view showing a liquid crystal panel in which a conventional gate driver is embedded;

3 is a view showing another liquid crystal panel in which a conventional gate driver is incorporated.

4 is a view showing a liquid crystal panel of a liquid crystal display device with a built-in gate driver according to a first embodiment of the present invention.

5 is a view showing a liquid crystal panel of a liquid crystal display device with a built-in gate driver according to a second embodiment of the present invention.

6 is a view showing a liquid crystal panel of a liquid crystal display device with a built-in gate driver according to a third embodiment of the present invention.

7 is a view showing a liquid crystal panel of a liquid crystal display device with a built-in gate driver according to a fourth embodiment of the present invention.

8 is a view showing a liquid crystal panel of a liquid crystal display device with a built-in gate driver according to a fifth embodiment of the present invention.

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device for facilitating the implementation of a gate driver using amorphous polysilicon (a-Si) or low temperature polysilicon (LTPS) technology at high resolution.

Recently, with the rapid development of the information society, the need for a flat panel display device having excellent characteristics such as thinning, light weight, and low power consumption has emerged. Liquid crystal display devices (Liquid Crystal Display device) is excellent in resolution, color display, image quality, etc. are actively applied to notebooks and desktop monitors.

In general, a liquid crystal display device arranges two substrates on which electrodes are formed so that the surfaces on which the two electrodes are formed face each other, forms a liquid crystal material between the two substrates, and applies a voltage to the two electrodes to generate an electric field. By moving the liquid crystal molecules, the image is expressed by the transmittance of light that varies accordingly.

1 is a detailed block diagram showing a conventional liquid crystal display device.

As shown in FIG. 1, a conventional liquid crystal display device drives a liquid crystal panel 2 in which liquid crystal cells Clc are arranged in a matrix, and drives gate lines GL1 to GLn of the liquid crystal panel 2. To control the gate driver 4, the data driver 6 for driving the data lines DL1 to DLm of the liquid crystal panel 2, the gate driver 4 and the data driver 6. The timing controller 10 is provided. The liquid crystal display device means a built-in liquid crystal display device in which the gate driver 4 is provided in the liquid crystal panel 2.

The liquid crystal panel 2 includes a thin film transistor TFT and a liquid crystal cell Clc formed at each pixel area defined by the intersection of the gate lines and the data lines.

The gate driver 4 includes a plurality of shift registers S / R or a plurality of shift registers S / R and a plurality of level shifts L / S for sequentially supplying a scan signal to each gate line. Will be provided. The plurality of shift registers S / R are controlled by the start pulse SP signal of the timing controller 10 and predetermined clock signals. At this time, the start pulse SP is input to the first shift register S / R, and the remaining ones are input. The output signal of the previous stage shift register is input to the second to nth shift registers S / R2 to S / Rn.

The data driver 6 outputs a pixel signal of one line for each horizontal period H1, H2 .. in response to the data control signals SSP, SSC, SOE, and POL from the timing controller 10. To DL1 to DLm.

The timing controller 10 generates a start pulse SP, which is a control signal for controlling the gate driver 4, and predetermined clock signals, and control signals SSC, SSP, which control the data driver 6. SOE), etc.

2 is a diagram illustrating a liquid crystal panel in which a conventional gate driver is embedded.

As shown in FIG. 2, the gate driver 4 is composed of n shift resistors S / R1 to S / Rn using amorphous silicon (a-Si) or low temperature polysilicon (LTPS) technology. . The n shift registers are each connected to a corresponding gate line. Pixel terminals (not shown) are connected to each gate line. Each shift register S / R is connected to a gate line to sequentially supply the scan signal to the gate line. The shift registers S / R receive a scan signal (ie, gate voltage) in response to a start clock SP and a predetermined clock signal generated by the timing controller to control the gate driver 4. It is supplied to each pixel stage via.

Referring to FIG. 2, when the start pulse SP generated by the timing controller is supplied to the first shift register S / R1, the first shift register S / R1 is connected to the first gate line GL1. The scan signal is supplied to the first gate line GL1, and the first gate line GL1 supplies the scan signals to a first pixel pixel. At this time, the shift registers S / R supply the scan signal to the next shift register S / R, and the scan signal is a voltage value for turning on / off operation of the pixel stage. It converts to. And a second shift register S / R2 in which an output signal (that is, a scan signal) generated by the start pulse SP signal supplied to the first shift register S / R1 is next to the first shift register. Is supplied. The second shift register supplies the scan signals to a second gate line GL2, and the second gate line GL2 supplies the scan signals to a second pixel pixel, and the scan signals are again provided. It is supplied to the 3 shift registers (S / R3).

As such, a scan signal is supplied to the shift registers S / R in response to a start pulse SP and predetermined clock signals for controlling the gate driver 4 in the timing controller. The scan signal is supplied to the gate lines corresponding to the first and second Rs, and the gate lines supply the scan signals corresponding to each pixel terminal.

3 is a view showing another liquid crystal panel in which a conventional gate driver is embedded.

As shown in FIG. 3, the gate driver includes n shift registers S / R and n level shifters L / S. The shift registers S / R respectively output level signals corresponding to the shifter registers S / R in response to a start pulse SP and a predetermined clock signal supplied from a timing controller. / S) The level shifters L / S supply the output signals to respective pixel stages through gate lines corresponding to the level shifters L / S. In this case, the level shifters L / S convert the output signals into scan signals of which the voltage is leveled so that turn-on / off operation of each pixel stage may be performed.

When the start pulse SP generated by the timing controller is supplied to the first shift register S / R1, the first shift register S / R1 supplies an output signal to the first level shifter L / S. do. The first level shifter L / S1 supplies scan signals for leveling a voltage to a first pixel terminal (not shown) via a first gate line GL1 and at the same time, the first shift register. S / R1 supplies the output signals to the second shift register S / R2. In this case, the first pixel pixel is turned on. The output signal input to the second shift register S / R2 is supplied to the second level shifter L / S2. The output signal inputted to the second level shifter L / S2 is a voltage leveled scan signal that turns on a second pixel terminal (not shown) via the second gate line GL2. Supplied. The shifter registers S / R may output an output signal corresponding to the control signals (start pulse SP and a predetermined clock signal) generated by the timing controller and the shifter registers S / R, respectively. It supplies the output signal to the shifter registers S / R present in the next stage while supplying the corresponding level shifters L / S.

In this case, the level shifters L / S output a scan signal for turning on / off the pixel terminal. The level shifters L / S convert scan signals supplied to the shifter registers S / R into voltages capable of turning on / off driving of each pixel stage. The pixels are sequentially supplied to each pixel terminal via gate lines corresponding to the shifters L / S.

Each pixel terminal receives the scan signal converted into a voltage value to turn on / off driving.

As shown in FIG. 2, a gate driver composed of n shift registers S / R is connected to one line of each pixel stage, and as shown in FIG. The gate driver including the shift registers S / R and n level shifters L / S is connected to each pixel terminal and a gate line. However, in the case of a model having high resolution and having high resolution, it is difficult to design a thin film transistor and various lines of the gate driver to correspond to the pixel size due to the limitation of process capability. That is, as the resolution increases, the pixel size decreases, and as the number of pixels increases, the area of the shift register or the shift register and the level shifter connected to the gate line of each pixel stage also decreases. Should be. However, there is a limit in design margin or process capability when designing a gate driver composed of a shift register or a shift register and a level shifter. Therefore, while the pixel size becomes smaller as the resolution is higher, the area of the gate driver is difficult to reduce.

An object of the present invention is to provide a liquid crystal display device in which the arrangement of the gate driver is changed to correspond to a high resolution pixel.

According to a preferred embodiment for achieving the above object, a liquid crystal display according to the present invention comprises a plurality of pixel stages arranged along a plurality of gate lines; A first gate driver in which odd shift registers are arranged on one side of the pixel terminal; And a second gate driver having even-numbered shift registers arranged on the other side of the pixel stage.

According to another preferred embodiment of the present invention, a liquid crystal display of the present invention comprises a plurality of pixel stages arranged along a plurality of gate lines; And first and second gate drivers arranged at respective shift registers consecutive to both sides of the pixel stage.

According to still another preferred embodiment of the present invention, a liquid crystal display of the present invention comprises: a plurality of pixel stages arranged along a plurality of gate lines; And a gate driver in which odd-numbered shift registers are arranged along a first column and even-numbered shift registers are arranged along a second column on one side of the pixel terminal.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

4 is a view showing a liquid crystal panel of a liquid crystal display device with a gate driver according to a first embodiment of the present invention.

As shown in FIG. 4, n shift registers S / R exist in the gate driver. The n shift registers S / R are divided into n / 2 and divided into an even-numbered shift register S / R and an even-numbered shift register S / R. The first gate driver 104 includes the odd-numbered shift registers S / R and the second gate driver 105 includes the even-numbered shift registers S / R. The first gate driver 104 and the second gate driver 105 are provided at both sides of the pixel array.

 Each of the nth shift registers S / R corresponds to a start pulse SP generated by a timing controller (not shown) and a scan signal corresponding to the odd shift register in response to predetermined clock signals. The gate lines are supplied to the odd pixel pixels. The odd-numbered shift registers S / R convert the scan signal into a voltage value for turning the odd-numbered pixel to turn on / off, and thus the odd-numbered pixel via the odd-numbered gate line. The scan signal converted into a voltage value is supplied to a (Pixel) terminal.                     

As shown in FIG. 4, the first shift register S / R1 present in the first gate driver 104 may receive a voltage in response to a start pulse SP signal generated by a timing controller (not shown). The scan signal converted into a value is supplied to a first pixel terminal (not shown) via the first gate line GL1. In this case, the first pixel (Pixel) terminal is turned on and is driven. The first shift register S / R1 supplies the scan signal to a second shift register S / R2 existing in the second gate driver 105. The second shift register S / R2 supplies the scan signal to a second pixel terminal (not shown) via the second gate line GL2. In this case, the second pixel pixel is turned on and driven. The scan signal is again supplied to the third shift register S / R3 of the first gate driver 104. Accordingly, the first gate driver 104 includes a first shifter register S / R1, a third shifter register S / R1, a fifth shifter register S / R5, and the like. The second gate driver 105 includes a second shifter register S / R2, a fourth shifter register S / R4, a sixth shifter register S / R6, and the like.

Therefore, in the case of a model having a high resolution, even if each pixel size becomes small, the odd-numbered shift registers S / R and the even-numbered shift registers S / R are provided to the gate drivers located on both sides of the pixel array. Each of the gate drivers can be easily disposed in an area corresponding to at least one pixel size.

5 is a diagram illustrating a gate driver of a liquid crystal display according to a second exemplary embodiment of the present invention.

As shown in FIG. 5, the shift registers S / R output the output signal in response to a start pulse SP generated by a timing controller (not shown) and predetermined clock signals. Feed the fields. In this case, the output signal has a low value and a high value and is supplied to the level shifters L / S. The level shifters L / S convert the output signal into a scan signal leveled to a voltage value and supply the same to the pixel stages via gate lines corresponding to the level shifters L / S. . In this case, the odd-numbered shift register and the level shifter are provided in the first gate driver 114, and the even-numbered shift register and the level shifters are provided in the second gate driver 115.

The first shift register S / R1 existing in the first gate driver 114 may output an output signal in response to the start pulse SP generated by a timing controller (not shown). Supply to the first level shifter L / S1 existing in correspondence with R1). The first level shifter L / S1 converts the output signal into a scan signal leveled to a voltage value to turn on / off an operation of the first pixel pixel via the first gate line GL1. The scan signal is supplied to the first pixel stage. At the same time, the first level shifter L / S supplies the scan signal to a second shift register S / R2 present in the second gate driver.

The second shift register S / R2 supplies the output signal to a second level shifter L / S2. The second level shifter L / S2 converts the output signal into a scan signal leveled to a voltage value so that the second pixel terminal can turn on / off. The scan signal is supplied to the second pixel (Pixel) terminal via the second gate line. As such, the second level shifter L / S2 supplies the scan signal to the first gate driver 114 having the odd shift register S / R and the level shifter L / S. Each shifter register and level shifter repeats the above process.

Therefore, as the resolution increases, the pixel shift size (S / R) is used so that the gate driver is connected to each pixel as the pixel size decreases and the number of pixels increases. And the level shifter (L / S), the even-numbered shift register (S / R), and the level shifter (L / S) are separated from each other so as to be divided into a first gate driver and a second gate driver. Accordingly, the gate driver can be implemented according to the pixel number and size even at a high resolution by using a gate driver having a limited area.

FIG. 6 is a diagram illustrating a liquid crystal panel of a liquid crystal display device having a gate driver according to a third embodiment of the present invention.

As shown in FIG. 6, the LCD according to the present invention includes a first gate driver 124 having n / 2 shifter registers and a second gate driver 125 having another n / 2 shifter registers. ). The first gate driver 124 and the second gate driver 125 are composed of respective shifter registers S / R. The shifter registers S / R turn-on / off a scan signal of each pixel in response to a start pulse SP generated by a timing controller (not shown) and a predetermined clock signal. Convert it to voltage so that

The first shifter register S / R1 in the first gate driver 124 converts a scan signal into a voltage value in response to a start pulse SP signal generated by a timing controller (not shown), thereby shifting the first shift. The first pixel line is supplied to the first pixel pixel via the first gate line GL1 corresponding to the register S / R1. At the same time, the first shifter register S / R1 supplies the scan signal to the second shifter register S / R2 present in the first gate driver 124. The second shifter register S / R2 receives the scan signal, converts the scan signal into a voltage value, and then supplies the scan signal converted into a voltage value to the second pixel pixel terminal via the second gate line GL2. do. At the same time, the second shifter register S / R2 supplies the scan signal to the third shifter register S / R3 present in the second gate driver 125. The third shifter register S / R3 converts the scan signal into a voltage value to enable turn-on / off operation of the third pixel terminal through the third gate line GL3. At the same time, the third shifter register S / R3 supplies a scan signal to the fourth shifter register S / R4 present in the second gate driver 125. The fourth shifter register S / R4 performs the same operation as described above.

As the resolution increases, the pixel size decreases and the pixels increase, so that each of the n / 2 separate shifter registers are provided so that the gate driver is connected to each pixel. Divided into a first gate driver and a second gate driver. Accordingly, the gate driver can be implemented according to the pixel number and size even at high resolution using a gate driver having a limited area. The first gate driver and the second gate driver may be placed on both sides of the pixel array.

FIG. 7 illustrates a liquid crystal panel of a liquid crystal display device with a gate driver according to a fourth embodiment of the present invention.

As shown in FIG. 7, the liquid crystal display according to the present invention has a first gate driver 134 provided with n / 2 shift registers S / R and level shifters L / S, and another n / 2. And a second gate driver 135 having two shifter registers S / R and level shifters L / S. The shift registers S / R supply an output signal to the level shifters L / S existing in correspondence with the shift registers S / R, and the level shifters L / S are output signals. Is converted into a voltage value to enable turn-on / off operation of each pixel stage to the pixel stages through the gate lines corresponding to the level shifters L / S. Supply a scan signal converted into a voltage value.

The first shift register S / R1 of the first gate driver 134 may output an output signal to the first level shifter L / S1 in response to a start pulse SP signal generated by a timing controller (not shown). To supply. The first level shifter L / S1 converts the output signal into a voltage value and supplies it to the first pixel Pixel. At the same time, the first shifter register S / R1 supplies an output signal to the second shifter register S / R2 present in the first gate driver 134. The second shifter register S / R2 supplies the output signal to the second level shifter L / S2. The second level shifter L / S2 converts the output signal into a scan signal leveled to a voltage value so that the second pixel pixel may turn on / off. The scan signal is supplied to the second pixel pixel terminal via the second gate line GL2. At the same time, the second level shifter L / S2 supplies a scan signal to the third shifter register S / R3 existing in the second gate driver 135. The third shifter register S / R3 supplies the scan signal to the third level shifter L / S3. The third level shifter L / S3 converts the scan signal into a voltage value to enable turn-on / off operation of the third pixel terminal. The third level shifter L / S3 supplies the scan signal converted into the voltage value to the third pixel pixel via the third gate line GL3. At the same time, the third shift register S / R3 supplies a scan signal to the fourth shifter register S / R4 existing in the second gate driver 135. The fourth shift register S / R4 supplies the scan signal to the fourth level shifter L / S4. The fourth level shifter L / S4 converts the scan signal into a voltage value to turn on / off the fourth pixel terminal. The fourth level shifter L / S4 supplies the scan signal converted into the voltage value to the fourth pixel terminal through the fourth gate line GL4. Therefore, the fourth pixel Pixel is turned on.

The shift registers S / R and the level shifters L / S present in the first gate driver 134 and the second gate driver 135 operate as described above. As the resolution increases, the pixel is driven by the first gate driver and the second gate driver to connect the gate driver with the respective pixels as the pixel size decreases and the pixels increase. (Pixel) It is provided on both sides of the array. Accordingly, the gate driver can be implemented according to the pixel number and size even at a high resolution by using a gate driver having a limited area.

8 is a view showing a liquid crystal panel of a liquid crystal display device with a gate driver according to a fifth embodiment of the present invention.

As shown in FIG. 8, the LCD according to the present invention has a first column 144 having n / 2 shifter registers S / R and another n / 2 shifter registers S / R. Gate driver 145 including a second column 146 having the same. The shift registers S / R perform turn-on / off operations of each pixel of the scan signal in response to a start pulse SP generated by a timing controller (not shown) and a predetermined clock signal. Convert it to voltage so that it can.

The first shift register S / R1 in the first column 144 turns the scan signal on the first pixel stage in response to the start pulse SP signal generated by a timing controller (not shown). In order to perform on / off operation, the voltage is converted into a voltage value and supplied to the first pixel pixel via the first gate line GL1. At the same time, the first shift register S / R1 supplies the scan signal to the second shift register S / R2 present in the second column 146. The second shift register S / R2 converts the scan signal into a voltage value to enable the turn-on / off operation of the second pixel terminal and converts the scan signal into a second pixel through the second gate line GL2. Supply to the (Pixel) stage. At the same time, the second shift register S / R2 supplies the scan signal to the third shifter register S / R3 present in the first column 144. The third shifter register S / R3 then supplies a scan signal to the shifter register and repeats the above process.

As described above, the gate drivers of the liquid crystal display according to the present invention are connected through the pixel terminal and the gate line, respectively. As the resolution increases, as the size of the pixels decreases and the number of pixels increases, the area of the shift register or the shift register and the level shifter connected to the gate line of the pixel stage increases. However, since the gate driver has a limited area, one gate driver may be disposed with at least one pixel stage.

That is, according to embodiments of the present invention, as the resolution increases, the gate driver is disposed on the left / right or one side of the pixel array. Accordingly, the gate driver can be integrated regardless of the process capability by using a space that can be integrated at one end of the gate driver as at least one pixel size.

As described above, according to the liquid crystal display device according to the present invention, when a high resolution is required, the gate driver is provided on both sides of the pixel array, thereby reducing the cost of producing a new gate driver suitable for high resolution. The gate driver can be reduced and can be connected to at least one pixel stage.

Claims (10)

A plurality of pixel stages arranged along a plurality of gate lines; A first gate driver disposed on one side of the pixel terminal and arranged with a first group of shift registers electrically connected to an odd-numbered gate line among the plurality of gate lines; And a second gate driver positioned on the other side of the pixel terminal and arranged with a second group of shift registers electrically connected to even-numbered gate lines among the plurality of gate lines. The output terminal of the shift registers of the first group is electrically connected to an input terminal of the shift register of the second group through a corresponding odd-numbered gate line, and the output terminal of the shift registers of the second group includes a corresponding even-numbered gate line. Is electrically connected to an input terminal of the shift register of the first group through And a first shift register among the shift registers of the first group provides a scan signal to a corresponding first odd-numbered gate line in response to a start pulse signal provided from a controller. The method of claim 1, Each output signal of the registers of the first group is supplied to each of the shift registers of the second group via the corresponding odd-numbered gate lines, and each output signal of the shift registers of the second group is corresponding to the evenness. And a plurality of shift registers of the first group through the first gate line. The method of claim 1, And a level shifter is connected to the rear ends of the shift registers. A plurality of pixel stages arranged along a plurality of gate lines; A first gate driver positioned at one side of the pixel stage and having a plurality of continuous shift registers and providing an output signal to a corresponding gate line; And And a second gate driver positioned on the other side of the pixel terminal, the second gate driver having a plurality of continuous shift registers and providing an output signal to a corresponding gate line. The output signal of the odd shift register among the plurality of shift registers of the first gate driver is provided to an input terminal of the successive even shift register, and the output of the odd shift register among the plurality of shift registers of the second gate driver is provided. The signal is provided to the input of consecutive successive shift registers, The output signal of the even-numbered shift register of the first gate driver is provided to an input terminal of the odd-numbered shift register of the second gate driver consecutive through the corresponding gate line. The output signal of the even-numbered shift register of the second gate driver is supplied to an input terminal of the odd-numbered shift register of the first gate driver consecutive through the corresponding gate line, A first odd shift register of the plurality of shift registers of the first gate driver provides an output signal to a corresponding gate line and a continuous even shift register in response to a start pulse signal from a controller; Display. delete delete delete The method of claim 4, wherein And a level shifter is connected to a rear end of the successive shift registers. A plurality of pixel stages arranged along a plurality of gate lines; And A gate driver in which odd shift registers are arranged along a first column and even-numbered shift registers are arranged along a second column on one side of the pixel terminal, An output terminal of the odd shift register is electrically connected to an input terminal of successive even shift registers, and an output terminal of the even shift shift registers is electrically connected to an input terminal of successive odd shift registers, A first odd shift register of the odd shift registers supplies an output signal to a corresponding first odd gate line in response to a start pulse signal from a controller; And an output signal of the first odd shift register is provided to a first even shift register among the even shift registers. The method of claim 9, And each output signal of the odd-numbered shift registers is supplied to a corresponding gate line and each of the even-numbered shift registers, respectively.

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