KR101097438B1 - Solid State Storage System For Controlling of Wear-Leveling Flexibly and Method of Controlling the Same - Google Patents

Abstract

A semiconductor storage system is disclosed. The disclosed semiconductor storage system includes a buffer unit for sequentially loading a plurality of mapping pages in which mapping information and deletion counts are stored, and a reference count of the target block and a target block to be replaced by a worn block. And a memory controller configured to set the number of the mapping pages to be searched, sample the mapping pages, and perform wear leveling.

Flash memory, wear leveling, search, mapping

Description

Solid State Storage System For Controlling of Wear-Leveling Flexibly and Method of Controlling the Same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor storage system and a control method thereof, and more particularly, to a semiconductor storage system and a method of controlling the same.

In general, nonvolatile memory is used as a storage memory for many portable information devices. Furthermore, in recent years, a solid state drive (SSD) using NAND flash memory has been released in place of a hard disk drive (HDD) in a personal computer (PC), which is expected to rapidly invade the HDD market.

Typically, controlling a data file in such a semiconductor storage system, such as an SSD, consists of writing, deleting, and updating the actual data in a page designated by a logical address that can identify the data file. More specifically, the logical address and the physical address of the data storage area are mapped to FTL (Flash Translation Layer) translation. Subsequently, if a logical address is referenced according to a command of a host (not shown), data may be written, deleted, and read at a corresponding location designated by a physical address mapped to the logical address. The physical address is page information of a memory area or position information of a sub block.

When updating data of a NAND flash memory cell, the data of the corresponding cell must be erased once and the new data must be programmed again since it is a nonvolatile memory. However, instead of programming the data evenly in all the memory cells during data programming, the program may be frequently concentrated in a specific cell area. In other words, depending on the data, a certain cell area or some cells may wear out due to the life of the cell due to frequent program and erase processes. However, even if there are cells that are not yet fresh, the performance of the semiconductor storage system as a whole can be limited by some 'old' cells.

This allows wear leveling to control the uniform use of cells by changing the physical location of the storage cells within each memory zone or plane before each memory cell wears out. leveling).

In order to perform the wear leveling, information about the number of deletions of all the blocks is stored in the NAND flash memory area, and when the wear leveling is required, the information is loaded into the RAM buffer to search for replaceable blocks and physically I changed the location.

However, with the recent trend of large-capacity SSDs, as the number of blocks in the memory area increases, the memory of the RAM buffer, which has to load the erase count of all of these blocks, becomes inevitable. However, memory growth of the RAM buffer is limited by cost and chip area.

An object of the present invention is to provide a semiconductor storage system for controlling wear leveling.

Another object of the present invention is to provide a control method of a semiconductor storage system for controlling wear leveling.

In order to achieve the technical object of the present invention, the semiconductor storage system according to an embodiment of the present invention, the buffer unit for sequentially loading a plurality of mapping pages in which the mapping information and the number of deletion is stored and the replacement of the worn block And a memory controller configured to perform wear leveling by sampling mapping pages by setting a reference number of deletion of the target block and a number of the mapping pages to be searched for the target block to find a target block.

In order to achieve the technical object of the present invention, the semiconductor storage system according to another embodiment of the present invention, when the wear leveling, the reference of the number of times of deletion of the block to be replaced of the worn block of the memory block and the And a memory controller configured to find a first block to be replaced as a target block and replace the worn block by setting a criterion of the number of search targets for the block to be replaced using information of the block.

In accordance with another aspect of the present invention, a method of controlling a semiconductor storage system may include: setting a first reference to determine a number of deletions of a target block to be replaced corresponding to a worn block during wear leveling; Setting the second criterion of the target block search according to the number of times of deleting, searching for the target block by the first and second criteria, and if the target block is not found, varying and updating the first criterion. And influencing a next target block search condition.

According to one embodiment of the present invention, even if the size of the memory area is increased, it is not necessary to add the size of the buffer unit for temporary storage of the mapping information and the number of deletions, and rather, it is possible to keep the size smaller than the conventional one. The execution time of wear leveling can be shortened by loading mapping information and the number of times of deletion only for the worn block, and setting conditions for the number of times of deletion and conditions for the number of times of searching. Therefore, while reducing the size of the buffer portion and shortening the execution time of the wear leveling, it is possible to improve the operating performance and cost efficiency of the semiconductor storage system.

Hereinafter, a semiconductor storage system according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

First, a semiconductor storage system according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 and 2.

1 is a block diagram of a semiconductor storage system 100 according to an embodiment of the present invention. 2 is a block diagram conceptually illustrating a relationship between a mapping table of a logical physical address and a buffer unit 120. Here, the semiconductor storage system 100 is exemplified as a storage system using NAND flash memory.

1 and 2, the semiconductor storage system 100 includes a host interface 110, a buffer unit 120, an MCU 130, a memory controller 140, and a memory region 150.

First, the host interface 110 is connected to the buffer unit 120. The host interface 110 transmits and receives a control command, an address signal, and a data signal between an external host (not shown) and the buffer unit 120. The interface method between the host interface 110 and an external host (not shown) is any one of serial Serial Technology Attachment (SATA), parallel Parallel Advanced Technology attachment (PATA), and SCSI, Express Card, and PCI-Express methods. Can be and is not limited.

The buffer unit 120 buffers output signals from the host interface 110 or temporarily stores mapping information between logical addresses and physical addresses, block allocation information of a memory area, the number of times of block deletion, and data received from the outside. The buffer unit 120 may be a buffer using static random access memory (SRAM) or dynamic random access memory (DRAM). As shown in FIG. 2, (a) from the sector view, the 1000th sector of the logical block is viewed from the NAND side of the memory area 150, showing the 30th page of the 200th block of the actual physical block. The buffer unit 120 stores the mapping information and the number of times of deletion of the block 200 (block 200) that is substantially accessed. This is only an example, but is not limited thereto. It is intended to conceptually illustrate that whenever a block is deleted, mapping information and the number of times of deletion of the worn block or worn block are loaded.

In particular, since the buffer unit 120 according to an embodiment of the present invention does not load the number of deletions of all the conventional blocks, and only loads the weared blocks as described above, the size of the buffer unit 120 may be small. Increase the efficiency

The microcontrol unit 130 may transmit and receive a control command, an address signal, a data signal, and the like between the host interface 110, or may control the memory controller 140 by such signals.

The memory controller 140 selects a predetermined NAND flash memory device ND among the plurality of NAND flash memory devices of the memory area 150, and provides a write, delete, or read command. In particular, the memory controller 140 according to an embodiment of the present disclosure may flexibly control wear leveling. That is, the memory controller 140 may control the search condition of the target block required for wear leveling and the number of searches using two criteria to efficiently manage the equal use of the memory life.

Conventionally, the erase count information of all the blocks is stored in a lump in a predetermined area of the memory area 150. Thus, when the wear leveling point is reached, the erase count information of all the blocks is loaded into the buffer unit 120, and the block having the lowest erase count is selected as a block to replace the block having the high erase count, and the physical position is changed. . At this time, since the buffer unit 120 should load the erase count of all blocks, the memory size had to be large.

However, according to an exemplary embodiment of the present invention, the memory controller 140 does not load the erase count information of all blocks into the buffer unit 120 at the time of the wear leveling, but samples several blocks set to match the search condition. (sampling) to perform wear leveling. In addition, the memory controller 140 according to an embodiment of the present invention adds the number of times of deletion each time a block is deleted. Thus, if the number of blocks deleted is greater than a predetermined value, wear leveling is performed. At this time, the cumulative number of failures is used as a criterion for the block search, and the difference between the number of deleted blocks and the average number of deleted blocks is different. By using as a criterion of the number of searches, the search time and the search conditions can be controlled to be flexible. In other words, according to an embodiment of the present invention, while using minimal information on wear leveling, it is possible to shorten the search time and increase the search probability of the replacement target block by setting the search criteria to be double. A detailed description thereof will be given later.

The memory area 150 is controlled by the memory controller 140 to perform write, delete, and read operations of data. The memory region 150 may be a NAND flash memory. According to an embodiment of the present invention, a cell of a NAND flash memory may be a single level cell (SLC) or a multi level cell (MLC). The memory area 150 may be provided with a plurality of chips including a plurality of blocks including a plurality of pages. On the other hand, the above-mentioned mapping information and the number of deletion information are stored in the memory area 150. This will be referred to separately as 'mapping page' here. That is, the physical definition of the mapping page refers to a page which is a processing unit or storage unit of the NAND flash memory. The mapping page stores the number of deletions together with mapping information between logical and physical addresses of one block information. define. To avoid confusing the semantics, you can name the mapping storage area instead of the mapping page.

3 is a flowchart illustrating a control method of the semiconductor storage system according to FIG. 1. Herein, it will be exemplified as determining whether to wear leveling at every deletion. This is merely an example, and of course, it may not be determined whether to perform wear leveling at each deletion.

1 to 3, first, data of an arbitrary block is deleted.

Each time the block data is deleted, the number of deletions is added and checked (S10).

It is determined whether the checked number of deletions is greater than a predetermined value (Sger).

Here, the predetermined value may be calculated by the following equation.

Predetermined value = (mean value of erase count + error range)

For example, if the average value of the number of deletions is 100 and the error range is 40, the predetermined value will be 140.

The above illustrated numbers are only numerical examples to aid understanding, but are not limited thereto.

Thus, if the total number of erased erased blocks is greater than 140 (Y), for example, the memory controller 140 controls the start of performing wear leveling. First, the first criterion of the target block search is set using an accumulated fail count (S30).

The cumulative number of failures is a kind of flag signal indicating success in finding a target block to be replaced with a worn block.

The initial value of the cumulative failure count is set to 0, and if the block to be replaced, that is, the target block, is not found through the following sequence, the cumulative failure count will be increased. This is to alleviate the criterion for erasing the target block whenever the cumulative failure count increases. In other words, as the cumulative number of failures increases, the search criteria of blocks to be replaced are further relaxed. Specifically, initially, the reference of the block having the low number of deletions is set to a value obtained by subtracting the error range from the average value of the number of deletions. For example, if the average value of the number of deletions is 100 and the error range is 40, the reference for the block with the lowest number of deletions initially set will be 60. However, if the search fails, it is determined that 60, which is a criterion of the block having a low number of deletions, is a high criterion, and thus, blocks having a higher number of deletions are also set as blocks to be replaced. Thus, whenever the cumulative number of failures increases, for example, the number of deletion criteria can be increased by, for example, 5, so that the criteria for the number of deletion blocks can be gradually relaxed to 45, 50, 55 ... . However, it is desirable to prevent the cumulative failure count from accumulating indefinitely and to set the cumulative failure allowance count so that a block having a minimum average erase count or less is selected as the target block. In conclusion, the search first condition of the target block is the number of deletions of the replacement target blocks that are the selection criteria of the target block.

This will be described in detail later with reference to FIG. 4.

In operation S40, the number of times of searching for the target block is set as the second criterion for searching for the target block.

The condition for the number of searches of the target block means the number of times of access to the stored mapping page of the memory area. In each access, a block stored in one mapping page of the memory area may be searched. Therefore, if the target block is not found within one time, another mapping page is accessed to search for possible target blocks. Accordingly, the search target of the target block increases each time the number of accesses increases. The number of times of access is not set arbitrarily or uniformly, but is changed flexibly according to the number of erased blocks. That is, according to the degree to which the number of erased blocks is higher than, for example, the sum of the average number of erases and the error range, that is, in the case of an urgent block replacing the worn block, the number of accesses of the mapping page is increased. Fluidly controlled. To do this, it is important to know how the number of erased blocks differs from the average number of erased blocks. In addition, the number of accesses may be differently applied to the performance sensitivity of the wear leveling according to the importance of the system to be applied.

It will not be difficult for those skilled in the art to understand that the performance sensitivity of the wear leveling will vary depending on the configuration of the semiconductor storage system to which it is applied, or depending on the respective application. However, FIG. 5 exemplarily shows the sensitivity and the number of deletions of blocks, and a detailed description thereof will be described later.

In this way, it is determined whether the number of accesses satisfies the set second search condition (S50).

That is, if the predetermined value of the number of accesses according to the calculation formula is not reached (N), the loop is performed until the target block is found (S60). If the number of accesses reaches a predetermined value (Y), it is determined whether the target block is found within the access count threshold (S70).

Alternatively, if a target block that satisfies the set number of erase times or less is found during the iteration loop (Y), the cumulative failure count is decreased and updated (S80). Since the search satisfies the set first and second conditions, the accumulated number of failures is reduced by a predetermined amount so as to secure a margin from the accumulated failure number to the accumulated failure allowance.

If the target block is not found within the access count threshold value (N), since the search condition needs to be further relaxed, the cumulative failure count is increased and updated (S90). That is, this situation is a case where a target block to be replaced is not found despite the currently set first and second search conditions. In such a case, the cumulative number of failures is updated to update the next search condition, and then the success rate of wear leveling is increased when the next block is deleted.

As described above, according to an embodiment of the present invention, in order to efficiently retrieve each of the number of deletion times of the distributed blocks, it can be seen that the conditions for the reference of the number of deletions and the conditions for the reference of the number of searches are respectively set. . Unlike in the related art, when a replacement time of a worn block comes, instead of looking for a block having the lowest number of deletions, wear leveling of the worn block is performed at the expense of the first block to be replaced. The first block found here implies that the block found within a predetermined number of times when performing the wear leveling (or the next time the wear leveling is performed) satisfies the condition of the number of deletions to be replaced. Thus, it is possible to shorten the execution time of the wear leveling rather than performing the wear leveling on the entire block.

4 is a graph showing a correlation between the number of deletions of a target block and the number of cumulative failures according to an embodiment of the present invention.

Referring to FIG. 4, the X axis represents the cumulative failure count, and the Y axis represents the deletion count of the target block to be replaced.

Here, the average erase count is set to 100, the error range is set to 40, and the threshold of the cumulative failure allowance is set to 5 or less.

Ⓐ of this graph can be implemented by equation (2).

Search condition of target block 1 = (average number of deletions-error range) + error range / (maximum cumulative number of failures allowed-cumulative failures)

However, such a formula can be applied when the cumulative failure allowance number is 5 or less, which is a threshold value. If the cumulative failure allowance number exceeds a threshold value, a first condition of a target block implemented as a straight line with a gentle slope may be set as shown in ⓑ in FIG. 4.

First condition of target block = (average number of deletions + upper limit of threshold error)-cumulative failures

That is, FIG. 4 means that the target block is actively searched for in the interval of 5 or less, which is the threshold of the cumulative failure allowance. When the cumulative failure allowance exceeds the threshold, the number of deletions of the target block is deleted. Since a situation in which the sum of the average number of times and the threshold is already exceeded is introduced, it implies that the meaning of lowering the search condition of the target block is not significant.

Therefore, in one embodiment of the present invention, the threshold of the cumulative failure tolerance is set to 5, and management is performed so as not to allow a situation exceeding the threshold.

5 is a table showing a correlation between the sensitivity and the number of deletion of blocks according to an embodiment of the present invention.

Referring to FIG. 5, it can be seen that, based on the number of deletions of the worn block, as the number of deletions increases, a predetermined search value according to the sensitivity is increased. In addition, in terms of the sensitivity, it can be seen that as the intensity of the sensitivity increases, a predetermined search value for the same number of times the erased block is increased.

Search for target block 2nd condition = (Basic Mapping Page Access Count -1) + (Number of Deleted Blocks-(Average Deletes + Threshold)) * Sensitivity

Here, the default mapping page access count is set to 7, the average deletion count is set to 100, and the threshold value is set to 40.

Therefore, as the erase count of the wear block is higher than the sum of the average erase count and the threshold value, the search for the target block corresponding to the wear block should be enhanced. Accordingly, the second condition of the search for the target block may be set by a calculation formula such as Equation 4 so that the number of mapping accesses is increased.

On the other hand, since a higher performance system requires higher sensitivity, Equation 4 can be implemented as a function of sensitivity.

FIG. 6 is a graph illustrating a correlation between the number of accesses versus the sensitivity according to FIG. 5.

Referring to FIG. 6, the X axis represents the number of erased blocks, and the Y axis represents the number of accesses.

As described above, the number of accesses is calculated by Equation 4, and when the sensitivity of FIG. 5 is applied, it can be seen that the slope of the graph is sharply increased according to the intensity of the sensitivity. That is, 1 to 5 of FIG. 6 correspond to the strengths 1 to 5 of the sensitivity described with reference to FIG. 5 and show that the number of accesses compared to the number of deletions varies according to the intensity of the sensitivity.

For example, based on a condition of 150 times the number of deletions, it can be seen that the number of accesses is distributed from 18 to 58 according to the intensity of sensitivity. The more sensitive the system, the stronger the search for the target block even if the number of accesses is increased.

As described above, since the deletion count information of all blocks cannot be loaded and the entire comparison cannot be performed during wear leveling, a search condition is appropriately set so that the target block can be efficiently searched for.

Here, instead of finding the target block having the lowest value, the block having the numerical value that is eligible for replacement in the shortest time is to be found. In other words, instead of the lowest target block, the first block that is qualified for replacement is sacrificed by the wear leveling of the worn block. To this end, the number of deletions of the target block, which is the first condition of the target block search, may be varied and controlled to improve the search success rate, and the number of target blocks to be searched may be increased according to the urgent need for replacing the worn block. Can also be. Thus, according to one embodiment of the present invention, it is not necessary to add the size of the buffer unit for temporary storage of the mapping information and the number of deletions, and it is possible to keep the size smaller than the conventional one.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a block diagram of a semiconductor storage system according to an embodiment of the present invention;

2 is a block diagram conceptually illustrating an address mapping according to FIG. 1;

3 is a flowchart illustrating a control method of the semiconductor storage system according to FIG. 1;

4 is a graph illustrating a correlation between the number of deletions of a target block and a cumulative failure number according to FIG. 3;

FIG. 5 is a table summarizing the relationship between the sensitivity according to FIG. 3 and the number of erased blocks; FIG. And

FIG. 6 is a graph illustrating that the erase count and access count of the worn block according to FIG. 5 are changed according to sensitivity.

<Explanation of symbols for the main parts of the drawings>

110: host interface 120: buffer unit

130: MCU 140: memory controller

150: memory area

Claims (21)

A buffer unit sequentially loading a plurality of mapping pages in which mapping information and a number of deletions are stored; And Sampling mapping pages by setting the number of deletion of the target block and the number of the mapping pages to be searched for the target block so as to find a target block to be replaced with a worn block. And a memory controller that performs wear-leveling. The method of claim 1, The memory controller determines whether to perform wear leveling every time data is deleted. 3. The method of claim 2, The memory controller may vary the number of deletions of the target block every time the wear leveling is performed. The method of claim 3, And when the memory controller fails to find the target block when performing the wear leveling, the memory controller increases the erase count of the target block when performing the next wear leveling. The method of claim 1, Further comprising a memory area including a plurality of memory blocks, The plurality of memory blocks includes the plurality of mapping pages, The memory controller may control the number of mapping pages to be searched differently while varying the number of times the memory area is accessed each time the wear leveling is performed. The method of claim 5, And the memory controller increases the number of times of access to the memory area as the erase count of the worn block is higher than a predetermined value. The method of claim 6, The memory controller increases the number of mapping pages loaded in the buffer unit as the number of times of accessing the memory area increases. The method of claim 7, wherein The mapping page loaded in the buffer unit is sequentially loaded, not simultaneously loaded. delete A memory area including a plurality of memory blocks, the mapping page storing mapping information and erase counts in each of the memory blocks; And In the wear leveling, by setting a criterion of the number of deletion targets for the block to be replaced of the worn out of the memory block and the reference of the number of search targets for the block to be replaced using the information of the weared block, And a memory controller that finds and replaces the first block to be replaced with the worn block as a target block. The method of claim 10, The memory controller is configured to control and vary the reference number of times of erasing the target block to improve a search success rate of the target block. The method of claim 11, And if the memory controller fails to find the target block when performing the wear leveling, the memory controller increases the number of deletions of the target block when performing the next wear leveling. The method of claim 10, The memory controller may vary the number of objects to be searched according to an urgent need for replacing the worn block. The method of claim 13, The memory controller increases the number of searches for accessing the memory area by increasing the number of the target blocks to be searched as the number of times of deleting the worn block is higher than a predetermined value. Setting a first criterion for determining the number of deletions of the target block to be replaced corresponding to the worn block during wear leveling; Setting a second reference of the target block search according to the number of deletions of the worn block; Finding the target block by the first and second criteria; And And if the target block is not found, changing the first criterion to update the target block, thereby affecting a next target block search condition. The method of claim 15, The setting of the first reference may include: And setting a number of deletions of a predetermined value to be selected as the target block. The method of claim 15, The setting of the second criterion may include: And controlling the number of accesses to the memory area by increasing the number of blocks to be searched to the target block as the number of erased blocks is increased. The method of claim 17, And repeatedly searching for the target block that satisfies the number of deletions of the first criterion or less during the number of accesses as the second criterion. The method of claim 15, Setting a cumulative number of failures indicating whether the target block has failed to search when entering the wear leveling; The setting of the first reference may include setting the number of deletions of the target block using the cumulative number of failures. The method of claim 19, And if the target block is not found, increasing the cumulative number of failures to increase the reference number of deletion of the target block. The method of claim 19, And if the target block is found, reducing the cumulative number of failures and lowering the reference for the number of deletions of the target block.

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