KR101096715B1 - Liquid Crystal Display Device - Google Patents

Abstract

According to an exemplary embodiment of the present invention, a spacer added to a sealant is positioned in a region where the gate link line and the data link line do not overlap, whereby a short defect is generated between the gate link line and the data link line when the substrate is opposed to each other. The present invention relates to a liquid crystal display device comprising: a first substrate having an active region and a pad portion region; A thin film transistor formed in the active area and defining a plurality of gate lines and data lines defining a pixel area, and a region in which the gate lines and data lines cross each other; A gate link line and a data link line formed in the pad portion region and respectively extending from the gate line and the data line; A gate pad and a data pad respectively connected to the gate link line and the data link line and disposed at one edge of the first substrate in the pad area; A second substrate facing the first substrate; A black matrix, a color filter layer, and a common electrode formed on the second substrate; A sealant for bonding the first and second substrates together; And a spacer formed inside the sealant to maintain cell gaps of the first and second substrates, wherein the gate link line and the data link line cross each other at one edge of the first substrate. The spacer is limited to an area where the gate link line and the data link line formed in the pad portion region do not overlap.

Spacer, Sealant, Short Fault, Gate Link Line, Data Link Line, Vcom Wiring

Description

Liquid Crystal Display Device

1 is a cross-sectional view of a liquid crystal display device according to the prior art.

2 is a plan view of a liquid crystal display device according to the prior art.

3 is a cross-sectional view of the liquid crystal display device along the line II ′ of FIG. 2.

4 is a plan view of a liquid crystal display device according to the present invention;

FIG. 5 is a cross-sectional view of the liquid crystal display device along the II-II 'line in FIG. 4; FIG.

6 is an enlarged plan view of a sealant forming region according to the present invention;

* Explanation of symbols on the main parts of the drawings

111 TFT array substrate 113 gate insulating film

116: protective film 117: pixel electrode

121: color filter array substrate 128: black matrix

123: color filter layer 126: sealant

130: first column space

g1, g2, g3, .., gn-1, gn: gate wiring

d1, d2, d3, .., dm-1, dm: data wiring

L _g1 , L _g2 , L _g3 , .., L _gn-1 , L _gn : Gate link line

L _d1 , L _d2 , L _d3 , .., L _dm-1 , L _dm : Data link line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device (LCD), and more particularly, to a liquid crystal display device for preventing unevenness occurring during image display of a liquid crystal display device.

BACKGROUND ART Liquid crystal display devices, which have recently been spotlighted as flat panel display devices, have been actively researched due to their high contrast ratio, suitable for gradation display or moving picture display, and low power consumption.

In particular, it can be manufactured with a thin thickness so that it can be used as an ultra-thin display device such as a wall-mounted TV in the future, and is light in weight and consumes significantly less power than a CRT CRT. It is being used as a next generation display device. In addition, since it is manufactured as a small panel and used as a mobile phone display, its use is various.

Generally, as shown in FIG. 1, the liquid crystal display device is formed at the intersection of the gate wiring (not shown) and the data wiring Dm, which are insulated from each other by the gate insulating film 13, and the two wirings. A TFT array substrate 11 having a thin film transistor TFT, a pixel electrode 17 penetrating through the passivation layer 16 and connected to the thin film transistor TFT, a black matrix 28 and a color filter layer 23. ) And a color filter array substrate 21 having a common electrode 25 formed thereon, and a liquid crystal layer 29 interposed between the two substrates, and applying a voltage to the electrodes to form liquid crystal molecules of the liquid crystal layer 29. By rearranging them, the amount of light transmitted is controlled to display an image.

In this case, the TFT array substrate 11 may be driven by an active region including a plurality of pixel regions formed at intersections of gate wirings and data wirings, and from external drive integrated circuits to gate wirings and data wirings of the active region. It is divided into a pad portion region of the outer portion of the active region including a gate pad and a data pad for supplying various signals required.

A gate link line extending from the gate line to the gate pad and a data link line extending from the data line to the data pad are further formed in the pad area.

In addition, a sealant 26 is provided in the pad region to completely adhere the TFT array substrate and the color filter array substrate.

Here, if the gap between the two substrates is not constant, the transmittance of the light passing through the portion is changed and the brightness is uneven, so that the spacer 31 is inserted between the two substrates to keep the substrate gap constant. A spacer 31 is added to the sealant to keep the substrate gap in the region constant.

The spacers used in this case include ball spacers (31 in FIG. 1) scattered on the substrate and column spacers attached to the substrate. As the substrate becomes larger in area, the ball spacers are difficult to maintain the cell gap uniformly. use.

Hereinafter, a liquid crystal display device according to the prior art will be described in more detail.

2 is a plan view of a liquid crystal display device according to the prior art, and FIG. 3 is a cross-sectional view of the liquid crystal display device along the line II ′ of FIG. 2.

As described above, the TFT array substrate 11 includes a plurality of gate wirings G1, G2, G3, .., Gn-1, Gn and data wirings perpendicularly intersecting with each other, as shown in FIG. A printed circuit board which is an external driving circuit by an active region 53 in which a pixel region is defined by D1, D2, D3, .., Dm-1, Dm, and a gate pad 22 and a data pad 24 ( A pad portion region 54 connected to the pad portion (not shown).

Specifically, the plurality of gate lines G1, G2, G3, .., Gn-1, Gn and the data lines D1, D2, D3, .., Dm-1, Dm cross the active region 53. A thin film transistor (TFT) is formed at the intersection of the gate line and the data line as a switching element, and the thin film transistor is connected to the pixel electrode 17 with a protective film interposed therebetween.

In the pad region, a gate pad 22 for applying a gate driving signal to each of the gate lines G1, G2, G3, .., Gn-1, Gn, and a data signal are applied to each of the data lines D1. A plurality of data pads 24 for applying to, D2, D3, .., Dm-1, Dm are formed to interface electrical signals with an external driving circuit.

In this case, the gate pad 22 may include a plurality of gate link lines L _G1 , LG _G2 , LG _G3 , .. extending from a plurality of gate lines G1, G2, G3,..., Gn-1, Gn. The data pads 24 are formed at ends of, L _Gn-1 , L _Gn , and the data pads 24 extend from a plurality of data wires D1, D2, D3, .., Dm-1, Dm. _D1 , L _D2 , L _D3 , .., L _Dm-1 , L _Dm ).

Recently, the gate pad 22 and the data pad 24 are collectively arranged at one edge of the substrate 11 to make the substrate size compact.

When the gate signal is to be sent to only one side, the signal is applied to both the left and right sides in preparation for the size of the substrate. That is, the odd-numbered gate lines G1, G3, .., Gn-1 extend from the right side to be connected to the gate pad 22, and the even-numbered gate lines G2, .., Gn-2, Gn are from the left side. Extends to connect to the gate pad 22.

At this time, the sealant 26 is formed in the pad region 54 to form a cell gap and to prevent the leakage of liquid crystal, and is printed seamlessly using a screen mask in which a predetermined pattern is formed. do.

The sealant 26 is added with glass fibers such as micro pearl (manufactured by Sekisui Fine Chemical Ltd.), plastic balls or silica balls, and pads to the thickness of the glass fibers. Maintain the cell gap of the subregion.

However, when the data pad 24 and the gate pad 22 are collectively arranged at one edge as described above, as shown in FIG. 3, the gate link line _LGN and the data link line L _{Dm are illustrated.} ) Overlaps with each other, where the sealant 26 is formed.

In this case, the sealant 26 includes a glass fiber 31 having a diameter of 40 μm, and the glass fiber in the pressing process to bond the TFT array substrate 11 and the color filter array substrate 21 to each other. 31 is pressed, and a defect occurs in which the gate link line _LG and the data link line L _Dm overlapping each other are shorted.

At this time, since the color filter layer of the color filter array substrate 21 is usually formed only in the active region, the sealant 26 comes into contact with the black matrix 28.

The present invention has been made to solve the above problems, and the spacer added to the sealant is located in a region where the gate link line and the data link line do not overlap, so that the substrate is bonded between the gate link line and the data link line at the time of opposing bonding. It is an object of the present invention to provide a liquid crystal display device for preventing short defects from occurring.

According to an aspect of the present invention, a liquid crystal display device includes a first substrate in which a thin film transistor is formed in a pixel region defined by vertical crossing of a plurality of gate lines and data lines, and a gate extending from the gate lines and data lines, respectively. A link line and a data link line, a second substrate facing the first substrate and having a color filter layer formed therein; a sealant for opposing and bonding the first and second substrates; and a sealant added inside the sealant. And a spacer disposed in a region where the gate link line and the data link line do not overlap while maintaining the cell gap of the second substrate.

That is, a sealant is formed in the pad region of the substrate to oppose the two substrates. In the case where a spacer is further formed in the sealant to maintain a constant cell gap of the front panel, the gate link line and the data link are formed. The space may be arranged in an area where lines do not overlap.

Accordingly, short defects can be prevented from occurring between the gate link line and the data link line by the spacers inside the sealant.

At this time, the space is a column space, ball spacers, such as glass fibers are generally manufactured in a size of 40㎛, it is difficult to produce less than that size to form a large area liquid crystal panel with a low cell gap In order to achieve this, a column spacer may be used. Since the column spacers are formed using photoetch technology, the patterns can be precisely formed.

In particular, the present invention is particularly useful for liquid crystal display devices in which the gate link lines and the data link lines overlap. As an embodiment, the data pads and the gate pads are formed at one side of the substrate at the same time for compactness of the substrate size, and both sides of the gate wirings are formed. The liquid crystal display element which applies a signal is mentioned.

Hereinafter, a liquid crystal display device according to an embodiment of the present invention will be described with reference to the accompanying drawings.

4 is a plan view of the liquid crystal display device according to the present invention, FIG. 5 is a sectional view of the liquid crystal display device along the line II-II 'of FIG. 4, and FIG. 6 is an enlarged plan view of the sealant formation region according to the present invention.

As shown in FIGS. 4 and 5, the liquid crystal display device according to the present invention can change the arrangement direction of the color filter array substrate 121 and the liquid crystal molecules in which the color filter layer 123 for color realization is formed. The active region 153 on which the thin film transistor TFT is formed, the gate pad 122 and the data pad 124 are collectively disposed at one edge of the substrate to form gate link lines L _g1 , L _g2 , L _g3 , .., TFT array divided into pad portion region 154 partially overlapping L _gn-1 , L _gn ) and data link lines L _d1 , L _d2 , L _d3 , .., L _dm-1 , L _dm A sealing agent formed on the substrate 111, a liquid crystal layer (not shown) formed between the two substrates, and an edge of the TFT array substrate 111 to bond the two substrates together and prevent liquid crystals from flowing out; 126 and the gate link lines L _g1 , L _g2 , and L _g3 provided at the region where the sealant 126 is formed. First column spacer formed only in a region where, .., L _gn-1 , L _gn ) and data link lines L _d1 , L _d2 , L _d3 , .., L _dm-1 , L _dm do not overlap It is characterized by consisting of 130.

In this case, the first column spacer 130 may have a width of 20 to 30 μm and a height of 4 to 5 μm. As shown in FIG. 6, the gate link line L _gn and the data link line ( L _dm ) can be formed as long as the region does not overlap.

The first column spacer 130 is formed to maintain a constant cell gap between the two substrates in the pad portion region 154 and simultaneously with the second column spacers (not shown) distributed in the active region 153. Can be formed. At this time, since the first and second column spacers have the same height, the color filter layer 123 extends to the pad region 154 to maintain a constant cell gap of the entire panel. If the color filter layer 123 is not formed in the pad portion region 154, the substrate gap between the active region 153 and the pad portion region 154 differs by the step of the color filter layer 123.

And a gate wiring layer including the gate link lines L _g1 , L _g2 , L _g3 , .., L _gn-1 , L _gn and the data link lines L _d1 , L _d2 , L _d3 , .., L _A gate insulating film 113 is interposed between the data wiring layers including _dm-1 and L _dm to insulate the two patterns, and the data link lines L _d1 , L _d2 , L _d3 , .., L _dm-1 , L _A protective film 116 is formed on the front surface including _dm ) to protect the pattern.

Specifically, in the active region 153 of the TFT array substrate 111, as shown in FIG. 4, a plurality of gate wirings g1, g2, g3, .., gn-1, gn and data wirings ( A plurality of pixel regions are defined by vertically crossing d1, d2, d3, .., dm-1, dm, and a thin film transistor (TFT) as a switching element is formed at the intersection of the gate wiring and the data wiring. The pixel electrode 117 is formed in each pixel region.

The pad portion region 154 extends from the gate lines g1, g2, g3, .., gn-1, gn and the data lines d1, d2, d3, .. dm-1, dm, respectively. A plurality of gate link lines L _g1 , L _g2 , L _g3 , .., L _gn-1 , g _n ) and data link lines L _d1 , L _d2 , L _d3 , .., L _dm-1 , L _dm ), and gate pads 122 and data pads 124 connected to ends of the gate link line and the data link line, respectively.

In this case, in order to minimize the size of the pad portion region 154, the gate pad 122 and the data pad 124 are collectively disposed under the TFT array substrate 111, and the gate wiring connected to the gate pad 122 is disposed. Each of the odd and even numbers extends from the left and right sides, respectively. That is, when the odd-numbered gate lines g1, g3,... Gn-1 extend from the left side of the TFT array substrate 111 to be connected to the gate pad, the even-numbered gate lines g2, .. gn extends from the right side of the TFT array substrate 111 and is connected to the gate pad 122. Of course, the opposite is also possible.

In this case, either of the odd-numbered gate lines or the even-numbered gate lines crosses the data link line to be connected to the gate pad, at which time the gate link line and the data link line overlap.

Meanwhile, the sealant 126 that bonds the two substrates is formed to be printed in the pad area without gap, and the gate link lines L _g1 and L are formed at one edge where the gate pad 122 and the data pad 124 are provided. _g2 , L _g3 , .., L _gn-1 , L _gn ) and data link lines L _d1 , L _d2 , L _d3 , .., L _dm-1 , L _dm . In this case, the gate pad 122 and the data pad 124 are exposed to the outside and connected to an external driving circuit.

Accordingly, the first column spacer 130 may be formed in an area where the gate link line L _gn and the data link line L _dm overlap, and the present invention links the first column spacer 130. The gate link line L _gn and the data link line L _dm may not be shorted by the first column spacer 130 by being disposed in the sealant forming part where the lines do not overlap.

For reference, the manufacturing method of the liquid crystal display device is as follows.

First, a low-resistance metal material such as aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), chromium (Cr), etc. is deposited and patterned on the TFT array substrate 111 by gate wiring (g1, g2). gate wiring layers such as (g3, .., gn-1, gn), gate electrodes, gate link lines (L _g1 , L _g2 , L _g3 , .., L _gn-1 , L _gn ), and gate pads 122 And a gate insulating film 113 is formed thereon.

Next, a low resistance metal is deposited on the gate insulating layer 113 and then patterned to form data lines d1, d2, d3, .., dm-1, dm, source / drain electrodes, and data link lines L _d1,. A data wiring layer such as L _d2 , L _d3 , .., L _dm-1 , L _dm ) and data pad 124 is formed, and a protective film 116 is formed thereon, and ITO (ITO) is formed on the protective film 116. A transparent conductive material such as Indium Tin Oxide (IZO) or Indium Zinc Oxide (IZO) is deposited and then patterned to form a pixel electrode 117 connected to the TFT.

Subsequently, a black matrix 128 is formed on the color filter array substrate 121 to block light leakage, and a red, green, and blue color is formed using dyes or pigments thereon. After the color filter layer 123 is formed, the common electrode 125 is formed on the color filter layer 123.

Next, the first column space 130 and the second column spacer (not shown) are coated or deposited using a photolithography technique after coating or depositing a material for a space on the color filter layer 123 on which the common electrode 125 is formed. At the same time.

As such, the column spacer can be easily formed on the color filter array substrate 121. This is because a large number of fine patterns are formed on the TFT array substrate 111, which may cause a defect in spacer patterning.

The material for space uses a polymer material such as photo acryl resin having photosensitivity, and is an example of a polymer material having no photosensitivity, such as an organic insulating material such as BCB (Benzocyclobutene) or silicon nitride (SiNx), The column spacer may be formed using a polymer material such as an inorganic insulating material such as silicon oxide (SiOx).

In this case, the first column spacer 130 is formed to be positioned at the portion where the _sealant 126 is printed, but is formed at a portion where the gate link line L _gn and the data link line L _dm overlap each other. The second column spacers are evenly formed in the active region excluding the openings.

Subsequently, a seal material 126 that serves as an adhesive on the edge of the TFT array substrate 111 is printed to bond the two substrates together. The sealant may be a thermosetting sealant such as an epoxy resin that is cured by applying heat, or a UV curable sealant such as an epoxy acrylate resin or a urethane acrylate resin that is cured by applying ultraviolet rays.                     

Thereafter, high pressure is applied to the two bonded substrates as described above, thereby curing the sealant while keeping the gap between the substrates constant, thereby completely bonding the two substrates. Here, since the first column spacer 130 is not formed at the portion where the gate link line L _gn and the data link line L _dm overlap each other, the first column spacer 130 is pressed by the first column spacer 130 even when the substrate is pressed. There is no fear of the link line shorting.

Next, the two bonded substrates are cut to a desired product size by performing a scribe process and a break process.

A liquid crystal panel having a required size is obtained by injecting and encapsulating a liquid crystal between the two substrates cut as described above through the liquid crystal inlet.

That is, the bonded liquid crystal cell is introduced into the vacuum chamber to immerse the liquid crystal inlet in the liquid crystal tray, vacuum degassing the inside of the cell, and supply the inert gas to make the vacuum chamber at atmospheric pressure. At this time, the liquid crystal is injected between the substrate due to the difference in the atmospheric pressure between the liquid crystal cell and the vacuum chamber. Nitrogen (N ₂ ) gas is used as the inert gas, and the liquid crystal injection rate is determined by the gas supply rate.

In recent years, as the liquid crystal display device is enlarged in size, the liquid crystal dropping method does not depend on the above-mentioned liquid crystal injection method, but also the liquid crystal dropping method of forming a liquid crystal layer by dropping and spreading the liquid crystal evenly on the inner surface of the substrate before the substrate opposing bonding.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

That is, in the above embodiment, the present invention is limited to the overlapping portion of the gate link line and the data link line, but the present invention can be applied to a liquid crystal display device in which the gate link line and the data link line do not overlap in the pad portion.

Specifically, a Vcom wiring parallel to the gate wiring may be further formed, and the Vcom wiring may overlap the gate link line or the data link line at the lower end of the sealant. As described above, in the case where the wirings through which different signals flow at the lower end of the sealant are overlapped, the spacers may be arranged in an area where the two wirings do not overlap.

The liquid crystal display of the present invention as described above has the following effects.

That is, a spacer is added to the sealant forming part to maintain a constant cell gap of the front panel, and the spacer is disposed in an area where the gate link line and the data link line do not overlap, so that the spacer is pressed by the spacer when the substrate is bonded. Short defects can be prevented from occurring between the gate link line and the data link line.

Therefore, the defective rate of a liquid crystal display element becomes low and productivity improves.

Claims (8)

A first substrate having an active region and a pad portion region; A thin film transistor formed in the active area and defining a plurality of gate lines and data lines defining a pixel area, and a region in which the gate lines and data lines cross each other; A gate link line and a data link line formed in the pad portion region and respectively extending from the gate line and the data line; A gate pad and a data pad respectively connected to the gate link line and the data link line and disposed at one edge of the first substrate in the pad area; A second substrate facing the first substrate; A black matrix, a color filter layer, and a common electrode formed on the second substrate; A sealant for bonding the first and second substrates together; And A spacer formed inside the sealant to maintain a cell gap of the first and second substrates; The gate link line and the data link line cross each other at one edge of the first substrate, And the spacer is limited to a region where the gate link line and the data link line formed in the pad portion region do not overlap. The method of claim 1, And a gate pad formed at an end of the gate link line and a data pad formed at an end of the data link line are collectively disposed at one edge of the first substrate. The method of claim 2, Of the gate wirings, When odd-numbered gate lines extend from the left side of the first substrate to be connected to the gate pad, And even-numbered gate lines extend from a right side of the first substrate and connected to the gate pad. The method of claim 1, And the spacer is a column spacer. The method of claim 4, wherein The color filter layer extends to the portion where the sealant is formed, The column spacer is formed on the color filter layer. The method of claim 4, wherein And the column spacer is formed at the same time as the column spacer of the active region. The method of claim 1, The Vcom wiring is further provided on the first substrate. The method of claim 7, wherein The spacer inside the sealant is formed in a region where the Vcom wiring does not overlap the gate link line or the data link line.

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