KR101089801B1 - 반도체 패키지 제조용 금형 장치 - Google Patents
반도체 패키지 제조용 금형 장치 Download PDFInfo
- Publication number
- KR101089801B1 KR101089801B1 KR1020090021098A KR20090021098A KR101089801B1 KR 101089801 B1 KR101089801 B1 KR 101089801B1 KR 1020090021098 A KR1020090021098 A KR 1020090021098A KR 20090021098 A KR20090021098 A KR 20090021098A KR 101089801 B1 KR101089801 B1 KR 101089801B1
- Authority
- KR
- South Korea
- Prior art keywords
- vacuum
- mold
- package
- vacuum holes
- cavity block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 238000000465 moulding Methods 0.000 title claims description 34
- 239000011265 semifinished product Substances 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 19
- 238000003825 pressing Methods 0.000 claims description 3
- 229920006336 epoxy molding compound Polymers 0.000 description 17
- 238000004140 cleaning Methods 0.000 description 8
- 229920005989 resin Polymers 0.000 description 7
- 239000011347 resin Substances 0.000 description 7
- GLGNXYJARSMNGJ-VKTIVEEGSA-N (1s,2s,3r,4r)-3-[[5-chloro-2-[(1-ethyl-6-methoxy-2-oxo-4,5-dihydro-3h-1-benzazepin-7-yl)amino]pyrimidin-4-yl]amino]bicyclo[2.2.1]hept-5-ene-2-carboxamide Chemical compound CCN1C(=O)CCCC2=C(OC)C(NC=3N=C(C(=CN=3)Cl)N[C@H]3[C@H]([C@@]4([H])C[C@@]3(C=C4)[H])C(N)=O)=CC=C21 GLGNXYJARSMNGJ-VKTIVEEGSA-N 0.000 description 5
- 229940125758 compound 15 Drugs 0.000 description 5
- 238000001179 sorption measurement Methods 0.000 description 3
- 238000001721 transfer moulding Methods 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 2
- 239000000356 contaminant Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000006260 foam Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- -1 that is Polymers 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Moulds For Moulding Plastics Or The Like (AREA)
Abstract
Description
Claims (8)
- 반도체 칩이 기판에 실장되어 와이어 본딩이 완료된 패키지 반제품을 고정시키도록 상기 패키지 반제품의 하면을 진공 흡착할 수 있는 복수의 진공홀이 관통 형성된 캐버티 블록을 구비한 하부 금형과,상기 하부 금형의 상방에 위치하되 상기 캐버티 블록에 대응하도록 하부에 오목한 캐버티가 형성된 상부 금형과,상기 복수의 진공홀 보다 더 작은 직경을 가지고, 복수의 진공홀에 진공 흡착력이 유지되도록 상기 복수의 진공홀에 삽입되는 복수의 핀; 및상기 복수의 진공홀과 연통되도록 상기 캐버티 블록의 내부에 형성된 진공라인;을 포함하며,상기 진공라인은,상기 복수의 진공홀 하부가 각각 연결되도록 상기 캐버티 블록의 내부에 형성된 연결홈; 및상기 연결홈으로부터 단차지게 확장되고, 상기 복수의 핀의 헤드의 높이와 동일하게 형성되어 상기 복수의 핀의 헤드가 안착되는 안착홈;을 포함하며,상기 복수의 핀의 헤드는,상기 복수의 진공홀의 진공 흡착력이 유지되도록 상기 복수의 진공홀 하부를 일부 개방하여 상기 복수의 진공홀 하부에 걸려 고정되는 것을 특징으로 하는 반도체 패키지 제조용 금형 장치.
- 삭제
- 삭제
- 삭제
- 제1항에 있어서,상기 복수의 핀의 헤드는 타원 형상인 것을 특징으로 하는 반도체 패키지 제조용 금형 장치.
- 제1항에 있어서,상기 복수의 진공홀은,패키지 반제품의 하면 외주 둘레부 및 내부를 각각 진공 흡착할 수 있도록 상기 캐버티 블록에 형성된 것을 특징으로 하는 반도체 패키지 제조용 금형 장치.
- 제1항에 있어서,상기 상부 금형이 상하로 승강 가능하게 설치되어 상기 상부 금형의 하면이 상기 하부 금형의 상면에 맞닿아 가압됨으로써 상기 패키지 반제품을 몰딩하는 것을 특징으로 하는 반도체 패키지 제조용 금형 장치.
- 제1항에 있어서,상기 하부 금형이 상하로 승강 가능하게 설치되어 상기 하부 금형의 상면이 상기 상부 금형의 하면에 맞닿아 가압됨으로써 상기 패키지 반제품을 몰딩하는 것을 특징으로 하는 반도체 패키지 제조용 금형 장치.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020090021098A KR101089801B1 (ko) | 2009-03-12 | 2009-03-12 | 반도체 패키지 제조용 금형 장치 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020090021098A KR101089801B1 (ko) | 2009-03-12 | 2009-03-12 | 반도체 패키지 제조용 금형 장치 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20100102836A KR20100102836A (ko) | 2010-09-27 |
KR101089801B1 true KR101089801B1 (ko) | 2011-12-08 |
Family
ID=43007701
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020090021098A Expired - Fee Related KR101089801B1 (ko) | 2009-03-12 | 2009-03-12 | 반도체 패키지 제조용 금형 장치 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR101089801B1 (ko) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101837967B1 (ko) | 2011-05-30 | 2018-03-14 | 삼성전자주식회사 | 진공 트레이 및 이를 사용한 발광소자 제조방법 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007273551A (ja) | 2006-03-30 | 2007-10-18 | Fujitsu Ltd | 樹脂封止用金型、樹脂封止装置及び半導体装置の製造方法 |
KR100833287B1 (ko) * | 2007-03-27 | 2008-05-28 | 세크론 주식회사 | 반도체소자 몰딩장치 |
-
2009
- 2009-03-12 KR KR1020090021098A patent/KR101089801B1/ko not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007273551A (ja) | 2006-03-30 | 2007-10-18 | Fujitsu Ltd | 樹脂封止用金型、樹脂封止装置及び半導体装置の製造方法 |
KR100833287B1 (ko) * | 2007-03-27 | 2008-05-28 | 세크론 주식회사 | 반도체소자 몰딩장치 |
Also Published As
Publication number | Publication date |
---|---|
KR20100102836A (ko) | 2010-09-27 |
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