KR101088450B1 - Semiconductor memory device - Google Patents

Abstract

In an embodiment, a semiconductor memory device may include first and second planes including a plurality of memory blocks; A block address comparison circuit for comparing whether an input block address is a bad block address and outputting a bad block signal according to the comparison result; Enable logic for outputting a first and second plane block enable signal in response to the bad block signal and a first and second plane selection signal; And an address decoder configured to output a block address signal in response to the first and second plane block enable signals.

Bad Blocks, Multiplanes, Block Enable

Description

Semiconductor memory device

The present invention relates to a semiconductor memory device.

A semiconductor memory device is a memory device that stores data and can be read when needed. Semiconductor memory devices are roughly divided into random access memory (RAM) and read only memory (ROM). Data stored in RAM is destroyed when power supply is interrupted. This type of memory is called volatile memory. On the other hand, data stored in the ROM is not destroyed even when the power supply is interrupted. This type of memory is called nonvolatile memory.

In the conventional semiconductor memory device, all blocks are arranged in one plane. This structure is called a single plane structure. Here, a block is a unit of erase operation. Each block includes a plurality of memory cells.

In flash memory with a single plane structure, only one block at a time for erasing, and pages within one block at a time for programming and reading. Command can be executed only for.

In order to improve the performance of a semiconductor memory device, a multi plane structure has been proposed. In a multiple plane structure semiconductor memory, blocks are distributedly arranged in a plurality of planes. An advantage of the multi-plane structure is that it can perform operations such as erase, write, or read on blocks or pages located in different planes at the same time. Blocks that are computed at the same time are arranged consecutively on adjacent planes.

The semiconductor memory device has been increasingly functionalized through higher integration, higher capacity, and increased chip size. However, with higher integration, higher capacity, and larger chip size, the circuit line width is reduced, the process is increased, and the complexity is increased. These conditions are a factor in reducing the yield of the semiconductor memory device.

In order to solve this problem, the semiconductor memory device includes a redundant memory cell (hereinafter, referred to as a redundant memory cell) for replacing a defective memory cell. It also includes means for switching the address of the defective cell to the address of the redundancy memory cell. In addition, a memory block that cannot be replaced with a redundant memory cell because the number of failed memory cells is too large is set as a bad block. Then, the access to the bad block is set to be blocked.

Therefore, the semiconductor memory device according to the embodiment of the present invention can immediately end the operation when a bad block is selected for each plane when a program or an erase operation is performed on the multi plane.

In a semiconductor memory device according to an embodiment of the present invention,

First and second planes comprising a plurality of memory blocks; A block address comparison circuit for comparing whether an input block address is a bad block address and outputting a bad block signal according to the comparison result; Enable logic for outputting a first and second plane block enable signal in response to the bad block signal and a first and second plane selection signal; And an address decoder configured to output a block address signal in response to the first and second plane block enable signals.

The enable logic includes an inverted signal of a power-on reset signal that is enabled when power starts to be input, an address storage signal that is enabled when an address is input, and an address storage completion signal that is enabled after address storage is completed. And a reset signal for outputting a reset signal according to a logical combination of the inverted signal of the multi-plane operation command, the command input signals enabled when the operation command is input, and a delayed reset signal for delaying the reset signal for a predetermined time. A signal output unit; A first plane that logically combines the delayed reset signal, the bad block signal output with respect to the block address of the first plane, and the first plane signal, and outputs the first plane block enable signal according to a result An enable portion; And a first logical combination of the delayed reset signal, the bad block signal output with respect to the block address of the second plane, and the second plane signal, and outputting the first plane block enable signal according to a result. It includes a plane enable portion.

The reset signal output unit may include an inverted signal of a power-on reset signal enabled when power is started to be input, an address storage signal enabled when an address is input, and an address storage completion signal enabled after address storage is completed. And a first logic circuit that OR-combines the inverted signal of the multi-plane operation command with the command input signals enabled when the operation command is input and outputs the result as the reset signal; And a delay unit delaying the reset signal for a predetermined time and outputting the delayed reset signal.

The first plane enable unit includes: a second logic circuit to AND-combine the delayed reset signal and a bad block signal for a block address of the first plane; A third logic circuit for AND combining the output of the second logic circuit and the first plane select signal; And a first flip-flop reset by the reset signal and outputting the first plane block enable signal in response to an output of the third logic circuit.

The second plane enable unit includes: a fourth logic circuit to AND-combine the delayed reset signal and a bad block signal for a block address of the second plane; A fifth logic circuit for AND combining the output of the fourth logic circuit and the second plane select signal; And a second flip-flop reset by the reset signal and outputting the second plane block enable signal in response to an output of the fifth logic circuit.

When the first or second plane block enable signal is disabled, the address decoder disables all block address signals in the corresponding plane.

As described above, the semiconductor memory device according to an embodiment of the present disclosure immediately stops performing an operation by checking whether a memory block selected for performing a program or an erase operation on a multi-plane is a bad block for each plane. To do it.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

1 illustrates a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 1, the semiconductor memory device 100 may include first and second planes 110 and 120, an X decoder 130, a peripheral circuit 140, an input / output logic 150, and a latch circuit 160. Circuit 170 and logic group 180.

The first and second planes 110 and 120 respectively include first to fourth memory blocks BK11 to BK14 and BK21 to BK24. The first and second planes 110 and 120 generally include a larger number of memory blocks, but only four memory blocks are shown for the purposes of the present description.

Each memory block includes cell strings (not shown) that are made up of memory cells for data storage.

In addition, one of the memory blocks BK14 and BK24 of the first and second planes 110 and 120 is designated and used as a cam cell block for storing option information. The memory block BK14 and BK24 store a bad block address, a repaired column address, and option information necessary for the semiconductor memory device 100 to operate.

The peripheral circuit 140 includes a page buffer (not shown), a Y decoder (not shown), a voltage providing circuit (not shown), etc. for storing data or reading the stored data.

The X decoder 130 includes block selection circuits 131 connected to corresponding memory blocks included in the first and second planes 110 and 120.

The block select circuit 131 enables the memory block connected to the block select circuit 141 in response to the address signal. When the memory block is enabled by the block selection switch 131, the lines SSL, WL0 to WL31 and DSL included in the memory block and the global lines GSSL, GWL0 to GWL31 and GDSL provided with an operating voltage are provided. This is connected.

The operating voltage provided to the global lines GSSL, GWL0 to GWL31 and GDSL is generated by a voltage providing circuit (not shown).

The latch circuit 160 includes a block address latch circuit 161 and a column address latch circuit 162.

The logic group 180 of the semiconductor memory device 100 loads the bad block address stored in the memory blocks BK14 and BK24, the repaired column address, and option information when power is started.

The bad block address is stored in the block address latch circuit 161, and the repaired column address is stored in the column address latch circuit 162. The option information is stored in registers (not shown) in logic group 180. The logic group 180 uses option information when controlling operations such as programming, reading, and erasing.

The comparison circuit 170 includes a block address comparison circuit 171 and a column address comparison circuit 172.

The block address comparison circuit 171 compares the block address input from the logic group 180 with the address of the bad block stored in the block address latch circuit 161. When the block address input from the logic group 180 is a bad block, the bad block signal BADBLK is output.

The bad block signal BADBLK is input to the logic group 180.

The column address comparison circuit 172 compares the column address input from the logic group 180 with the address of the repaired column stored in the column address latch circuit 162. If the column address input from the logic group 180 is a repaired column address, the repair signal REP is output.

The repair signal REP is input to the peripheral circuit 140.

The input / output logic 150 controls data input / output between the semiconductor memory device 100 and an external system in response to the input / output control signal.

The logic group 180 includes logics for outputting control signals for controlling the X decoder 130, the peripheral circuit 140, the input / output logic 150, the latch circuit 160, and the comparison circuit 170.

The block selection circuit 131 of the X decoder 130 may be implemented in various ways.

If the memory block connected to the block select circuit 131 is a bad block that is failed, the block select circuit 131 should not be enabled.

A general circuit configuration of the block selection circuit 131 includes a fuse in a circuit to which a block address is input, and when the fuse is connected to the bad block, cutting the fuse F prevents the bad block from being electrically enabled.

When the fuse is included in the block selection circuit 131, the area of the fuse itself is large. In addition, the fuse may be cut only during the manufacturing process of the semiconductor memory device 100.

Therefore, as shown in FIG. 1, the address of the bad block is stored in the blocks BK14 and BK24, and the fuse of the block selection circuit 131 is removed.

Since there is no fuse of the block selection circuit 131, the logic group 180 has a function of disabling and outputting a block address according to the bad block signal BADBLK.

FIG. 2 illustrates a block address comparison circuit of FIG. 1.

Referring to FIG. 2, the block address comparison circuit 171 includes a plurality of address comparison circuits connected in series, a first PMOS transistor P1, a first NMOS transistor N1, a NOR gate NOR, and a first inverter. (IN1).

Each of the address comparison circuits includes four NMOS transistors, and an address FAXBLC <20:32> and an inverted address FAXBLC_N <20:32> input from the block address latch circuit 161 are respectively input. The block address AXBLC <20:32> input from the logic block 180 and the inverted address AXBLC_N <20:32> are input.

The first PMOS transistor P1 is connected between the power supply voltage input terminal and the node SENSE. The output of the NOR gate NOR is input to the gate of the first PMOS transistor P1.

The comparison reset signal RST_CAM_COMP and the sensing signal SENSE are input to the NOR gate NOR. The NOR gate NOR outputs a low level signal if at least one of the two input signals has a high level signal. The high level signal is output only when both signals are low level.

The first inverter IN1 inverts and outputs a signal corresponding to the voltage level of the node SENSE.

The output of the first inverter IN1 is the bad block signal BADBLK.

When the operation command is input, the logic group 180 first applies a comparison reset signal RST_CAM_COMP to a high level. At this time, the sensing signal SENSE is at a low level.

Therefore, the NOR gate NOR outputs a low level signal. When the NOR gate NOR outputs a low level signal, the first PMOS transistor P1 is turned on.

Therefore, a power supply voltage is applied to the node SENSE. The node SENSE is inverted by the first inverter IN1. Therefore, the bad block confirmation signal BADBLK is output at a low level.

When the logic group 180 receives the operation command and the address, the bad block check enable signal BADBLKCHKEN is input to the high level. When the bad block check enable signal BADBLKCHKEN is at a high level, the first NMOS transistor N1 is turned on.

When the first NMOS transistor N1 is turned on, the addresses FAXBLC <20:32> and FAXBLC_N <20:32> stored in the block address latch circuit 161 and the blocks input from the logic group 180 are stored. If the addresses AXBLC <20:32> and AXBLC_N <20:32> match, node SENSE is connected to the ground node.

When the node SENSE is connected to the ground node, the first inverter IN1 inverts this and outputs a high level signal. Therefore, the bad block signal BADBLK is output at a high level.

The logic group 180 converts and outputs a block address so that all blocks are disabled by the bad block signal BADBLK.

When using the method of determining and disabling the bad block as described above, when a command for a multi-plane that simultaneously selects and operates the first and second planes 110 and 120 is input, the memory of the first plane 110 is input. Blocks cannot be selected normally.

This is because when the multi-plane operation command is input, the control logic 181 recognizes that all of the control logic 181 is disabled for the block address for the first plane. This is because after the address of the first plane is input, the address of the second plane is subsequently input with an operation command. When the operation command is continuously input, the control logic 181 recognizes the operation command for the multi plane and ignores the address of the first plane.

The reason why the block address of the first plane is disabled in the multi-plane operation command is that the current multi-plane operation command must select only memory blocks having the same address in the first and second planes 110 and 120. Because there is.

For example, in FIG. 1, if the memory block BK12 of the first plane 110 and the memory block BK23 of the second plane 120 are bad blocks, the multi-plane command may have a block address of '00'. It can be input only to the memory blocks BK11 and BK210.

Multi-plane commands cannot be input to memory blocks BK12 and BK22 with a block address of '01' or memory or memory blocks BK13 and BK23 with a block address of '10'.

Therefore, since it is obvious that the same block address is input to the first plane 110 and the second plane 120 when the multi-plane command is input, the block address for the first plane 110 is disabled. It is omitted.

Therefore, when a multi-plane command is input, an arbitrary block address may be selected for the first plane for the bad block, and it may be determined whether the bad block is a bad block.

If the randomly selected block address is a bad block, the operation cannot be executed normally.

According to an embodiment of the present invention, when a multi-plane command is input, an address of a block may be input to each plane, and the logic group 180 may operate by checking a bad block for each plane.

To this end, the logic group 180 is configured as follows.

3 illustrates a logic group of FIG. 1.

Referring to FIG. 3, the logic group 180 includes a control logic 181, a block enable logic 182, an address decoder 183, and a register 184.

The control logic 181 receives an operation command and address information and outputs a control signal for executing the operation command. The control logic 181 outputs a plane selection signal, a block address, and a column address included in the address information.

The block address is input to the block address comparison circuit 171 and the address decoder 183. The plane selection signal is input to the address decoder 183 and the block enable logic 182.

The column address is input to the column address comparison circuit 171.

The block enable logic 182 uses the control signals input from the control logic 181, the plane selection signal, and the bad block signal BADBLK from the block address comparison circuit 171 to control the first and second planes. Outputs the block enable signals XDECEN_P0 and XDECEN_P1.

The address decoder 183 may use a block selection signal from the control logic 181 and a block address signal (AX, BX, CX) to enable memory blocks of the first and second planes 110 and 120 using the block address. , DX).

When the block enable signals XDECEN_P0 and XDECEN_P1 of the first and second planes are input at a low level, the first address decoder 183 may transmit all of the block address signals AX, BX, CX, and DX of the plane. Output at the low level.

When the block addresses AX, BX, CX, and DX are all low level disabled, the X decoder 130 disables all blocks.

The register 184 stores option information, and uses the option information stored in the register 184 when the logic group 181 performs a control operation according to an operation command.

4 illustrates the block enable logic of FIG. 3.

Referring to FIG. 4, the block enable logic 182 includes a first plane enable unit 410, a second plane enable 420, and a reset signal output unit 430.

The first plane enable unit 410 is reset by the reset signal XDEC_RST output by the reset signal output unit 430, and is in response to the bad block signal BADBLK and the first plane selection signal PLANSEL_P0. Outputs the plane block enable signal XDECEN_P0.

The second plane enable unit 410 is reset by the reset signal XDEC_RST of the reset signal output unit 430, and in response to the bad block signal BADBLK and the second plane selection signal PLAESEL_P1, the second plane block 410 is reset. The enable signal XDECEN_P1 is output.

The reset signal output unit 430 may be configured to include the first and the first signals when power is input to the semiconductor memory device 100 to output power on reset, when an address is input, and when a command is input. The reset signal XDEC_RST is output to reset the output of the two-plane enable unit 410.

The first plane enable unit 410 includes first and second AND gates AND1 and AND2 and a first flip-flop F1, and the second plane enable unit 420 includes third and fourth ends. Gates AND3 and AND4 and a second flip-flop F2.

The reset signal output unit 430 includes an OR gate and a delay unit 431.

OR gate OR powers ON-reset signal POR, address storage signal ALEREG or address storage completion signal ALEDONE, and command input signal CLEREG or multi-plane command signal CI_DUALPLANE. Combine and print the result.

The output of the OR gate is the reset signal XDEC_RST. The reset signal XDEC_RST is input to the delay unit 431. In addition, the reset signal XDEC_RST is input to the reset terminals of the first and second flip-flops F1 and F2.

The delay unit 431 delays the reset signal XDEC_RST for a predetermined time and outputs the delayed signal. The output of the delay unit 431 is a delay reset signal XDEC_RST_DEL.

The delay reset signal XDEC_RST_DEL is input to the first and third AND gates AND1 and AND3.

An AND logic combination of the bad block signal BADBLK and the delay reset signal XDEC_RST_DEL is performed on the first AND gate AND1, and the result is output.

The output of the first AND gate AND1 is input to the second AND gate AND2.

The second AND gate AND2 performs an AND logic combination of the output of the first AND gate AND1 and the first plane select signal PLANSEL_P0, and outputs the result.

The output of the second AND gate AND2 is input to the clock terminal of the first flip flop F1 as the first clock signal CK0.

The first flip-flop F1 receives a power supply voltage and outputs a low level signal when the first clock signal CK0 is input at a high level. When the first clock signal CK0 is input at a low level, a high level signal is output.

The output of the first flip-flop F1 is the first plane block enable signal XDECEN_P0.

The third AND gate AND3 performs an AND logic combination of the bad block signal BADBLK and the delay reset signal XDEC_RST_DEL and outputs the result. The output of the third AND gate AND3 is input to the fourth AND gate AND4.

The fourth AND gate AND4 performs an AND logic combination on the outputs of the second plane selection signal PLANSEL_P1 and the third AND gate AND3, and outputs the result.

The output of the fourth AND gate AND4 is input to the clock terminal of the second flip-flop F2 as the second clock signal CK1.

The second flip-flop F2 receives a power supply voltage and outputs a low level signal when the second clock signal CK1 is input at a high level. When the second clock signal CK1 is input at a low level, a high level signal is output.

The output of the second flip-flop f2 is the second plane block enable signal XDECEN_P1.

The operation of the semiconductor memory device 100 according to the embodiment of the present invention will be described below.

5 is an operation timing diagram when a multi-plane command is input to a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 5, a command latch enable signal CLE is used to input an operation command in a state in which a chip enable signal CEb for enabling the semiconductor memory device 100 is applied at a low level. Is input at a high level. The operation command COM is input while the command latch enable signal CLE is at a high level.

When the operation command is input, the command latch enable signal CLE is changed to the low level.

The address latch enable signal ALE is input at a high level for address input, and the address is input while the address latch enable signal ALE is at a high level.

The address of the semiconductor memory device 100 is input in five cycles, the first two cycles being the column addresses Col1 and Col2, and the next three cycles being the row addresses Row1, Row2 and Row3.

The plane address and block address are included in the row address.

When the address is inputted, the address latch enable signal ALE is changed to the low level.

If the operation command is a program command, data to be programmed next is input.

The command latch enable signal CLE is applied to the high level again, and an end or confirmation command 11h is input.

When the operation command, address, data, and the like are input, data is input in accordance with toggling of the write enable signal WE #.

If it is an operation command for the multi-plane, the operation command, the address, the data, and the confirmation command are input again after a predetermined time. The memory blocks of the two planes are enabled at the same time to start the program operation.

At this time, the ready busy (R / B) signal is maintained at a high level while an operation command, an address, and data are input.

The read enable signal RE # is maintained at a high level and is applied at a low level when verifying is performed during a program operation.

When the multi-plane operation is performed, the operation of checking the bad block is as follows.

6 is a timing diagram illustrating a method of identifying a bad block according to an embodiment of the present invention.

Referring to FIG. 6, while the operation command is input as shown in FIG. 5, the command input signal CLEREG is at a high level, and the address storage signal ALEREG is at a high level while the address latch enable signal ALE is at a high level. It becomes a level. The address storage signal ALEREG is held at a high level until the next command is input, and is changed to a low level after the next command is input.

Then, according to the next command, the address is changed back to the high level while the address is input.

The address storage completion signal ALEDONE is changed to the high level when the address input is completed, and is changed to the low level when the next command starts to be input.

The multi-plane command signal CI_DUALPLANE is applied to the high level when the second operation command is input following the first operation command.

In the period T1 in which the operation command and the address for the first plane are input, the address storage signal ALEREG is at a high level, and the inverted signal ALEDONEb of the address storage completion signal ALEDONE is at a high level. The OR gate outputs a high level reset signal XDEC_RST during a period t1 in which the inverted signal CI_DUALPLANEb of the plane command signal CI_DUALPLANE is at a high level.

The first and second flip-flops F1 and F2 are reset by the high level reset signal XDEC_RST, and the first and second plane block enable signals XDECEN_P0 and XDECEN_P1 are output.

The reset signal XDEC_RST is delayed by the delay unit 431 and output as a delay delay signal XDEC_RST_DEL. The delay unit 431 delays the reset signal XDEC_RST by the time taken to compare whether the block address is a bad block.

When the address is input, the control logic 181 transmits the block address to the block address comparison circuit 171.

The block address comparison circuit 171 checks whether the block address from the control logic 181 is a bad block, and if the block address from the control logic 181 is an address of the bad block, the high level bad block signal BADBLK. Outputs

Referring to FIG. 6, when the block of the first plane is a bad block, the bad block signal BADBLK is changed to a high level after all addresses are input.

When the bad block signal BADBLK is output at a high level, the delay reset signal XDEC_RST_DEL is changed to a high level.

Since the block addresses of the first plane are compared with each other, the first plane selection signal PLANSEL_P0 is input at a high level.

Accordingly, the first AND gate AND1 outputs a high level, and the second AND gate AND2 also outputs a high level.

Since the output of the second AND gate AND2 is the first clock signal CK0, the first clock signal CK0 is also at a high level.

Therefore, the first flip-flop F1 outputs a low level signal. The output of the first flip-flop F1 is the first plane block enable signal XDECEN_P0. Therefore, the first plane block enable signal XDECEN_P0 is at a low level.

The low level of the first plane block enable signal XDECEN_P0 means that the memory block of the first plane input together with the operation command is a bad block.

The address decoder 183 disables all of the block address signals AX, BX, CX, and DX to a low level in response to the low level first plane block enable signal XDECEN_P0.

When the block address signals AX, BX, CX, and DX are all disabled at the low level, the memory blocks of the first plane 110 are all disabled.

The above-described operation is also repeated for the second input command and the address of the second plane.

That is, the address storage signal ALEREG is at a high level, the inverted signal ALEDONEb of the address storage confirmation signal ALEDONE is at a high level, and the inverted signal CI_DUALPLANEb of the multiplane command signal CI_DUALPLANE is at a high level. The reset signal XDEC_RST is output at a high level.

When the reset signal XDEC_RST is output at a high level, the first and second flip-flops F1 and F2 are reset.

The delay unit 431 delays the reset signal and outputs a delay reset signal XDEC_RST_DEL while checking whether the block address is a bad block in the address of the second plane.

If the block address of the second plane is a bad block, the bad block signal BADBLK is output at a high level.

The second plane selection signal PLANSEL_P1 also becomes high.

Therefore, the third and gate AND3 and the fourth and gate AND4 output high level signals. The output of the fourth AND gate AND4 is the second clock signal CK1.

Therefore, the second clock signal CK1 is also at a high level. When the second clock signal CK1 is at the high level, the second flip-flop F2 outputs the low level second plane block enable signal XDECEN_P1.

In response to the high level second plane block enable signal XDECEN_P1, the address decoder 183 disables all of the memory blocks in the second plane 120 (AX, BX, CX, DX). Outputs

According to the above operation, it is possible to confirm whether the bad block is a block for each plane for each of the multiple planes, and to prevent the operation from proceeding in the case of the bad block.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments of the present invention are possible within the scope of the technical idea of the present invention.

1 illustrates a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 illustrates a block address comparison circuit of FIG. 1.

3 illustrates a logic group of FIG. 1.

4 illustrates the block enable logic of FIG. 3.

5 is an operation timing diagram when a multi-plane command is input to a semiconductor memory device according to an embodiment of the present invention.

6 is a timing diagram illustrating a method of identifying a bad block according to an embodiment of the present invention.

* Brief description of the main parts of the drawings *

410: first plane enable portion

420: second plane enable part

430: reset signal output unit

Claims (10)

First and second planes comprising a plurality of memory blocks; A block address comparison circuit for comparing whether an input block address is a bad block address and outputting a bad block signal according to the comparison result; Enable logic for outputting a first and second plane block enable signal in response to the bad block signal and a first and second plane selection signal; An address decoder configured to output a block address signal in response to the first and second plane block enable signals, The enable logic is, Reset according to the logical combination of the power-on reset signal, the address storage signal, the inverted signal of the address storage completion signal, the inverted signal of the multi-plane operation command, and the command input signals enabled when the operation command is input. A reset signal output unit for outputting a signal and a delayed reset signal delaying the reset signal for a set time; A first plane enable unit configured to logically combine the delayed reset signal, the bad block signal, and the first plane selection signal, and output the first plane block enable signal according to a result; And A second plane enable unit configured to logically combine the delayed reset signal, the bad block signal, and the second plane selection signal, and output the second plane block enable signal according to a result; Semiconductor memory device comprising a. delete Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1, And the bad block signals respectively input to the first and second plane enable parts are output with respect to addresses of memory blocks of the corresponding plane. Claim 4 was abandoned when the registration fee was paid. The method of claim 3, The reset signal output unit, A power-on reset signal enabled when power is started to be input, an address storage signal enabled when an address is input, an inverted signal of an address storage completion signal enabled after address storage is completed, and a multi-plane operation command A first logic circuit that OR-combines the inverted signal of and the command input signals enabled when an operation command is input and outputs the result as the reset signal; And And a delay unit configured to delay the reset signal for a predetermined time and output the delayed reset signal as a delayed reset signal. Claim 5 was abandoned upon payment of a set-up fee. The delay unit, And delaying the reset signal until the block address comparison circuit outputs a bad block signal for the block address of the first or second plane. Claim 6 was abandoned when the registration fee was paid. The method of claim 3, The first plane enable portion, respectively A second logic circuit for and combining the delayed reset signal and the bad block signal for the block address of the first plane; A third logic circuit for AND combining the output of the second logic circuit and the first plane select signal; And And a first flip-flop reset by the reset signal and outputting the first or second plane block enable signal in response to an output of the third logic circuit. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 3, The second plane enable portion, A fourth logic circuit for and combining the delayed reset signal and the bad block signal for the block address of the second plane; And a second flip-flop reset by the reset signal and outputting the second plane block enable signal in response to an output of the fifth logic circuit. Claim 8 was abandoned when the registration fee was paid. The method of claim 1, And using one of the memory blocks of the first and second planes as a memory block for storing the bad block address. Claim 9 was abandoned upon payment of a set-up fee. The method of claim 8, A latch circuit for loading and storing the bad block address when power is started to be input, And the block address comparison circuit compares the bad block address stored in the latch circuit with the input block address, and outputs the bad block signal according to a comparison result. Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 1, And when the first or second plane block enable signal is disabled, the address decoder disables all block address signals on the plane.

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