KR101086074B1 - Silicon nanowire manufacturing method, solar cell including silicon nanowire and manufacturing method of solar cell - Google Patents

Abstract

The present invention relates to a method for manufacturing a silicon nanowire, a solar cell including the silicon nanowire, and a method for manufacturing the solar cell. According to the present invention, a substrate; A first ⁺⁺ type polycrystalline silicon layer provided on the substrate; A first type silicon nanowire layer comprising a first type silicon nanowire grown from the first ⁺⁺ type polycrystalline silicon layer; An intrinsic layer provided on the substrate provided with the first type silicon nanowire layer; And a second type doping layer provided on the intrinsic layer.

Silicon nanowires, metal catalysts, solar cells

Description

Method for fabricating silicon nano wire, solar cell including silicon nano wire and method for fabricating solar cell}

The present invention relates to a method for manufacturing a silicon nanowire, a solar cell including the silicon nanowire, and a method for manufacturing the solar cell.

Currently, the obligation to reduce greenhouse gases under the Climate Change Convention is accelerating, and the CO2 market is being activated accordingly, which is drawing attention in the renewable energy field.

Solar cell, a representative renewable energy field, is a system for producing electricity by using solar light, an infinite clean energy source, and a solar cell that directly converts light into electricity is at its core.

Currently, more than 90% of solar cells that are commercially available are bulk-based silicon solar cells, which are affected by silicon supply and demand, and are difficult to thin, thin, or low temperature because they are complicated by high temperature-oriented processes.

It is an object of the present invention to provide a method for producing silicon nanowires.

Another object of the present invention is to provide a method for producing silicon nanowires from a seed layer using low temperature high density plasma.

Still another object of the present invention is to provide a method of manufacturing a solar cell including a method of manufacturing silicon nanowires.

In order to achieve the above object, according to an aspect of the present invention, a substrate; A first ⁺⁺ type polycrystalline silicon layer provided on the substrate; A first type silicon nanowire layer comprising a first type silicon nanowire grown from the first ⁺⁺ type polycrystalline silicon layer; An intrinsic layer provided on the substrate provided with the first type silicon nanowire layer; And a second type doping layer provided on the intrinsic layer.

The solar cell: a TCO layer provided on the second type doping layer; An anti-reflection film provided on the TCO layer to expose certain regions of the TCO layer; And a front electrode provided in a patterned form on predetermined regions of the exposed TCO layer.

The solar cell: TCO layer provided between the substrate and the first ⁺⁺ type polycrystalline silicon layer; And a back electrode provided on the second type doped layer.

The intrinsic layer is a top cell intrinsic layer, the second type doping layer is a top cell type 2 doping layer, and the solar cell includes: a buffer layer provided on the top cell type 2 doping layer; A bottom cell first type doping layer provided on the buffer layer; A bottom cell intrinsic layer provided on the bottom cell first type doping layer; A bottom cell second type doping layer provided on the bottom cell intrinsic layer; And a back electrode provided on the bottom cell type 2 doped layer.

The first type silicon nanowires have a length of 2 to 5 µm and a diameter of 1 to 5 nm.

In order to achieve the above object, according to another aspect of the invention, the first ⁺⁺ type polysilicon layer forming step of forming a first ⁺⁺ type polycrystalline silicon layer on a substrate; A metal thin film layer forming step of forming a metal thin film layer on the first ⁺⁺ type polycrystalline silicon layer; A metal nanoparticle forming step of forming the metal thin film layer using metal nanoparticles; And a first type silicon nanowire growth step of growing a first type silicon nanowire from the first ⁺⁺ type polycrystalline silicon layer using the metal nanoparticle as a seed.

In order to achieve the above object, according to still another aspect of the present invention, there is provided a solar cell manufacturing method, the first ⁺⁺ type polysilicon layer forming step of forming a first ⁺⁺ type polycrystalline silicon layer on a substrate; A metal thin film layer forming step of forming a metal thin film layer on the first ⁺⁺ type polycrystalline silicon layer; A metal nanoparticle forming step of forming the metal thin film layer using metal nanoparticles; And a first type silicon nanowire growth step of growing a first type silicon nanowire from the first ⁺⁺ type polycrystalline silicon layer using the metal nanoparticle as a seed.

An intrinsic layer forming step of forming an intrinsic layer on the substrate on which the first type silicon nanowires are grown after the first type silicon nanowire growth step; A second type doping layer forming step of forming a second type doping layer on the intrinsic layer; Forming a TCO layer on the second type doped layer; An anti-reflection film forming step of forming an anti-reflection film on the TCO layer; And a front electrode forming step of forming a front electrode on the anti-reflection film.

And a TCO layer forming step of forming a TCO layer on the substrate before the forming of the first ⁺⁺ type polycrystalline silicon layer, and after the growing of the first type silicon nanowire, the first type of silicon nano An intrinsic layer forming step of forming an intrinsic layer on the substrate on which the wire is grown; A second type doping layer forming step of forming a second type doping layer on the intrinsic layer; And a back electrode forming step of forming a back electrode on the second type doped layer.

And a TCO layer forming step of forming a TCO layer on the substrate before the forming of the first ⁺⁺ type polycrystalline silicon layer, and after the growing of the first type silicon nanowire, the first type of silicon nano Forming a top cell intrinsic layer on the substrate on which the wire is grown; Forming a top cell second type doping layer to form a top cell second type doping layer on the top cell intrinsic layer; A buffer layer forming step of forming a buffer layer on the top cell type 2 doped layer; A bottom cell first type doping layer forming step of forming a bottom cell first type doping layer on the buffer layer; A bottom cell intrinsic layer forming step of forming a bottom cell intrinsic layer on the bottom cell first type doping layer; Forming a bottom cell second type doping layer on the bottom cell intrinsic layer; And a back electrode forming step of forming a back electrode on the bottom cell type 2 doped layer.

The metal thin film layer forming step is a step of depositing a metal using a sputtering method or an evaporation method (evaporation method), a thickness of 100 to 150nm.

The metal nanoparticle forming step and the first type of silicon nanowire growth step use an inductively coupled plasma chemical vapor deposition device or a very high frequency-chemical vapor deposition device.

The metal nanoparticle forming step and the first type of silicon nanowire growth step are continuously performed using an inductively coupled plasma chemical vapor deposition apparatus or an ultra-high frequency chemical vapor deposition apparatus.

The metal nanoparticle forming step is a process temperature of 200 to 400 ℃, a process pressure of 80 to 150mTorr, hydrogen (H ₂ ) gas flow rate of 100 to 300sccm, plasma power of 500 to 700W, susceptor power of 30 to 50W and 30 The metal thin film layer is formed of metal nanoparticles using the inductively coupled plasma chemical vapor deposition apparatus under a process condition including a process time of about 90 minutes.

The metal nanoparticle forming step may be performed using the ultra-high frequency chemical vapor deposition apparatus under process conditions including a process temperature of 200 to 400 ° C., a process pressure of 0.05 to 0.2 Torr, a plasma power of 40 to 60 W, and a processing time of 30 to 60 minutes. Forming the metal thin film layer using metal nanoparticles.

The type 1 silicon nanowire growth step includes a process temperature of 200 to 400 ° C., a process pressure of 70 to 80 mTorr, a silane gas ratio of 0.1 to 0.2, a plasma power of 500 to 700 W, a susceptor power of 30 to 50 W, and 1 to 20 Using the inductively coupled plasma chemical vapor deposition apparatus at a process condition including a process time of minutes, wherein the silane gas ratio is a ratio of the silane gas in a mixed gas of silane (SiH ₄ ) gas and hydrogen gas.

The type 1 silicon nanowire growth step includes a process temperature of 200 to 400 ° C., a process pressure of 0.05 to 0.2 Torr, a silane gas ratio of 0.4 to 0.6, a plasma power of 40 to 60 W, and a processing time of 30 to 60 minutes. Using the ultra-high frequency chemical vapor deposition apparatus as a process condition, wherein the silane gas ratio is the ratio of the silane gas in a mixed gas of silane gas and hydrogen gas.

The silicon nanowires have a length of 2 to 5 µm and a diameter of 1 to 5 nm.

And a residual metal removal step of removing metal remaining on the substrate after the first type silicon nanowire growth step.

According to the configuration of the present invention can achieve all the objects of the present invention described above. Specifically, according to the present invention, there is an effect of providing a method for producing a silicon nanowire.

In addition, according to the present invention, there is an effect of providing a method for forming a seed layer using a low-temperature, high-density plasma, and manufacturing a silicon nanowire using the seed layer.

Moreover, according to this invention, there exists an effect of providing the method of manufacturing the solar cell containing the method of manufacturing a silicon nanowire.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view showing a solar cell according to an embodiment of the present invention.

Referring to FIG. 1, a solar cell 100 according to an embodiment of the present invention includes a substrate 110, a first ⁺⁺ type polycrystalline silicon layer 120, a first type silicon nanowire layer 130, An intrinsic layer 140, a second type doping layer 150, a TCO layer 160, an antireflection film 170, and a front electrode 180 are included.

In this case, the first type is P type, and the second type is N type. On the contrary, the first type may be N type and the second type may be P type.

On the other hand, the first type or the second type represented by the "++" indicates the degree of doping the P-type or N-type impurities, "+" than the type 1 or type 2 without the "+" mark Type 1 or type 2 with more impurity doped, type 1 or type 2 with "++" sign type 1 or type 2 with "+" sign That means more impurities are doped.

The substrate 110 may be made of an opaque substrate such as a transparent insulating substrate or a metal foil substrate through which sunlight can pass.

When the substrate 110 is made of a transparent insulating substrate, the substrate 110 may be made of a glass substrate or plastic.

The substrate 110 in this case made of a metal foil substrate, a first ⁺⁺ type substrate for the insulation of the polysilicon layer 120, 110 from the first ⁺⁺ is provided on the substrate 110, An insulating layer may be provided between the type polycrystalline silicon layers 120.

The first ⁺⁺ type polycrystalline silicon layer 120 is provided on one surface of the substrate 110.

The first ⁺⁺ type polycrystalline silicon layer 120 is provided with a polycrystalline silicon layer doped with a high concentration of the first type.

The first ⁺⁺ type polycrystalline silicon layer 120 is formed of polycrystalline silicon doped with a high concentration of the first type to serve as a back electrode.

In addition, the first ⁺⁺ type polycrystalline silicon layer 120 serves as a seed layer in which the first type silicon nanowires of the first type silicon nanowire layer 130 grow.

The first type silicon nanowire layer 130 is formed of first type silicon nanowires grown in predetermined regions of the first ⁺⁺ type polycrystalline silicon layer 120. That is, the first type silicon nanowire layer 130 may have predetermined regions of the first ⁺⁺ type polycrystalline silicon layer 120 by a metal induced crystallization method or a laser crystallization method. It is made by the first type silicon nanowires grown in.

The length of the first type silicon nanowire constituting the first type silicon nanowire layer 130 is 2 to 5㎛, the diameter is preferably 1 to 5nm. This is because the first type silicon nanowires of the first type silicon nanowire layer 130 absorb light when sunlight is incident. That is, it is preferable that the first type silicon nanowires are formed to have a length and diameter of 2 to 5 µm and 1 to 5 nm, which are the length and diameter capable of absorbing sunlight best.

The intrinsic layer 140 is a surface of the first type silicon nanowire layer 130 and the first ⁺⁺ type polycrystalline silicon layer 120 on which the first type silicon nanowires are not grown, that is, the first type. The type silicon nano wire layer 130 is provided on the substrate 110.

The intrinsic layer 140 is made of intrinsic silicon which is not doped with impurities of the first type or the second type.

The intrinsic layer 140 may be made of intrinsic silicon in various forms. Preferably, the intrinsic layer 140 is formed of a hydrogenated amorphous silicon layer, that is, an α-Si: H layer.

The intrinsic layer 140 also functions to passivate the first type silicon nanowire layer 130.

The intrinsic layer 140 may be formed by chemical vapor deposition or physical vapor deposition. Preferably, the intrinsic layer 140 may be formed by inductively coupled plasma-chemical vapor deposition.

When the intrinsic layer 140 is deposited by the inductively coupled plasma chemical vapor deposition apparatus, a mixed gas including hydrogen (H ₂ ) gas and silane (SiH ₄ ) gas is used, and the hydrogen gas to silane gas ratio ( H ₂ / SiH ₄ ratio) is 8 to 10, the process pressure is 70 to 90mtorr, the process power is 200 to 300W, the process temperature is preferably formed by deposition under process conditions of 250 to 350 ℃.

When the intrinsic layer 140 is formed by the inductively coupled plasma chemical vapor deposition apparatus, the interfacial characteristics with the layer in contact with the intrinsic layer 140, in particular, the first type silicon nanowire layer 130 are excellent. Become.

The second type doped layer 150 is provided on the intrinsic layer 140.

The second type doped layer 150 is formed of a silicon layer doped with a second type.

The second type doping layer 150 may be formed of a second ⁺ type doping layer, and may be formed of a second type doping layer having a lower impurity concentration of type 2 than that of the second ⁺ type doping layer.

The second type doping layer 150 may be formed of a chemical vapor deposition device such as plasma enhanced chemical vapor deposition, a physical vapor deposition device, or the like.

The transparent conducting oxide (TCO) layer 160 is provided on the second type doped layer 150.

The TCO layer 160 may be made of a transparent conductive oxide such as zinc oxide (ZnO), aluminum zinc-doped ZnO film, aluminum zinc oxide (AZO), indium tin oxide (ITO), and SnO 2: F.

Preferably, the TCO layer 160 is formed to have a thickness of at least 5 μm or more, and is formed using a physical vapor deposition apparatus such as a sputtering apparatus or a chemical vapor deposition apparatus such as metal organic chemical vapor deposition (MOCVD). can do.

The anti-reflection film 170 is provided on the TCO layer 160, and some regions of the TCO layer 160 are exposed.

The anti-reflection film 170 is configured to prevent incident sunlight from being reflected and emitted to the outside, and serves to increase photoelectric conversion efficiency of the solar cell 100.

The anti-reflection film 170 may be formed of a material such as silicon nitride (SiN).

The front electrode 180 is provided to contact the TCO layer 160 on some regions of the TCO layer 160 exposed by the anti-reflection film 170.

The front electrode 180 is made of a conductive material such as aluminum (Al) or silver (Ag).

The front electrode 180 is made of a thickness of 0.2 to 1㎛, preferably 0.5㎛.

The front electrode 180 is provided in a patterned form.

2 is a cross-sectional view showing a solar cell according to another embodiment of the present invention.

Referring to FIG. 2, the solar cell 200 according to another embodiment of the present invention includes a substrate 210, a TCO layer 220, a first ⁺⁺ type polycrystalline silicon layer 230, and a first type silicon nano. The wire layer 240, the intrinsic layer 250, the second type doping layer 260, and the back electrode 270 are included.

The substrate 210 may be formed of a transparent insulating substrate through which sunlight can pass.

The substrate 210 may be made of a glass substrate or plastic.

The TCO layer 220 is provided on one surface of the substrate 210.

The TCO layer 220 may be made of a transparent conductive oxide such as ZnO, AZO, ITO, SnO 2: F, and the like.

The TCO layer 220 may be formed using a physical vapor deposition apparatus such as a sputtering apparatus or a chemical vapor deposition apparatus such as MOCVD.

The first ⁺⁺ type polycrystalline silicon layer 230 is provided on the TCO layer 220.

The first ⁺⁺ type polycrystalline silicon layer 230 is provided with a polycrystalline silicon layer doped with a high concentration of the first type.

In addition, the first ⁺⁺ type polycrystalline silicon layer 230 serves as a seed layer in which the first type silicon nanowires of the first type silicon nanowire layer 240 grow.

The first type silicon nanowire layer 240 is formed of first type silicon nanowires grown in predetermined regions of the first ⁺⁺ type polycrystalline silicon layer 230. That is, the first type silicon nanowire layer 240 is formed on the first type silicon nanowires grown in predetermined regions of the first ⁺⁺ type polycrystalline silicon layer 230 by metal induced crystallization or laser crystallization. Is made by

The length of the first type silicon nanowires constituting the first type silicon nanowire layer 240 is 2 to 5㎛, the diameter is preferably 1 to 5nm. This is because the first type silicon nanowire of the first type silicon nanowire layer 240 absorbs light when sunlight is incident. That is, it is preferable that the first type silicon nanowires are formed to have a length and diameter of 2 to 5 µm and 1 to 5 nm, which are the length and diameter capable of absorbing sunlight best.

The intrinsic layer 250 is provided on the surface of the first type silicon nanowire layer 240 and the first ⁺⁺ type polycrystalline silicon layer 240 in which the first type silicon nanowires are not grown.

The intrinsic layer 250 is made of intrinsic silicon which is not doped with impurities of the first type or the second type.

The intrinsic layer 250 may be made of intrinsic silicon in various forms. Preferably, the intrinsic layer 250 is formed of a hydrogenated amorphous silicon layer, that is, an α-Si: H layer.

The intrinsic layer 250 is provided to a thickness of 400 to 600nm, preferably 500nm.

The intrinsic layer 250 also serves to passivate the first type silicon nanowire layer 240.

The intrinsic layer 250 may be formed by a chemical vapor deposition apparatus or a physical vapor deposition apparatus. Preferably, the intrinsic layer 250 may be formed of an inductively coupled plasma chemical vapor deposition apparatus.

When the intrinsic layer 250 is deposited by the inductively coupled plasma chemical vapor deposition apparatus, a mixed gas including hydrogen gas and silane gas is used, and the hydrogen gas to silane gas ratio (H ₂ / SiH ₄ ratio) is 8 to 10, the process pressure is 70 to 90mtorr, the process power is 200 to 300W, the process temperature is preferably formed by deposition under process conditions of 250 to 350 ℃.

When the intrinsic layer 250 is formed by the inductively coupled plasma chemical vapor deposition apparatus, the interfacial characteristics with the layer in contact with the intrinsic layer 250, in particular, the first type silicon nanowire layer 240 are excellent. Become.

The second type doped layer 260 is provided on the intrinsic layer 250.

The second type doped layer 260 is formed of a silicon layer doped with a second type.

The second type doping layer 260 may be formed of a second ⁺ type doping layer, and may be formed of a second type doping layer having a lower impurity concentration of type 2 than that of the second ⁺ type doping layer.

The second type doping layer 260 may be formed of a chemical vapor deposition apparatus or a physical vapor deposition apparatus such as a plasma chemical vapor deposition apparatus.

The second type doped layer 260 is provided in a thickness of 10 to 15nm, preferably 12nm.

The back electrode 270 is provided on the second type doped layer 260.

The back electrode 270 is made of a conductive material such as aluminum or silver.

The back electrode 270 is provided on the entire surface of the second type coating layer 260.

The back electrode 270 also serves as an anti-reflection film that prevents incident sunlight from being reflected and emitted to the outside.

When the back electrode 270 is formed of aluminum, it is provided with a thickness of 200 to 400 nm, preferably 300 nm.

3 is a cross-sectional view showing a solar cell according to another embodiment of the present invention.

Referring to FIG. 3, the solar cell 300 according to another embodiment of the present invention includes a substrate 310, a TCO layer 320, a top cell 330, a buffer layer 340, a bottom cell 350, and The back electrode 360 is included.

The top cell 330 includes a first ⁺⁺ type polycrystalline silicon layer 332, a first type silicon nanowire layer 334, a top cell intrinsic layer 336, and a top cell second type doping layer 338.

The bottom cell 350 includes a bottom cell first type doping layer 352, a bottom cell intrinsic layer 354, and a bottom cell second type doping layer 356.

The substrate 310 may be formed of a transparent insulating substrate through which sunlight can pass.

The substrate 310 may be made of a glass substrate or plastic.

The TCO layer 320 is provided on one surface of the substrate 310.

The TCO layer 320 may be made of a transparent conductive oxide such as ZnO, AZO, ITO, SnO 2: F, or the like.

The first ⁺⁺ type polycrystalline silicon layer 332 is provided on the TCO layer 320.

The first ⁺⁺ type polycrystalline silicon layer 332 is provided with a polycrystalline silicon layer doped with a high concentration of the first type.

The first ⁺⁺ type polycrystalline silicon layer 332 serves as a seed layer in which the first type silicon nanowires of the first type silicon nanowire layer 334 grow.

The first type silicon nanowire layer 334 is formed of first type silicon nanowires grown in predetermined regions of the first ⁺⁺ type polycrystalline silicon layer 332. That is, the first type silicon nanowire layer 332 is formed on the first type silicon nanowires grown in predetermined regions of the first ⁺⁺ type polycrystalline silicon layer 332 by metal induced crystallization or laser crystallization. Is made by

It is preferable that the length of the said 1st type silicon nanowire which comprises the said 1st type silicon nanowire layer 334 is 2-5 micrometers, and the diameter is 1-5 nm. This is because the first type silicon nanowires of the first type silicon nanowire layer 334 absorb light when sunlight is incident. That is, it is preferable that the first type silicon nanowires are formed to have a length and diameter of 2 to 5 µm and 1 to 5 nm, which are the length and diameter capable of absorbing sunlight best.

The top cell intrinsic layer 336 is provided on the surfaces of the first type silicon nanowire layer 334 and the first ⁺⁺ type polycrystalline silicon layer 332 on which the first type silicon nanowires are not grown.

The top cell intrinsic layer 336 is made of intrinsic silicon which is not doped with impurities of the first type or the second type.

The top cell intrinsic layer 336 may be made of intrinsic silicon in various forms, but preferably, is made of a hydrogenated amorphous silicon layer, that is, an α-Si: H layer.

In this case, the top cell intrinsic layer 336 may be provided in the same form as the intrinsic layer 250 described with reference to FIG. 2.

The top cell intrinsic layer 336 may also passivate the first type silicon nanowire layer 334.

The top cell intrinsic layer 336 may be formed by a chemical vapor deposition apparatus or a physical vapor deposition apparatus. Preferably, the top cell intrinsic layer 336 may be formed by an inductively coupled plasma chemical vapor deposition apparatus.

When the top cell intrinsic layer 336 is deposited by the inductively coupled plasma chemical vapor deposition apparatus, a mixed gas including hydrogen gas and silane gas is used, and the hydrogen gas to silane gas ratio (H ₂ / SiH ₄ ratio) is used. Is 8 to 10, the process pressure is 70 to 90 mtorr, the process power is 200 to 300W, the process temperature is preferably formed by deposition under process conditions of 250 to 350 ℃.

When the top cell intrinsic layer 336 is formed by the inductively coupled plasma chemical vapor deposition apparatus, the interfacial property with the layer in contact with the top cell intrinsic layer 336, in particular, the first type silicon nanowire layer 334. This is excellent.

The top cell intrinsic layer 336 is provided with a thickness of 400 to 600 nm, preferably 500 nm.

The top cell second type doping layer 338 is provided on the top cell intrinsic layer 336.

The top cell type 2 doped layer 338 is formed of a silicon layer doped with impurities of type 2.

In this case, the top cell second type doping layer 338 may be provided in the same form as the second type doping layer 260 described with reference to FIG. 2.

The top cell second type doping layer 338 may be formed of a second ⁺ type doping layer, and may be formed of a second type doping layer having a lower impurity concentration of type 2 than that of the second ⁺ type doping layer.

The top cell type 2 doped layer 338 may be formed of a chemical vapor deposition device or a physical vapor deposition device such as a plasma chemical vapor deposition device.

The buffer layer 340 is provided on the top cell second type doping layer 338.

The buffer layer 340 electrically connects the top cell 330 and the bottom cell 350.

The buffer layer 340 is the top cell 330 and the bottom cell 350, in particular, the top cell second type doping layer 338 of the top cell 330 and the bottom first type doping layer 352 of the bottom cell 350. ) Serves for tunnel junctions.

The buffer layer 340 also serves to adjust a band gap between the top cell 330 and the bottom cell 350.

The buffer layer 340 is preferably made of a transparent conductive material such as ZnO.

The bottom cell first type doping layer 352 is provided on the buffer layer 340.

The bottom cell first type doping layer 352 may be formed of a first ⁺ type doping layer, and may be formed of a second type doping layer having a lower impurity concentration of a second type than the first ⁺ type doping layer.

The bottom cell type 1 doping layer 352 may be formed of a chemical vapor deposition device or a physical vapor deposition device such as a plasma chemical vapor deposition device.

The bottom cell intrinsic layer 354 is provided on the bottom cell first type doping layer 352.

The bottom cell intrinsic layer 354 is made of intrinsic silicon that is not doped with impurities of the first type or the second type.

The bottom cell intrinsic layer 354 may be made of intrinsic silicon in various forms. Preferably, the bottom cell intrinsic layer 354 is formed of a hydrogenated microcrystalline silicon layer, that is, a μc-Si: H layer.

The bottom cell intrinsic layer 354 may be formed by a chemical vapor deposition apparatus or a physical vapor deposition apparatus.

The bottom cell intrinsic layer 354 is provided with a thickness of 1 to 2㎛.

The bottom cell second type doping layer 356 is provided on the bottom cell intrinsic layer 354.

The bottom cell type 2 doped layer 356 is formed of a silicon layer doped with impurities of type 2.

The bottom cell second type doping layer 356 may be formed of a second ⁺ type doping layer, and may be formed of a second type doping layer having a lower impurity concentration of type 2 than the second ⁺ type doping layer.

The bottom cell type 2 doped layer 356 may be formed of a chemical vapor deposition apparatus such as a plasma chemical vapor deposition apparatus or a physical vapor deposition apparatus.

The back electrode 360 is provided on the second type doped layer 356.

The back electrode 360 is made of a conductive material such as aluminum or silver.

4 is a flowchart illustrating a method of manufacturing a first type silicon nanowire according to an embodiment of the present invention.

Referring to FIG. 4, the method of manufacturing a first type silicon nanowire according to an embodiment of the present invention may include forming a first ⁺⁺ type polycrystalline silicon layer (S110), forming a metal thin film layer (S120), and a metal. Nanoparticles forming step (S130), the first type of silicon nanowires growth step (S140) and residual metal removal step (S150).

The first ⁺⁺ type polycrystalline silicon layer forming step (S110) is a step of forming a first ⁺⁺ type polycrystalline silicon layer on a substrate.

In the first ⁺⁺ type polycrystalline silicon layer, the silicon layer doped with a high concentration of the first type is crystallized into polycrystal.

In the forming of the first ⁺⁺ type polycrystalline silicon layer (S110), the first ⁺⁺ type polycrystalline silicon layer may be formed by various methods.

In this embodiment, one of the methods for forming the first ⁺⁺ type polycrystalline silicon layer is introduced.

The first ⁺⁺ type polycrystalline silicon layer may be formed by forming a first ⁺⁺ type amorphous silicon layer on the substrate, and using a metal induced crystallization method or a laser crystallization method. There may be a method of forming the first ⁺⁺ type silicon layer into the first ⁺⁺ type polycrystalline silicon layer using the same crystallization method.

In this case, a method of forming the first ⁺⁺ type amorphous silicon layer may use a general silicon layer forming method. That is, the first layer on the substrate 110 may be formed using a chemical vapor deposition apparatus such as plasma enhanced chemical vapor deposition or inductively coupled plasma chemical vapor deposition. ⁺⁺ type amorphous silicon layer can be formed.

After the first ⁺⁺ type polycrystalline silicon layer forming step S110, the metal thin film layer forming step S120 is performed.

The metal thin film layer forming step (S120) is a step of forming a metal layer by depositing a metal on the first ⁺⁺ type polycrystalline silicon layer using a sputtering method or an evaporation method.

In the forming of the metal thin film layer (S120), the metal layer is deposited to a thickness of 100 to 150 nm.

In the forming of the metal thin film layer (S120), the metal layer may be formed, but the metal layer may be formed to deposit metals of the metal layer at low density. This is for the metal layer to be easily changed to the metal nanoparticles in the metal nanoparticle forming step (S130).

The metal of the metal thin film layer includes any one or more of Au, In, Ga, and Sn.

After the metal thin film layer forming step (S120), the metal nanoparticle forming step (S130) is performed.

The metal nanoparticle forming step (S130) is a step of changing the metal thin film layer to metal nanoparticles.

The metal nanoparticle forming step (S130) forms the metal nanoparticles by using an inductively coupled plasma chemical vapor deposition apparatus or a very high frequency-chemical vapor deposition apparatus.

The metal nanoparticle forming step (S130), when using the inductively coupled plasma chemical vapor deposition apparatus, a process temperature of 200 to 400 ℃, a process pressure of 80 to 150 mTorr, hydrogen (H ₂ ) gas flow rate of 500 to 100 sccm, 500 The metal nanoparticles may be formed under process conditions including a plasma power of about 700 W, a susceptor power of 30 to 50 W, and a processing time of about 30 to 90 minutes.

In addition, the metal nanoparticle forming step (S130), when using the ultra-high frequency chemical vapor deposition apparatus, a process temperature of 200 to 400 ℃, a process pressure of 0.05 to 0.2Torr, plasma power of 40 to 60W and 30 to 60 minutes The metal nanoparticles may be formed under process conditions including a process time.

After the metal nanoparticle formation step (S130), the first type silicon nanowires growth step (S140) is performed.

The first type silicon nanowire growth step (S140) is a step of growing the first type silicon nanowire, precisely the first type silicon nanowire, by using an inductively coupled plasma chemical vapor deposition apparatus or an ultra-high frequency chemical vapor deposition apparatus. .

The first type silicon nanowire growth step (S140) is the first type silicon nanowire using the first ⁺⁺ type polycrystalline silicon layer on which the metal nanoparticles are formed in the metal nanoparticle formation step (S130) as a seed layer. Step of growing.

That is, the metal nanoparticles formed on the first ⁺⁺ type polycrystalline silicon layer serve as a seed of crystal growth, and the first type silicon nanowires are grown from the first ⁺⁺ type polycrystalline silicon layer.

The first type of silicon nanowire growth step (S140), when using the inductively coupled plasma chemical vapor deposition apparatus, a process temperature of 200 to 400 ℃, a process pressure of 70 to 80 mTorr, silane gas ratio of 0.1 to 0.2, 500 to 700 W Growing the first type silicon nanowire under process conditions including a plasma power, a susceptor power of 30 to 50 W, and a processing time of 1 to 20 minutes.

In addition, the first type of silicon nanowire growth step (S140), when using the ultra-high frequency chemical vapor deposition apparatus, a process temperature of 200 to 400 ℃, a process pressure of 0.05 to 0.2 Torr, silane gas ratio of 0.4 to 0.6, 40 to Growing the first type silicon nanowire under a process condition including a plasma power of 60 W and a process time of 30 to 60 minutes.

In this case, the silane gas ratio is the ratio of the silane gas in the mixed gas of silane gas and hydrogen gas during the process of growing the type 1 silicon nanowires using the inductively coupled plasma chemical vapor deposition apparatus and the ultra-high frequency chemical vapor deposition apparatus. SiH ₄ / (SiH ₄ + H ₂ )).

The metal nanoparticle forming step (S130) and the first type of silicon nanowire growth step (S140) may be continuously performed using the inductively coupled plasma chemical vapor deposition apparatus and ultra-high frequency chemical vapor deposition apparatus. That is, the metal thin film layer provided on the first ⁺⁺ type polycrystalline silicon layer is changed into metal nanoparticles, and the first type silicon nanowire is formed from the first ⁺⁺ type polycrystalline silicon layer using the metal nanoparticles. The growth process may be carried out in a continuous process in the inductively coupled plasma chemical vapor deposition apparatus or ultra-high frequency chemical vapor deposition apparatus.

In this case, the first type silicon nanowires grown in the first type silicon nanowire growth step S140 have a length of 2 to 5 μm and a diameter of 1 to 5 nm.

After the first type of silicon nanowire growth step (S140), the residual metal removal step (S150) is performed.

The residual metal removing step (S150) is a metal remaining on the substrate, in particular, the first type silicon nanowire layer made of the first type silicon nanowires after the first type silicon nanowire growth step (S140). Is removed by a wet process such as etching.

In this case, the remaining metal may be part of the metal thin film layer or part of the metal nanoparticles.

5 is a flowchart illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.

Referring to Figure 5, the solar cell manufacturing method according to an embodiment of the present invention is the first ⁺⁺ type polycrystalline silicon layer forming step (S210), the first type silicon nanowire layer forming step (S220), intrinsic And a layer forming step S230, a second type doping layer forming step S240, a TCO layer forming step S250, an antireflection film forming step S260, and a front electrode forming step S270.

The solar cell manufacturing method according to the present embodiment will be described based on the method of manufacturing the solar cell 100 described with reference to FIG. 1.

The forming of the first ⁺⁺ type polycrystalline silicon layer (S210) is a step of forming the first ⁺⁺ type polycrystalline silicon layer 120 on the substrate 110.

First, before forming the first ⁺⁺ type polycrystalline silicon layer 120 on the substrate 110, the substrate 110 is cleaned and prepared. In this case, the process of cleaning the substrate 110 may be a process of removing organic substances, metals, and oxides remaining on the substrate 110. The process of removing organic substances, metals, and oxides remaining on the substrate 110 may use a process used in a general semiconductor manufacturing process.

Subsequently, the first ⁺⁺ type polycrystalline silicon layer 120 is formed on the substrate 110.

The first ⁺⁺ type polycrystalline silicon layer 120 may be formed on the substrate 110 using the same method as the first ⁺⁺ type polycrystalline silicon layer forming step S110 described with reference to FIG. 4. Detailed description is omitted.

After the first ⁺⁺ type polycrystalline silicon layer forming step S210, the first type silicon nanowire layer forming step S220 is performed.

In the forming of the first type silicon nanowire layer (S220), the first type silicon nanowire layer is grown on the first ⁺⁺ type polycrystalline silicon layer 120 to form the first type silicon nanowire layer 130. It's a step.

The first type silicon nanowire layer forming step (S220) may include the metal thin film layer forming step (S120), the metal nanoparticle forming step (S130), the first type silicon nanowire growing step (S140), and the method described with reference to FIG. 4. Residual metal removal step (S150) is sequentially performed to grow the first type silicon nanowires from the first ⁺⁺ type polycrystalline silicon layer 120 to form the first type silicon nanowire layer 130 Detailed description is omitted since it is a step.

After the first type of silicon nanowire layer forming step S220, the intrinsic layer forming step S230 is performed.

The intrinsic layer forming step (S230) may be performed on the surface of the first type silicon nanowire layer 130 and the first ⁺⁺ type polycrystalline silicon layer 120 on which the first type silicon nanowires are not grown. 140 is a step of forming.

The intrinsic layer forming step (S230) may form an intrinsic layer 140 made of intrinsic silicon of various types without doping impurities of a first type or a second type, but preferably, a hydrogenated amorphous silicon layer, that is, It is preferable to form an intrinsic layer 140 composed of an α-Si: H layer.

The intrinsic layer forming step (S230) may be a step of forming the intrinsic layer 140 using a chemical vapor deposition apparatus or a physical vapor deposition apparatus, preferably an inductively coupled plasma chemical vapor deposition apparatus.

In the intrinsic layer forming step (S230), when using the inductively coupled plasma chemical vapor deposition apparatus, a mixed gas including hydrogen gas and silane gas is used, and the hydrogen gas to silane gas ratio (H ₂ / SiH ₄ ratio) is used. Is 8 to 10, the process pressure is 70 to 90mtorr, the process power is 200 to 300W, the process temperature is preferably formed in the intrinsic layer 140 under the process conditions of 250 to 350 ℃.

After the intrinsic layer forming step (S230), the second doped layer forming step (S240) is performed.

The second doping layer forming step (S240) is a step of forming the second type doping layer 150 on the intrinsic layer 140.

The second type doping layer forming step (S240) is a chemical vapor deposition apparatus such as a plasma chemical vapor deposition apparatus or the like, or a physical vapor deposition apparatus, etc., the second type impurity or the second layer of the silicon layer doped with the second ⁺ type impurities The doping layer 150 may be formed.

After the second type doped layer forming step S240, the TCO layer forming step S250 is performed.

The TCO layer forming step (S250) is a step of forming the TCO layer 160 on the second type doped layer 150.

The TCO layer forming step S250 may include at least 5 TCO layers 160 made of a transparent conductive oxide such as ZnO, AZO, ITO, SnO ₂ : F, etc. on the second type doped layer 150. It is a step of forming to a thickness of more than μm.

The TCO layer forming step S250 may be a step of forming the TCO layer 160 by using a physical vapor deposition apparatus such as a sputtering apparatus or a chemical vapor deposition apparatus such as MOCVD.

After the TCO layer forming step (S250), the anti-reflection film forming step (S260) is performed.

The anti-reflection film forming step (S260) is a step of forming the anti-reflection film 170 on the TCO layer 160 with a material such as a silicon nitride film.

The anti-reflection film forming step (S260) may be a step of forming the anti-reflection film 170 in two ways.

The first method is to form the anti-reflection film 170 on the entire surface on the TCO layer 160, the second method is to form the anti-reflection film 170 on the TCO layer 160, the TCO The anti-reflection film 170 is patterned to form certain regions of the layer 160.

After the anti-reflection film forming step (S270), the front electrode forming step (S270) is performed.

In the forming of the front electrode (S270), a conductive material such as aluminum or silver is formed to contact the TCO layer 160, but the front electrode 180 is formed in a patterned form.

The front electrode forming step (S270) may be formed in two ways as in the anti-reflection film forming step (S260).

In the first method, when the anti-reflection film 170 is formed over the entire surface of the TCO layer 160, the front electrode forming paste is applied onto predetermined areas of the anti-reflection film 170, that is, the pattern shape. After coating, the method may be baked to etch the anti-reflection film 170 to form the front electrode 180 in contact with the TCO layer 160.

In this case, the front electrode forming paste includes not only aluminum or silver, which is a material forming the front electrode 280, but also an etching material capable of etching the anti-reflection film 170.

In the second method, when the anti-reflection film 170 is provided on the TCO layer 160 in a patterned form, the front electrode 180 is patterned on the exposed TCO layer 160. It may be a method of depositing. That is, the patterned front electrode 180 may be formed using a pattern mask method or the like.

At this time, the front electrode forming step (S270) is a step of forming the front electrode 180 to a thickness of 0.2 to 1㎛, preferably 0.5㎛.

6 is a flowchart illustrating a method of manufacturing a solar cell according to another embodiment of the present invention.

Referring to Figure 6, the solar cell manufacturing method according to another embodiment of the present invention is a TCO layer forming step (S310), the first ⁺⁺ type polycrystalline silicon layer forming step (S320), the first type silicon nanowire layer The forming step (S330), the intrinsic layer forming step (S340), the second type doping layer forming step (S350) and the back electrode forming step (S360).

The solar cell manufacturing method according to the present embodiment will be described based on the method of manufacturing the solar cell 200 described with reference to FIG. 2.

The TCO layer forming step (S310) is a step of forming the TCO layer 220 on the substrate 210.

First, before forming the TCO layer 220 on the substrate 210, the substrate 210 is cleaned and prepared.

In this case, the method of cleaning the substrate 210 may be the same method as the method of cleaning the substrate 110 described with reference to FIG. 5, and thus a detailed description thereof will be omitted.

In addition, since the TCO layer forming step (S310) may form the TCO layer 220 on the substrate 210 in the same method as the TCO layer forming step (S250) described with reference to FIG. Omit.

After the TCO layer forming step (S310), a first ⁺⁺ type polycrystalline silicon layer forming step (S320) is performed.

First described in the first ⁺⁺ type polysilicon layer forming step (S320), see FIG. 5 by forming a first ⁺⁺ type polycrystalline silicon layer 230 on the TCO layer 220, ^{+ Since the} same method as the ⁺ type polycrystalline silicon layer forming step S220 may be used, a detailed description thereof will be omitted.

After forming the first ⁺⁺ type polycrystalline silicon layer (S320), the forming of the first type silicon nanowire layer (S330) is performed.

In the forming of the first type silicon nanowire layer (S330), the first type silicon nanowire layer is grown from the first ⁺⁺ type polycrystalline silicon layer 230 to form the first type silicon nanowire layer 240. In this step, since the same method as the first type silicon nanowire forming step S220 described with reference to FIG. 5 may be used, a detailed description thereof will be omitted.

The intrinsic layer forming step S340 is performed after the first type silicon nanowire layer forming step S330.

The intrinsic layer forming step (S340) is to form the intrinsic layer 250 to a thickness of 400 to 600nm, preferably 500nm on the substrate on which the first type silicon nanowire layer 240 is grown. Since there may be a difference in the thickness of the intrinsic layer 250 formed with the intrinsic layer forming step S230 described with reference to FIG. 5, other detailed descriptions thereof will be omitted.

After the intrinsic layer forming step S340, the second type doping layer forming step S350 is performed.

The second type doping layer forming step (S350) is a step of forming the second type doping layer 260 on the intrinsic layer 250.

The second type doping layer forming step (S350) is a step of forming the second type doping layer 260 to a thickness of 10 to 15nm, preferably 12nm, the second type described with reference to FIG. There may be a difference in the thickness of the second type doped layer 260 formed from the doping layer forming step (S240), and since the same method may be used, the detailed description thereof will be omitted.

After forming the second type doped layer (S350), the back electrode forming step (S360) is performed.

The back electrode forming step (S360) is a step of forming the back electrode 270 on the second type doped layer 260.

The back electrode forming step (S360) is a step of forming a thickness of 200 to 400 nm, preferably 300 nm, when the back electrode 270 is formed of aluminum.

The back electrode forming step (S360) is a step of forming a back electrode 270 made of a conductive material such as aluminum or silver on the second type doped layer 260 by using a sputtering method or an evaporation method.

7 is a flowchart illustrating a method of manufacturing a solar cell according to still another embodiment of the present invention.

Referring to Figure 7, the solar cell manufacturing method according to another embodiment of the present invention is a TCO layer forming step (S410), the first ⁺⁺ type polycrystalline silicon layer forming step (S422), the first type of silicon nanowires Layer forming step (S424), top cell intrinsic layer forming step (S426), top cell second type doping layer forming step (S428), buffer layer forming step (S430), bottom cell first type doping layer forming step (S442), bottom cell An intrinsic layer forming step (S444), a bottom cell second type doping layer forming step (S446), and a back electrode forming step (S450) are included.

The solar cell manufacturing method according to the present embodiment will be described based on the method of manufacturing the solar cell 300 described with reference to FIG. 3.

The TCO layer forming step (S410) is a step of forming a TCO layer 320 on the substrate 310.

First, before forming the TCO layer 320 on the substrate 310, the substrate 310 is cleaned and prepared.

In this case, the method of cleaning the substrate 310 may be the same as the method of cleaning the substrate 110 described with reference to FIG. 5, and thus a detailed description thereof will be omitted.

In addition, since the TCO layer forming step S410 may form the TCO layer 320 on the substrate 310 in the same manner as the TCO layer forming step S250 described with reference to FIG. Omit.

After the TCO layer forming step (S410), the first ⁺⁺ type polycrystalline silicon layer forming step (S422), the first type silicon nanowire layer forming step (S424), the top cell intrinsic layer forming step (S426) and the top cell second The mold doping layer forming step S428 is performed sequentially.

The first ⁺⁺ type polycrystalline silicon layer forming step (S422), the first type silicon nanowire layer forming step (S424), the top cell intrinsic layer forming step (S426) and the top cell second type doping layer forming step (S428) are The first ⁺⁺ type polycrystalline silicon layer 332 is formed on the TCO layer 320, and the silicon nanowires are grown from the first ⁺⁺ type polycrystalline silicon layer 332, respectively. A layer 334 is formed, a bottom cell intrinsic layer 336 is formed on a substrate on which the first type silicon nanowire layer 334 is formed, and a bottom cell doped layer 338 is formed on the bottom cell intrinsic layer 336. To form the step, the first ⁺⁺ type polycrystalline silicon layer forming step (S210), the first type silicon nanowire layer forming step (S220), the intrinsic layer forming step (S230) and the second described with reference to FIG. Since it can be formed in the same manner as the type doping layer forming step (S240), detailed description thereof will be omitted.

After the top cell second type doping layer forming step S428, the buffer layer forming step S430 is performed.

The buffer layer forming step (S430) is a step of forming a buffer layer 340 to allow tunnel coupling between the top cell 330 formed in the step and the bottom cell 350 to be formed later.

The buffer layer forming step (S430) is a step of forming the buffer layer 340 on the second type doping layer 338 by using a chemical vapor deposition apparatus or a physical vapor deposition apparatus.

After the buffer layer forming step S430, the bottom cell first type doping layer forming step S442 is performed.

The bottom cell first type doping layer forming step (S442) is a step of forming the bottom cell first type doping layer 352 on the buffer layer 340.

The bottom cell first type doping layer forming step (S442) is a step of forming a silicon layer doped with the first type on the buffer layer 340.

In this case, the bottom cell type 1 doping layer 352 may be formed of a first type ⁺ doping layer, and may be formed of a type 1 doping layer having a lower impurity concentration of type 1 than that of the first type ⁺ type doping layer. .

The bottom cell type 1 doping layer forming step (S442) is a step of forming the bottom cell type 1 doping layer 352 by using a chemical vapor deposition apparatus such as a plasma chemical vapor deposition apparatus or a physical vapor deposition apparatus. Can be.

After the bottom cell first type doping layer forming step S442, the bottom cell intrinsic layer forming step S444 is performed.

The bottom cell intrinsic layer forming step (S444) may be performed on the bottom cell intrinsic layer 354 formed of a hydrogenated microcrystalline silicon layer, ie, a μc-Si: H layer, on the bottom cell first type doping layer 352. It is a step of forming to a thickness of 1 to 2㎛.

In the bottom cell intrinsic layer forming step (S444), the bottom cell intrinsic layer 354 formed of the hydrogenated microcrystalline silicon layer may be directly formed using an inductively coupled plasma chemical vapor deposition apparatus, and the first type doping layer ( After forming the hydrogenated amorphous silicon layer on the 352, the crystallization method may be used to form the bottom cell intrinsic layer 354 formed of the hydrogenated microcrystalline silicon layer. In this case, the crystallization may be performed by selecting any one of various methods such as heat treatment crystallization, laser crystallization, and metal catalyst crystallization.

After the bottom cell intrinsic layer forming step S444 is performed, the bottom cell second type doping layer forming step S446 is performed.

The bottom cell second type doping layer forming step (S446) is a step of forming the bottom cell second type doping layer 356 on the bottom cell intrinsic layer 354, and the second type described with reference to FIG. 5. Since it can be formed in the same manner as the doping layer forming step (S230), a detailed description thereof will be omitted.

After forming the bottom cell second type doping layer (S446), the back electrode forming step (S450) is performed.

The back electrode forming step (S450) is a step of forming the back electrode 360 on the bottom cell second type coating layer 356, which is the same as the back electrode forming step S360 described with reference to FIG. 6. Since it can form by a method, detailed description is abbreviate | omitted.

The present invention has been described above with reference to the above embodiments, but the present invention is not limited thereto. It will be apparent to those skilled in the art that modifications and variations may be made without departing from the spirit and scope of the invention, and that such modifications and variations are also contemplated by the present invention.

1 is a cross-sectional view showing a solar cell according to an embodiment of the present invention.

2 is a cross-sectional view showing a solar cell according to another embodiment of the present invention.

3 is a cross-sectional view showing a solar cell according to another embodiment of the present invention.

4 is a flowchart illustrating a method of manufacturing a first type silicon nanowire according to an embodiment of the present invention.

5 is a flowchart illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.

6 is a flowchart illustrating a method of manufacturing a solar cell according to another embodiment of the present invention.

7 is a flowchart illustrating a method of manufacturing a solar cell according to still another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

110,210.310: substrate 120,230,332: first ⁺⁺ type polycrystalline silicon layer

130,240,334: type 1 silicon nanowire layer

Claims (30)

Board; A first ⁺⁺ type polycrystalline silicon layer provided on the substrate; A first type silicon nanowire layer comprising a first type silicon nanowire grown from the first ⁺⁺ type polycrystalline silicon layer; An intrinsic layer provided on the substrate provided with the first type silicon nanowire layer; And And a second type doping layer provided on the intrinsic layer. The method of claim 1, The solar cell: A TCO layer provided on the second type doped layer; An anti-reflection film provided on the TCO layer to expose certain regions of the TCO layer; And And a front electrode provided in a patterned form on certain regions of the exposed TCO layer. The method of claim 1, The solar cell: A TCO layer provided between the substrate and the first ⁺⁺ type polycrystalline silicon layer; And And a back electrode provided on the second type doped layer. The method of claim 1, The intrinsic layer is a top cell intrinsic layer, The second type doped layer is a top cell second type doped layer, The solar cell: A buffer layer provided on the top cell type 2 doping layer; A bottom cell first type doping layer provided on the buffer layer; A bottom cell intrinsic layer provided on the bottom cell first type doping layer; A bottom cell second type doping layer provided on the bottom cell intrinsic layer; And And a back electrode provided on the bottom cell type 2 doping layer. The method of claim 1, The type 1 silicon nanowire has a length of 2 to 5㎛, its diameter is 1 to 5nm solar cell, characterized in that. The first ⁺⁺ type polysilicon layer forming step of forming a first ⁺⁺ type polycrystalline silicon layer on a substrate; A metal thin film layer forming step of forming a metal thin film layer on the first ⁺⁺ type polycrystalline silicon layer; A metal nanoparticle forming step of forming the metal thin film layer using metal nanoparticles; And And growing a first type silicon nanowire from the first ⁺⁺ type polycrystalline silicon layer using the metal nanoparticle as a seed. The method of claim 6, The metal thin film layer forming step is a step of depositing a metal using a sputtering (sputtering method) or evaporation (evaporation method), the step of depositing a silicon nanowire thickness, characterized in that the step of deposition. The method of claim 7, wherein The metal is a method of forming silicon nanowires, characterized in that it comprises any one or more of Au, In, Ga and Sn. The method of claim 6, The metal nanoparticle forming step and the first type of silicon nanowire growth step may use an inductively coupled plasma chemical vapor deposition device or a very high frequency-chemical vapor deposition device. Method of forming silicon nanowires. The method of claim 9, The metal nanoparticle forming step and the first type of silicon nanowire growth step are silicon nanowires forming method characterized in that the continuous progress using an inductively coupled plasma chemical vapor deposition apparatus or ultra-high frequency chemical vapor deposition apparatus. The method of claim 9, The metal nanoparticle forming step is a process temperature of 200 to 400 ℃, a process pressure of 80 to 150mTorr, hydrogen (H ₂ ) gas flow rate of 100 to 300sccm, plasma power of 500 to 700W, susceptor power of 30 to 50W and 30 And forming the metal thin film layer into metal nanoparticles using the inductively coupled plasma chemical vapor deposition apparatus under a process condition including a process time of about 90 minutes. The method of claim 9, The metal nanoparticle forming step may be performed using the ultra-high frequency chemical vapor deposition apparatus under a process condition including a process temperature of 200 to 400 ° C., a process pressure of 0.05 to 0.2 Torr, a plasma power of 40 to 60 W, and a process time of 30 to 60 minutes. Forming the metal thin film layer by using metal nanoparticles. The method of claim 9, The type 1 silicon nanowire growth step includes a process temperature of 200 to 400 ° C., a process pressure of 70 to 80 mTorr, a silane gas ratio of 0.1 to 0.2, a plasma power of 500 to 700 W, a susceptor power of 30 to 50 W, and 1 to 20 Using the inductively coupled plasma chemical vapor deposition apparatus at a process condition including a process time of minutes, The silane gas ratio is a ratio of the silane gas in a mixed gas of silane (SiH ₄ ) gas and hydrogen gas. The method of claim 9, The type 1 silicon nanowire growth step includes a process temperature of 200 to 400 ° C., a process pressure of 0.05 to 0.2 Torr, a silane gas ratio of 0.4 to 0.6, a plasma power of 40 to 60 W, and a processing time of 30 to 60 minutes. Process conditions using the ultra-high frequency chemical vapor deposition apparatus, And the silane gas ratio is a ratio of the silane gas in a mixed gas of silane gas and hydrogen gas. The method of claim 6, The silicon nanowires have a length of 2 to 5㎛, the diameter of 1 to 5nm characterized in that the silicon nanowires forming method. The method of claim 6, After the type 1 silicon nanowire growth step, And removing the remaining metal to remove the metal remaining on the substrate. In the solar cell manufacturing method, The first ⁺⁺ type polysilicon layer forming step of forming a first ⁺⁺ type polycrystalline silicon layer on a substrate; A metal thin film layer forming step of forming a metal thin film layer on the first ⁺⁺ type polycrystalline silicon layer; A metal nanoparticle forming step of forming the metal thin film layer using metal nanoparticles; And And a first type silicon nanowire growth step of growing a first type silicon nanowire from the first ⁺⁺ type polycrystalline silicon layer by using the metal nanoparticle as a seed. The method of claim 17, After the type 1 silicon nanowire growth step, Forming an intrinsic layer on the substrate on which the first type silicon nanowires are grown; A second type doping layer forming step of forming a second type doping layer on the intrinsic layer; Forming a TCO layer on the second type doped layer; An anti-reflection film forming step of forming an anti-reflection film on the TCO layer; And Forming a front electrode on the anti-reflection film; forming a front electrode; solar cell manufacturing method comprising a. The method of claim 17, Before forming the first ⁺⁺ type polycrystalline silicon layer, And a TCO layer forming step of forming a TCO layer on the substrate. After the type 1 silicon nanowire growth step, Forming an intrinsic layer on the substrate on which the first type silicon nanowires are grown; A second type doping layer forming step of forming a second type doping layer on the intrinsic layer; And And a back electrode forming step of forming a back electrode on the second type doped layer. The method of claim 17, Before forming the first ⁺⁺ type polycrystalline silicon layer, And a TCO layer forming step of forming a TCO layer on the substrate. After the type 1 silicon nanowire growth step, Forming a top cell intrinsic layer on the substrate on which the first type silicon nanowires are grown; Forming a top cell second type doping layer to form a top cell second type doping layer on the top cell intrinsic layer; A buffer layer forming step of forming a buffer layer on the top cell type 2 doped layer; A bottom cell first type doping layer forming step of forming a bottom cell first type doping layer on the buffer layer; A bottom cell intrinsic layer forming step of forming a bottom cell intrinsic layer on the bottom cell first type doping layer; Forming a bottom cell second type doping layer on the bottom cell intrinsic layer; And And a back electrode forming step of forming a back electrode on the bottom cell type 2 doped layer. The method of claim 17, The metal thin film layer forming step is a step of depositing a metal using a sputtering method or evaporation method, the solar cell manufacturing method characterized in that the step of depositing to a thickness of 100 to 150nm. The method of claim 21, The metal is a solar cell manufacturing method comprising at least one of Au, In, Ga and Sn. The method of claim 17, The metal nanoparticle forming step and the first type of silicon nanowire growth step are a solar cell manufacturing method characterized in that using an inductively coupled plasma chemical vapor deposition apparatus or ultra-high frequency chemical vapor deposition apparatus. The method of claim 23, wherein The metal nanoparticle forming step and the first type of silicon nanowire growth step is a solar cell manufacturing method characterized in that proceeds continuously. The method of claim 23, wherein The metal nanoparticle forming step is a process temperature of 200 to 400 ℃, process pressure of 80 to 150 mTorr, hydrogen gas flow rate of 100 to 300 sccm, plasma power of 500 to 700 W, susceptor power of 30 to 50 W and 30 to 90 minutes And forming the metal thin film layer into metal nanoparticles using the inductively coupled plasma chemical vapor deposition apparatus under a process condition including a process time. The method of claim 23, wherein The metal nanoparticle forming step may be performed using the ultra-high frequency chemical vapor deposition apparatus under a process condition including a process temperature of 200 to 400 ° C., a process pressure of 0.05 to 0.2 Torr, a plasma power of 40 to 60 W, and a process time of 30 to 60 minutes. Forming a metal thin layer by using metal nanoparticles. The method of claim 23, wherein The type 1 silicon nanowire growth step includes a process temperature of 200 to 400 ° C., a process pressure of 70 to 80 mTorr, a silane gas ratio of 0.1 to 0.2, a plasma power of 500 to 700 W, a susceptor power of 30 to 50 W, and 1 to 20 Using the inductively coupled plasma chemical vapor deposition apparatus at a process condition including a process time of minutes, The silane gas ratio is a ratio of the silane gas in a mixed gas of silane gas and hydrogen gas. The method of claim 23, wherein The type 1 silicon nanowire growth step includes a process temperature of 200 to 400 ° C., a process pressure of 0.05 to 0.2 Torr, a silane gas ratio of 0.4 to 0.6, a plasma power of 40 to 60 W, and a processing time of 30 to 60 minutes. Process conditions using the ultra-high frequency chemical vapor deposition apparatus, The silane gas ratio is a ratio of the silane gas in a mixed gas of silane gas and hydrogen gas. The method of claim 17, The type 1 silicon nanowire has a length of 2 to 5㎛, the diameter of the solar cell manufacturing method, characterized in that 1 to 5nm. The method of claim 17, After the type 1 silicon nanowire growth step, Residual metal removal step of removing the metal remaining on the substrate; solar cell manufacturing method comprising a.

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