KR101064286B1 - Manufacturing Method of Semiconductor Device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein in a MPDL device of a system on chip (SOC) device, a gate for a DRAM cell transistor is formed in a multilayer structure of a first gate / dielectric film / second gate. The logic transistor gate is formed in a multi-layered structure of the first gate and the second gate, and the gate oxide film for the DRAM cell transistor is simultaneously formed when the gate oxide film for the logic transistor is formed. Therefore, the logic transistor can maintain a low threshold voltage by using a thin gate oxide film as it is and obtain a high operating speed. The DRAM cell transistor has a high structure due to the stacked structure of the first gate / dielectric film / second gate on the thin gate oxide film. By maintaining the threshold voltage, the off-leakage current can be reduced, reducing the process time and improving process control with a single gate oxidation process. In addition, according to the present invention, the dielectric film for the DRAM cell capacitor may be formed of a material having a high dielectric constant, so that the capacitor capacity may be increased.

Plannar DRAM, SOC, MPDL

Description

Method of manufacturing semiconductor device             

1A to 1E are cross-sectional views of a device for explaining a method of manufacturing a conventional semiconductor device; And

2A to 2D are cross-sectional views of devices for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

11: semiconductor substrate 11C: bottom electrode for DRAM cell capacitor

12: device isolation film 13: first oxide film

13D: gate oxide film for DRAM cell transistor

14: first photoresist pattern 15: second oxide film

15L: gate oxide for logic transistor

15C: DRAM Cell Capacitor Dielectric Film 16: Polysilicon Layer

16L: gate for logic transistor 16D: gate for DRAM cell transistor

16C: top electrode for DRAM cell capacitor 17: second photoresist pattern

18: insulating film spacer 19L: source / drain for logic transistor                 

19D: Source / drain 21 for DRAM cell transistor: semiconductor substrate

21C: bottom electrode for DRAM cell capacitor 22: device isolation film

23: oxide film 23L: gate oxide film for logic transistor

23D: gate oxide film for DRAM cell transistor

24: polysilicon layer 24L: first gate for logic transistor

24D: first gate 25 for DRAM cell transistor 25: first photoresist pattern

26: dielectric film 26D: dielectric film for DRAM cell transistor

26C: dielectric film for DRAM cell capacitor 27: second photoresist pattern

28: conductive layer 28L: second gate for logic transistor

28D: second gate for DRAM cell transistor

28C: top electrode for DRAM cell capacitor 29: third photoresist pattern

30: insulating film spacer 31L: source / drain for logic transistor

31D: Source / drain for DRAM cell transistor

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a merged planar DRAM and logic (MPDL) device.

In general, a system module of an electronic product is composed of several packaged chips having respective functions integrated on a board. Currently, system on chip (SOC) products, which are designed by integrating several chips of each function into one chip, are being actively developed. Especially, a product that combines memory and logic into a single chip is produced and developed. This is becoming a lot. One such SOC family, MDL (Merged DRAM and Logic) products, is designed to have special features, but the development process is challenging due to differences in DRAM and logic processes. MPDL products using logic processes have been developed and used to reduce these process differences and to take advantage of the fast operation speed of logic devices. In this case, gate oxides are used to reduce the off leakage current of DRAM cells. By using a thicker thickness of the to have a high threshold voltage, logic is made to increase the operating speed of the device by increasing the saturation current by lowering the threshold voltage by thinning the gate oxide film.

1A to 1E are cross-sectional views of a device for explaining a method of manufacturing a conventional semiconductor device.

Referring to FIG. 1A, a device isolation layer 12 is formed on a semiconductor substrate 11 in which a logic transistor region and a DRAM cell region are defined using a common device isolation method such as a trench isolation (STI). The DRAM cell region is divided into a transistor region and a capacitor region. A thick oxide first oxide film 13 is formed on the surface of the semiconductor substrate 11 on which the device isolation film 12 is formed to form a gate oxide film of a DRAM cell transistor. The first photoresist pattern 14 is formed on the first oxide layer 13 to close the DRAM cell transistor region.

Referring to FIG. 1B, an exposed portion of the first oxide layer 13 is etched using an etching process using the first photoresist pattern 14 as an etching mask to leave the first oxide layer 13 only in the DRAM cell transistor region. Thereafter, the first photoresist pattern 14 is removed.

Referring to FIG. 1C, an oxide process for forming a gate oxide film of a logic transistor and a dielectric film of a DRAM cell capacitor is performed to transfer a thin second oxide film 15 to a semiconductor substrate 11 in a logic transistor region and a DRAM cell capacitor region. To form. At this time, the second oxide film 15 is formed on the first oxide film 13 to a thickness of several tens of microwatts to determine the final thickness of the gate oxide film for the DRAM cell transistor in the DRAM cell transistor region.

Referring to FIG. 1D, the polysilicon layer 16 is formed on the entire structure in which the first and second oxide films 13 and 15 are formed. On the polysilicon layer 16, a second photoresist pattern 17 is formed on which the gate of the logic transistor, the gate of the DRAM cell transistor, and the top electrode of the DRAM cell capacitor are formed.

Referring to FIG. 1E, the polysilicon layer 16 and the oxide layers 13 and 15 are etched by the etching process using the second photoresist pattern 17 as an etch mask, and the second photoresist pattern 17 is removed. The insulating film spacers 18 are formed, and source / drain ion implantation processes are performed to form source / drain 19L and 19D for logic transistors and DRAM cell transistors. As a result of this process, the gate oxide film 15L for the logic transistor as the second oxide film 15 is formed on the semiconductor substrate 11 in the logic transistor region, and the logic as the polysilicon layer 16 on the gate oxide film 15L. A logic transistor is composed of a transistor gate 16L and a logic transistor source / drain 19L formed on both semiconductor substrates 11 of the gate 16L. On the semiconductor substrate 11 in the DRAM cell transistor region, the gate oxide film 13D for the DRAM cell transistor made of the first oxide film 13 and the DRAM cell transistor made of the polysilicon layer 16 on the gate oxide film 13D. A DRAM cell transistor comprising a gate 16D and a source / drain 19D for DRAM cell transistors formed on both semiconductor substrates 11 of the gate 16D is configured. On the semiconductor substrate 11 in the DRAM cell capacitor region, a DRAM cell capacitor dielectric film 15C made of the second oxide film 13 and a DRAM cell capacitor made of the polysilicon layer 16 on the dielectric film 15C. The DRAM cell capacitor including the top electrode 16C and the bottom electrode 11C for the DRAM cell capacitor formed of the semiconductor substrate 11 below the top electrode 16C is configured.

Thereafter, the MPDL device is manufactured through an interlayer insulating film forming process, a contact process, and a wiring process.

In the conventional method, since the oxidation process is performed twice to form dual gate oxide films having different thicknesses, the process time is long, and a photo process and an etching process for forming the dual gate oxide film are added, thereby reducing device characteristics. In addition, since the same material as the gate oxide film, such as a thermal oxide film, is used as the capacitor dielectric film, it is difficult to secure the capacitor capacity.

Therefore, the present invention can reduce the process time and improve the process control ability by forming the gate oxide films of the logic transistor and the DRAM cell transistor in a single gate oxidation process in the MPLD device. It is an object of the present invention to provide a method for manufacturing a semiconductor device which can be formed of a material having an increase in the capacitor capacity.

According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, including forming an oxide film and a polysilicon layer on a semiconductor substrate on which a logic transistor region, a DRAM cell transistor region, and a DRAM cell capacitor region are defined; Removing the polysilicon layer and the oxide film in the DRAM cell capacitor region, and then forming a dielectric film on an entire structure; Removing the dielectric film in the logic transistor region, and then forming a conductive layer over the entire structure; And etching a portion of the conductive layer, the dielectric layer, the polysilicon layer, and the oxide layer, and then performing a source / drain ion implantation process to form a logic transistor, a DRAM cell transistor, and a DRAM cell capacitor, respectively. do.

In the above, the oxide film is formed to a thickness of 20 to 50 kPa by a dry or wet oxidation process.                     

The polysilicon layer is formed by doping phosphorus (P) of 1E18 / cm ³ to 1E22 / cm ³ to a thickness of 300 to 1500 Å is deposited as undoped or soft type (undoped).

The dielectric film is formed to a thickness of 50 to 300 kW using at least one of Si ₃ N ₄ , Al ₂ O ₅ , HfO ₂ , ZrO ₂ , TiO ₂ and BST.

The conductive layer uses one conductive material selected from the group consisting of Poly-Si, Al, W, Ta, Mo, Ti, Ir, Pt, Ru, Ag, Os and Re, or a mixture thereof or an alloy thereof. To form a thickness of 500 to 2000 mm 3.

The logic transistor may include: a gate oxide film for a logic transistor formed of the oxide film on the semiconductor substrate; A first gate for a logic transistor comprising the polysilicon layer on the gate oxide film for the logic transistor; A second gate for a logic transistor as the conductive layer on the first gate for the logic transistor; And a source / drain for a logic transistor formed in the semiconductor substrate by the source / drain ion implantation process.

The DRAM cell transistor may include a gate oxide film for a DRAM cell transistor including the oxide film on the semiconductor substrate; A first gate for a DRAM cell transistor comprising the polysilicon layer on the gate oxide film for the DRAM cell transistor; A dielectric film for a DRAM cell transistor formed of the dielectric film on the first gate for the DRAM cell transistor; A second gate for a DRAM cell transistor comprising the conductive layer on the DRAM cell transistor dielectric film; And a source / drain for a DRAM cell transistor formed on the semiconductor substrate by the source / drain ion implantation process.

The DRAM cell capacitor may include a dielectric film for a DRAM cell capacitor including the dielectric film on the semiconductor substrate; A top electrode for a DRAM cell capacitor as the conductive layer on the DRAM cell capacitor dielectric film; And a bottom electrode for the DRAM cell capacitor formed of the semiconductor substrate under the top electrode for the DRAM cell capacitor.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only the present embodiment is provided to make the disclosure of the present invention complete, and to fully convey the scope of the invention to those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

2A to 2D are cross-sectional views of devices for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 2A, a device isolation layer 22 is formed on a semiconductor substrate 21 in which a logic transistor region and a DRAM cell region are defined using a conventional device isolation method such as trench isolation (STI) to manufacture an MPDL device. do. The DRAM cell region is divided into a transistor region and a capacitor region. In order to have a low threshold voltage of the logic transistor, an oxide layer 33 having a thin thickness is formed on the surface of the semiconductor substrate 21 on which the device isolation layer 22 is formed. The polysilicon layer 24 is formed on the oxide film 33. A first photoresist pattern 25 is formed on the polysilicon layer 24 with the DRAM cell capacitor region open.

In the above, the oxide film 33 is formed in a thin thickness of 20 to 50 kPa by a dry or wet oxidation process, and the thin film oxide 33 is used only as a gate oxide film of a logic transistor in the conventional process. Is also used as a gate oxide film of a DRAM cell transistor that requires a high threshold voltage. In order to have a high threshold voltage, a thick oxide film is required, but the gate oxide film of the DRAM cell transistor of the present invention is also applicable to the thin oxide film 33 used as the gate oxide film of the logic transistor, which will be described later. . Polysilicon layer 24, phosphorus (P) of a thickness of is used as a logic transistor and a DRAM lower layer of the cell transistor, each of the gate be formed through a subsequent process, from 300 to 1500 Å 1E18 / cm ³ to 1E22 / cm ³ is Formed by vapor deposition in doped or undoped form. The polysilicon layer 24 as the lower layer of the gate of the DRAM cell transistor serves to have the high threshold voltage of the DRAM cell transistor together with the oxide film 33.

Referring to FIG. 2B, a portion of the semiconductor substrate 21 is exposed by removing the polysilicon layer 24 and the oxide layer 23 of the DRAM cell capacitor region by an etching process using the first photoresist pattern 25 as an etching mask. Let's do it. The first photoresist pattern 25 is removed and a dielectric film 26 is formed over the entire structure including the exposed semiconductor substrate 21 and the patterned polysilicon layer 24. A second photoresist pattern 27 having an open logic transistor region is formed on the dielectric film 26.

In the above, the dielectric film 26 is a dielectric having a high dielectric constant (high-k), for example, Si ₃ N ₄ , Al ₂ O ₅ , HfO to increase the capacitance of the capacitor to be formed through subsequent processes ₂ , ZrO ₂ , TiO ₂ , or at least one of BST to form a thickness of 50 to 300 kPa. The dielectric layer 26 is used for a DRAM cell capacitor and serves to have a high threshold voltage of the DRAM cell transistor.

Referring to FIG. 2C, a portion of the polysilicon layer 24 is exposed by removing the dielectric layer 26 in the logic transistor region by an etching process using the second photoresist pattern 27 as an etching mask. A conductive layer 28 is formed over the entire structure, including the exposed polysilicon layer 24 and the patterned dielectric film 26. A third photoresist pattern 29 is disposed on the conductive layer 28, each of which covers a portion where a gate of the logic transistor is to be formed, a portion where a gate of the DRAM cell transistor is to be formed, and a portion where the top electrode of the DRAM cell capacitor is to be formed. To form.

In the above, the conductive layer 28 is one conductive material selected from the group consisting of Poly-Si, Al, W, Ta, Mo, Ti, Ir, Pt, Ru, Ag, Os and Re or a mixture thereof or It forms with these alloys. The conductive layer 28 is used as the upper layer of the gate of each of the logic transistor and DRAM cell transistor to be formed through a subsequent process, and is deposited to a thickness of 500 to 2000 kHz.                     

Referring to FIG. 2D, the conductive layer 28, the dielectric layer 26, the polysilicon layer 24, and the oxide layer 23 are sequentially etched by an etching process using the third photoresist pattern 29 as an etching mask. The third photoresist pattern 29 is removed. An insulating layer spacer 30 is formed on sidewalls of each of the patterns formed by the etching process, and a source / drain ion implantation process is performed to form source / drains 31L and 31D for logic transistors and DRAM cell transistors.

As a result of the above process, the gate oxide film 23L for the logic transistor made of the oxide film 23 is formed on the semiconductor substrate 21 in the logic transistor region, and the logic transistor for the logic transistor made of the polysilicon layer 24 is formed on the gate oxide film 23L. The first gate 24L, the second gate 28L for the logic transistor including the conductive layer 28 on the first gate 24L, the gate oxide film 23L, the first gate 24L, and the second gate A logic transistor composed of a logic transistor source / drain 31L formed on both semiconductor substrates 21 having a stacked structure of 28L is formed. On the semiconductor substrate 21 in the DRAM cell transistor region, the gate oxide film 23D for the DRAM cell transistor made of the oxide film 23 and the first gate for the DRAM cell transistor made of the polysilicon layer 24 on the gate oxide film 23D. A DRAM cell transistor dielectric film 26D formed of a dielectric film 26 on the first gate 24D, and a DRAM cell transistor made of a conductive layer 28 on the dielectric film 26D. Source for DRAM cell transistor formed on both semiconductor substrates 21 having a structure in which two gates 28D, a gate oxide film 23D, a first gate 24D, a dielectric film 26D, and a second gate 28D are stacked. A DRAM cell transistor made of / drain 31D is configured. On the semiconductor substrate 21 in the DRAM cell capacitor region, a DRAM cell capacitor dielectric film 26C made of a dielectric film 26 and a DRAM cell capacitor top made of a conductive layer 28 on the dielectric film 26C. The DRAM cell capacitor including the electrode 28C and the bottom electrode 21C for the DRAM cell capacitor formed of the semiconductor substrate 21 below the top electrode 28C is configured.

Thereafter, the MPDL device is manufactured through an interlayer insulating film forming process, a contact process, and a wiring process.

In the present invention described above, the logic transistor has a low threshold voltage due to the thin gate oxide film 23L having a thickness of 20 to 50 kV, and the DRAM cell transistor has a logic gate instead of the thick gate oxide film. A gate oxide film 23D having the same thickness as that of the gate oxide film 23L is applied, but the first gate 24D, which is electrically floating, is formed between the gate oxide film 23D and the dielectric film 26D so that the second gate ( When the voltage is applied to 28D), a high threshold voltage is obtained. In addition, the DRAM cell capacitor can form the dielectric film 26C with a dielectric having a high dielectric constant (high-k) without forming a dielectric film of the same material as the gate oxide film, which is advantageous for securing the capacitance of the capacitor.

As described above, according to the present invention, in an MPDL device of a system on chip (SOC) device, a logic transistor can obtain a fast operation speed by maintaining a low threshold voltage using a thin gate oxide film as it is, and a DRAM cell. The transistor can reduce off-leakage current by maintaining a high threshold voltage due to a stacked structure of a gate oxide film, a first gate, a dielectric film, and a second gate on a thin gate oxide film. The control capability can be improved, and the dielectric film for the DRAM cell capacitor can be formed of a dielectric having a high dielectric constant value, thereby increasing the capacitor capacity. In addition, a metal material having excellent conductivity may be introduced into the gate structure, thereby improving electrical characteristics of the gate.

Claims (8)

Forming an oxide film and a polysilicon layer on a semiconductor substrate on which a logic transistor region, a DRAM cell transistor region, and a DRAM cell capacitor region are defined; Removing the polysilicon layer and the oxide layer of the DRAM cell capacitor region, and then forming a dielectric film on the entire structure including the logic transistor region and the DRAM cell capacitor region; Removing the dielectric layer of the logic transistor region, and then forming a conductive layer on the entire structure including the logic transistor region and the DRAM cell capacitor region; And Etching a portion of the conductive layer, the dielectric layer, the polysilicon layer, and the oxide layer, and then performing a source / drain ion implantation process to form a logic transistor, a DRAM cell transistor, and a DRAM cell capacitor, respectively. Method of manufacturing a semiconductor device. The method of claim 1, The oxide film is a method of manufacturing a semiconductor device to form a thickness of 20 to 50 kPa by a dry or wet oxidation process. The method of claim 1, The polysilicon layer is a method of manufacturing a semiconductor device formed by depositing a phosphorus (P) of 1E18 / cm ³ to 1E22 / cm ³ doped or undoped to a thickness of 300 to 1500 Å. The method of claim 1, The dielectric film is a method of manufacturing a semiconductor device to form a thickness of 50 to 300 kHz using at least any one of Si ₃ N ₄ , Al ₂ O ₅ , HfO ₂ , ZrO ₂ , TiO ₂ and BST. The method of claim 1, The conductive layer uses one conductive material selected from the group consisting of Poly-Si, Al, W, Ta, Mo, Ti, Ir, Pt, Ru, Ag, Os and Re, or a mixture thereof or an alloy thereof. To form a thickness of 500 to 2000 GPa. The method of claim 1, The logic transistor, A gate oxide film for a logic transistor comprising the oxide film on the semiconductor substrate; A first gate for a logic transistor comprising the polysilicon layer on the gate oxide film for the logic transistor; A second gate for a logic transistor as the conductive layer on the first gate for the logic transistor; And A method for manufacturing a semiconductor device comprising a source / drain for a logic transistor formed on the semiconductor substrate by the source / drain ion implantation process. The method of claim 1, The DRAM cell transistor, A gate oxide film for a DRAM cell transistor including the oxide film on the semiconductor substrate; A first gate for a DRAM cell transistor comprising the polysilicon layer on the gate oxide film for the DRAM cell transistor; A dielectric film for a DRAM cell transistor formed of the dielectric film on the first gate for the DRAM cell transistor; A second gate for a DRAM cell transistor comprising the conductive layer on the DRAM cell transistor dielectric film; And A method of manufacturing a semiconductor device comprising a source / drain for a DRAM cell transistor formed on the semiconductor substrate by the source / drain ion implantation process. The method of claim 1, The DRAM cell capacitor, A dielectric film for a DRAM cell capacitor comprising the dielectric film on the semiconductor substrate; A top electrode for a DRAM cell capacitor as the conductive layer on the DRAM cell capacitor dielectric film; And A semiconductor device manufacturing method comprising a bottom electrode for a DRAM cell capacitor made of the semiconductor substrate below the top electrode for a DRAM cell capacitor.

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