KR101046922B1 - Thin film transistor array panel and liquid crystal display including the same - Google Patents

Abstract

A liquid crystal display device according to an embodiment of the present invention includes a gate line having a gate electrode, a storage electrode overlapping a pixel electrode thereafter to form a storage capacitor, a gate insulating film formed over the gate line, and a semiconductor formed over the gate insulating film. And a data line orthogonal to the gate line, a drain electrode facing the source electrode on the gate electrode, a protective film made of an organic insulating material covering the semiconductor layer, and electrically connected to the drain electrode. Covering the pixel electrode and the data line formed in duplicate, each adjacent pixel electrode completely covers one data line formed in double, so that the difference in parasitic capacitance between the pixel electrode and the data line is affected by misalignment between the layers of the process. Thin film transistor substrate and pixel It is a liquid crystal display device which has a board | substrate with which the counter electrode which forms a liquid crystal capacitance is formed facing a pole.

Common voltage, pixel electrode, counter electrode, parasitic capacitance, data line, organic insulating material

Description

Thin film transistor array panel and liquid crystal display including the same {THIN FILM TRANSISTOR PANEL AND LIQUID CRYSTAL DISPLAY INCLUDING THE PANEL}

1 is a layout view of a thin film transistor array panel for a liquid crystal display according to a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line II-II ′ of FIG. 1, illustrating a liquid crystal display device in which the thin film transistor array panel and the opposing display panel illustrated in FIG. 1 are assembled;

FIG. 3 is a cross-sectional view taken along line III-III ′ of FIG. 1 illustrating a liquid crystal display in a state in which the thin film transistor array panel and the opposing display panel illustrated in FIG. 1 are assembled;

4 is a layout view of a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention.

FIG. 5 is a cross-sectional view of the liquid crystal display of FIG. 4 taken along the line V-V ″ of FIG. 4 in a state where the thin film transistor array panel and the opposing display panel are assembled;

6 is a cross-sectional view taken along line VI-VI ′ of the liquid crystal display in a state in which the thin film transistor array panel and the opposing substrate of FIG. 4 are assembled.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array panel and a liquid crystal display device including the same, and more particularly, to a liquid crystal display device having a high opening ratio.

A liquid crystal display generally includes an upper panel on which counter electrodes are formed, a lower panel on which thin film transistors, pixel electrodes, and the like are formed, and a liquid crystal layer formed therebetween, and different potentials are applied to the pixel electrode and the counter electrode. By applying to form an electric field to change the arrangement of the liquid crystal molecules, and through this to adjust the transmittance of light to express the image.

In such a general liquid crystal display device, securing the aperture ratio of pixels increases the luminance of the screen and has many effects. To this end, the pixel electrode and the data line are disposed to overlap each other. Thus, parasitic capacitance is formed between the pixel electrode to which the pixel voltage is applied and the data line to which the continuously varying data voltage is transmitted. Occurs. As an example, when using an exposure mask smaller than an active area in which a pixel electrode of a display panel is positioned in a photolithography process of a liquid crystal display device, the display panel is divided into several blocks to perform an exposure process. The distance between the pixel electrode and the data line may vary slightly for each block according to the degree of. As a result, the parasitic capacitance generated between the pixel electrode and the data line may vary depending on the block, and thus stitch failure may occur.

SUMMARY OF THE INVENTION The present invention provides a thin film transistor array panel having a uniform parasitic capacitance generated between a pixel electrode and a data line, and a liquid crystal display including the same.

The thin film transistor array panel for achieving the above object of the present invention comprises a plurality of gate lines for transmitting a scan signal; A plurality of data lines intersecting the gate lines and transferring image signals, each of the first and second sub data lines electrically connected to and separated from each other; A plurality of pixel electrodes electrically connected to the gate line, the data line, and the thin film transistor and covering both edges of an adjacent first sub data line or a second sub data line; A passivation film formed between the data line and the pixel electrode; And a light blocking member forming the same layer as the gate line and covering the first sub data line and the second sub data line.

 In addition, another liquid crystal display device for achieving the above object of the present invention, a plurality of gate lines for transmitting a scan signal; A plurality of data lines intersecting the gate line and transferring an image signal, each of the first and second sub data lines electrically connected to and spaced apart from each other, and electrically through the gate line and the data line and the thin film transistor. A plurality of pixel electrodes connected to and covering both edges of the adjacent first sub data line or the second sub data line; A thin film transistor array panel including a color filter layer formed between the data line and the pixel electrode; And a light blocking member formed in the same layer as the gate line and stacked with the divided data line.                     

      In this way, each data line is formed as a pair of sub data lines parallel to each other, and pixel electrodes positioned on both sides of each sub data line overlap with adjacent sub data lines, and the light blocking member covers the gap between the data line and the pixel electrode. It is possible to minimize the parasitic capacitance generated at and to maximize the aperture ratio.

The present invention has various embodiments according to the position of a data line composed of a pair of sub data lines, a pixel electrode overlapping the sub data lines, and a light blocking member covering the sub data lines.

In the thin film transistor array panel according to the exemplary embodiment of the present invention, data includes a gate line transmitting a scan signal, a pair of sub data lines intersecting the gate line, transmitting an image signal, and at least a distance from each other around the pixel electrode. A thin film transistor including a line, a pixel electrode disposed in the pixel region defined by the gate line and the data line, and a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode. It is.

The thin film transistor array panel further includes an insulating film covering the thin film transistor, the gate line, and the data line, and the pixel electrode is preferably formed on the insulating film, and the insulating film may be formed of an organic insulating material or a color filter, It may further include a storage electrode overlapping to form a storage capacitor.

The data line is arranged in parallel in parallel with the length of the pixel and has a curved portion that appears linearly or repeatedly and intersects with the gate line. The curved portion of the data line includes at least two straight portions, and the straight portion includes a gate. It is preferable that the angle is substantially ± 45 degrees with respect to the line, and the pixel electrode is preferably patterned along the curved shape of the data line in the pixel. Here, the pixel electrode covers both edges of adjacent sub data lines, and the light blocking member is electrically insulated from the data lines and is made of a metallic material, in particular at least between each pair of sub data lines, the outer edge of which is the sub data. It is desirable not to cross the outer edge of the line.

The liquid crystal display device including the thin film transistor array panel further includes an opposing display panel facing the thin film transistor array panel and having a counter electrode facing the pixel electrode, and a liquid crystal layer formed between the thin film transistor array panel and the opposing display panel.

In this case, the liquid crystal layer may be any of a variety of types, but the embodiment has been described with reference to the TN mode, but can also be said to be the case of the vertical alignment mode. In the vertical alignment mode liquid crystal display, the liquid crystal layer has negative dielectric anisotropy and the long axis of the liquid crystal molecules is vertically aligned with respect to the surfaces of the two display panels. In the case of the liquid crystal display of the vertical alignment mode, cutouts or protrusions may be provided at the counter electrode and the pixel electrode to contribute to the improvement of the so-called viewing angle by changing the direction in which the liquid crystal molecules lie when the electric field is applied to the liquid crystal layer.

The thin film transistor array panel further includes a semiconductor layer formed between the gate electrode and the source and drain electrodes, and may have an island shape, but in some cases, may extend to a lower portion of the data line, and may include a channel between the source electrode and the drain electrode. The semiconductor layer except for the portion may have the same planar shape as the data line and the drain electrode.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Next, a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a layout view of a thin film transistor array panel for a liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 2 illustrates a liquid crystal display in a state in which the thin film transistor array panel and the opposing display panel illustrated in FIG. 1 are assembled. 3 is a cross-sectional view taken along line II ′, and FIG. 3 is a cross-sectional view taken along line III-III ′ of FIG. 1 in a state in which the thin film transistor array panel and the opposing substrate shown in FIG. 1 are assembled.

As shown in FIGS. 2 and 3, the liquid crystal display according to the present exemplary embodiment includes the thin film transistor array panel 100 and the opposing display panel 200 facing each other and the liquid crystal layer 300 disposed therebetween. 330. An anisotropic conductive film for attaching the substrate 430, such as a flexible printed circuit film, on which the signal line 420 is formed, and the substrate 430 to the display panel 100 may be formed on the thin film transistor array panel 100. 410 is provided.

First, referring to the thin film transistor substrate 100, as illustrated in FIG. 1, a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), may be formed on an insulating substrate 110 made of a transparent insulating material such as glass. A plurality of pixel electrodes 190 made of a material, a plurality of thin film transistors connected to the pixel electrode 190, and a plurality of gate lines 121 connected to the thin film transistors to transmit scan signals and an image signal. A plurality of data lines 171 formed of a pair of sub data lines 171a and 171b are formed. The thin film transistor is turned on or off according to the scan signal to selectively transfer the image signal to the pixel electrode 190. In this case, an area in which the plurality of pixel electrodes 190 is located is called an active area (or a screen area) and an outside thereof is called a peripheral area.

The thin film transistor array panel 100 will be described in detail.

A plurality of gate lines 121 and a plurality of storage electrode lines 131 extending mainly in the horizontal direction are formed on the transparent insulating substrate 110, and a plurality of light blocking members 160 extending mainly in the vertical direction are formed. have.

The gate line 121 transmits a gate signal, and a portion of each gate line 121 protrudes to form a plurality of protrusion electrode gate electrodes 124. The gate line 121 has a gate pad 129 for receiving a gate signal from the outside. Alternatively, the end portion of the gate line 121 may be connected to the output terminal of the gate driving circuit formed directly on the substrate 110.

The storage electrode line 131 includes a storage electrode 135 having an extended width.

The light blocking layer 160 is electrically separated from the gate line 121 and the storage electrode line 131.

In order to transfer the common voltage to the counter display panel 200, a counter electrode application wiring (not shown) may be formed on the same layer as the gate line 121.

The gate line 121 and the storage electrode line 131 are made of metal such as Al, Al alloy, Ag, Ag alloy, Cu, Cr, Ti, Ta, Mo, or the like. The gate line 121 and the storage electrode line 131 of the present embodiment are formed of a single layer, but have a high resistivity metals layer of Cr, Mo, Ti, Ta, etc., and an Al-based or Ag having a low specific resistance. It may be made of a double layer including a series of metal layers. In particular, in the case of containing aluminum, a double layer or more should be used to avoid contact with the pixel electrode material. In addition, the gate line 121 and the storage electrode line 131 may be made of various metals or conductors.

The side surface of the metal layer pattern formed on the same layer as the gate line such as the gate line 121 and the storage electrode line 131 is inclined, and the inclination angle with respect to the horizontal plane is preferably about 30-80 °.

A gate insulating layer 140 made of silicon nitride (SiNx) or the like is formed on the gate line 121 and the storage electrode line 131.                     

A plurality of data lines 171, a plurality of drain electrodes 175, and a storage electrode line connection part 176 are formed on the gate insulating layer 140.

The drain electrode 175 extends to overlap the storage electrode 135 in the middle of the storage electrode line 131. Since at least a dielectric layer including the gate insulating layer 140 is interposed between the drain electrode 175 and the storage electrode line 131, a storage capacitance can be secured therebetween.

Each data line 171 mainly extends in the vertical direction, and has a source electrode 173 formed with a plurality of branches toward each drain electrode 175. The data line 171 also includes a contact portion 179 located at one end, and the contact portion 179 receives an image signal from the outside. Here, each data line 171 includes a pair of sub data lines 171a and 171b electrically connected to each other in the active region. Each pair of sub data lines 171a and 171b are connected through a plurality of connection parts 178 in the active area, and are joined to each other in the peripheral area to form one contact part 179. The space between the sub data lines 171a and 171b is covered by the light blocking member 160. In the active region, the light blocking member 160 has an outer edge of the sub data lines 171a and 171b to prevent the decrease of the aperture ratio. Do not exceed. As described above, since the light blocking member 160 is in an electrically floating state, parasitic capacitance is hardly formed between the sub data lines 171a and 171b and the light blocking member 160.

The storage electrode line connection part 176 is positioned outside the active area and mainly extends in the vertical direction to intersect the gate line 121 at a portion adjacent to the gate pad 129. The storage electrode line connecting portion 176 is also adjacent to the end of the storage electrode line 131 and, as will be described later, will be connected to all the storage electrode lines 131 so as to be connected to the storage electrode line 131 at a constant voltage, for example, an opposing display panel. The common voltage supplied to the 200 is supplied. When there is no gate pad part 129, the pattern of the storage electrode line 131 may be integrally connected (not shown).

The data line 171, the drain electrode 175, and the storage electrode line connecting portion 176 are also made of a material such as chromium, molybdenum, and aluminum, and may be made of a single layer as shown in FIGS. 2 and 3, but may be made of multiple layers. Can be. A typical example of the multilayer is a Mo / Al / Mo triple layer. In this case, a low-resistance metal layer such as aluminum is placed in the center, and a refractory metal such as molybdenum is placed on the upper and lower sides thereof.

An island-like semiconductor 154 is formed under the source electrode 173, the drain electrode 175, and a portion therebetween. 1 shows that the width of the semiconductor 154 is slightly wider than the width of the source electrode 173 and the drain electrode 175, but may be narrower. An island-like semiconductor 152 is formed at the intersection of the sustain electrode line 131 and the data line 171, and two signal lines 121 and 171 are also formed at the intersection of the gate line 121 and the data line 171. A semiconductor can be provided between the two lines to strengthen the disconnection of the two signal lines 121 and 171. Unlike FIG. 1, a semiconductor may be placed under the data line 171. The semiconductors 152 and 154 may be made of amorphous silicon.

Looking at the manufacturing method in detail, a gate line is formed on a substrate, and a gate insulating film, a semiconductor layer, an intermediate layer, and an electrode layer are successively deposited, and then a photosensitive film is coated thereon. The photosensitive film is irradiated with light through a mask and then developed to form a photosensitive film pattern. The first portion of the photoresist pattern positioned in the channel portion between the source electrode and the drain electrode is made smaller in thickness than the second portion located in the portion where the data line is to be formed, and all other portions of the photoresist are removed. Subsequently, after removing the photoresist residue remaining on the surface through ashing, the source layer and the drain electrode are separated by etching and removing the electrode layer of the channel portion and the intermediate layer pattern thereunder. Next, a protective film, a pixel electrode, and the like are formed.

A plurality of island-like ohmic contacts 161 and 162 for reducing contact resistance between the semiconductors 151 and 152 on the island and the source electrode 173 and the drain electrode 175 or the data line 171. Is formed. The ohmic contacts 161 and 162 are made of amorphous silicon doped with silicide or n-type impurities at a high concentration.

The gate electrode 121, the source electrode 173, and the drain electrode 175 form a thin film transistor together with a portion of the semiconductor 154 between the source electrode 173 and the drain electrode 175.

On the data line 171, the drain electrode 175, the storage electrode line connection part 176, and the semiconductors 152 and 154 not covered with these, an inorganic insulating material such as silicon nitride is deposited on the plasma enhanced chemical vapor deposition (PGA). A thin inorganic protective film 180a having a thickness of about 300 mW to 700 mW formed by PECVD is provided. The inorganic passivation layer 180a may include a portion of the drain electrode 175, a gate pad 129 of the gate line 121, a contact portion 179 of the data line 171, an end portion of the storage electrode line 131, and a connection portion of the storage electrode line 176. ) And a plurality of contact holes (185, 181, 182, 183, 184, 186) positioned over the ends thereof. On the inorganic insulating layer, an organic passivation layer 180b, which is formed of a photosensitive organic material having excellent planarization characteristics and has a low dielectric constant of 3.0 or less, is formed. This organic protective film 180b has a thickness of about 0.7 μm or more. Similar to the inorganic protective film 180a, the organic protective film 180b also has a contact hole 185, 181, and 182 having substantially the same position and the same shape as the contact holes 185, 181, 182, 184, and 186 of the inorganic protective film 180a. , 183, 184, 186). That is, the plurality of contact holes 182 and at least one end of the storage electrode line 131 exposing at least a portion of the drain electrode 175 and the data pad portion 179 which is the end of the data line 171, respectively. Contact holes 186 and a plurality of contact holes 187 and 188 located in the middle and end portions of the sustain electrode wire connecting portion 176 are provided.

These contact holes are used for two purposes. The edges of the thin film transistor array panel are mainly used to receive various signals from semiconductor chips, etc., and the inner side is a means for electrically connecting internal wirings. Used. As will be described later, a method of forming a connecting leg as a conductive material on the passivation layer 180b as an electrical connecting means and connecting the lower conductors through contact holes is used.

 In particular, the contact holes 181 and 186 on the gate pad 129 and the end of the storage electrode line 131 at the end of the gate line 121 have both of these wires 121 and 131 below the gate insulating layer 140. Therefore, not only the passivation layers 180a and 180b but also the gate insulating layer 140 penetrates to expose the respective interconnections 121 and 131.

As indicated by reference numeral C in FIG. 2, for example, the thickness of the organic passivation layer 180b is reduced around the contact hole 185 exposing the drain electrode 175 so that the contact hole (from the surface of the organic passivation layer 180b is formed). 185) the step down is slow. In order to facilitate the structure, as described above, the material of the organic passivation layer 180b preferably has photosensitivity. In this case, a method of making the structure around the contact hole 185 with a step difference is briefly described.

First, a positive photosensitive organic film is coated on the substrate 110, the exposure mask (not shown) is aligned, and then exposed through a mask (not shown).

The exposure mask is provided with a transflective area having a slit pattern composed of a transparent area, an opaque area, and a plurality of slits having a width smaller than the resolution of the exposure machine. The transparent area of the exposure mask corresponds to the contact hole 185, and a slit pattern is disposed around the transparent area. Since the exposure amount of the photoresist portion exposed through the slit pattern is small and the exposure amount of the portion of the contact hole 185 exposed through the transparent region is sufficient, a portion of the photoresist portion having a small exposure after the development of the photoresist has some thickness and has a sufficient exposure amount. 185) The part is completely removed. Subsequently, the exposed inorganic insulating layer 180a and the gate insulating layer 140 are dry-etched using the organic insulating layer 180b as an etch stop layer to form a contact hole 185.

At this time, in order to form contact holes 186 and 181 for exposing the wiring of the metal layer of the same layer as the gate line 121, such as the end of the storage electrode line 131, the gate insulating layer 140, which is an inorganic insulating layer, is also included. The metal layer and the inorganic insulating layer have to be removed by dry etching. In this case, since the metal and the inorganic insulating layer have different etching selectivity, the metal layer exposed through the contact holes on the wires in the same layer as the data line 171 uses almost no etching property.

On the other hand, in the peripheral region where the data pad 179 at the end of the data line 171 and the gate pad 129 at the end of the gate line 121 are located, parasitic capacitance is not a concern, as shown in FIGS. 2 and 3. The thickness of the organic insulating film 180b is made smaller than in the active region. In this case, the wiring 121 which exposes the pad bump (not shown) of the substrate 430 or the driving circuit chip on which the signal line 420 for applying the gate signal or the data voltage is formed through the contact holes 181 and 182. When it attaches with 171 and the anisotropic conductive film 410, contact reliability becomes high. In order to do so, in the process of forming the protective film 180a and 180b patterns, as in the periphery of the contact hole, the active region having the pixel electrode 190 corresponds to the periphery region by making a transflective region made of a slit or translucent material smaller than the resolution of the exposure machine corresponding to the periphery region. The height of the passivation layer 180b may be lower than that of the region.

On the passivation layer 180, the pads at the ends of the plurality of data pads 179, the gate pads 129, and the storage electrode line connecting portion 176 including the plurality of pixel electrodes 190 and the contact holes 181, 182, and 186 thereon. Connection legs 85 including a plurality of contact auxiliary members 81, 82, and 86 electrically connected through the same, and, for example, a connection bridge between the storage electrode line 131 and the storage electrode line connection part 176. ) Is formed. These are all made of the same material and made of a conductor such as indium tin oxide (ITO) or indium zinc oxide (IZO).                     

As shown in FIGS. 1 and 2, the pixel electrode 190 completely covers the inner edges of adjacent sub data lines 171a and 171b. As shown in FIG. 2, the distance w1 between the edge of the pixel electrode 190 and the inner edges of the sub data lines 171a and 171b adjacent thereto is preferably about 2 μm or more. However, this figure may vary depending on the misalignment margin of the exposure equipment. The pixel electrode 190 is electrically connected to the thin film transistor through the contact hole 185 on the drain electrode 175 extending to the storage electrode line 131.

As such, when the pixel electrode 190 covers the inner edges of the adjacent sub data lines 171a and 171b, the pixel electrode 190 and the sub data line 171a may be shifted even if a deviation occurs within the alignment error on the left and right sides of the display panel 100. , 171b) has the same parasitic capacitance.

The opposing display panel 200 will now be described.

The color filter layer 230 is formed on the transparent insulating substrate 210 such as glass to face the pixel electrode 190 of the thin film transistor array panel 100, and a transparent insulating film 250 made of an organic material is formed thereon. The counter electrode 270 is formed thereon. The transparent insulating layer 250 is not necessarily required, and the opposite electrode 270 may directly come on the color filter layer 230. As described above, since the light blocking member 160 of the thin film transistor array panel 100 is sufficiently prevented from leaking light, there is no need to provide a light blocking member such as a black matrix on the opposing display panel 200.

The alignment layers 11 and 21 are formed on the inner surfaces of the thin film transistor array panel 100 and the opposing display panel 200, respectively, and the polarizers 12 and 22 are attached to the outer surfaces thereof. The alignment films 11 and 21 are located almost in the active region.

The real material 330 is positioned between the thin film transistor array panel 100 and the opposing display panel 200 and has a band shape extending along the circumference of the opposing display panel 200. At least a portion of the actual material 330 and the light blocking member 160 may be overlapped to prevent light leakage.

The liquid crystal layer 300 is positioned between the pixel electrodes 190 and the alignment layers 11 and 21 formed on the opposing electrode 170 of the thin film transistor array panel 100 and the opposing display panel 200, respectively, in an area surrounded by the real material 330. It is imprisoned.

Various kinds of liquid crystal display devices can be configured according to the kind of material of the alignment film 11 and 21, the kind of the liquid crystal 300, the alignment method, and the like. In the case of the liquid crystal display shown in FIGS. 1 to 3, it is preferable to use the twisted nematic (TN) mode.

When the liquid crystal display device is used in the vertical alignment mode, it is preferable to provide a plurality of cutouts (not shown) in the pixel electrode 190 and the counter electrode 270 to extend the viewing angle. The cutouts are parallel to each other and refracted at least once so that the electric field generated by the pixel electrode 190 and the counter electrode 270 is distorted by the fringe field effect caused by the cutout, so that the liquid crystal molecules are positioned on one pixel electrode 190. The lying direction of the field appears in several directions. Instead of placing an incision in both electrodes 190 and 270, an incision in the pixel electrode 190, and an incision in the pixel electrode 190 between the alignment layer 21 and the opposite electrode 270 on the opposite electrode 270 side. The projections may be parallel to and formed of a photosensitive organic film. The direction of liquid crystal molecules lying down is determined by the difference between the dielectric constant of the projections and the dielectric constant of the liquid crystals or the inclined plane of the projections. You can make a variety. Only protrusions may be provided on both the pixel electrode 190 and the counter electrode 27 without a cutout.

A liquid crystal display according to a second exemplary embodiment of the present invention will be described with reference to FIGS. 4 to 6.

4 is a layout view of a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 5 is a V-V of the liquid crystal display of FIG. 4 in a state in which the thin film transistor array panel and the opposing display panel are assembled. 6 is a cross-sectional view taken along the line VI-VI ′ of the liquid crystal display of FIG. 4, with the thin film transistor array panel and the opposing display panel assembled in FIG. 4.

The liquid crystal display according to the second embodiment has an arrangement structure and a layered structure similar to that of the liquid crystal display according to the first embodiment.

First, a thin film transistor array panel includes a plurality of gate lines 121 including a plurality of gate electrodes 124 on the substrate 110, a plurality of light blocking members 160 and a plurality of layers forming the same layer as the gate lines 121. A plurality of storage electrode lines 131 including the storage electrodes 133 of the plurality of storage electrodes 133 are formed, and a gate insulating layer 140, a plurality of semiconductors 154, and a plurality of ohmic contacts 161 and 162 are sequentially formed thereon. have. A plurality of source electrodes 173 are disposed on the ohmic contact members 161 and 162, and each of the plurality of data lines 171 and the plurality of drain electrodes 175 and the pair of sub data lines 171a and 171b is provided. The electrode pole connection part 176 is formed, and the inorganic protective film 180a is formed on it. An organic passivation layer 180b is formed on the inorganic passivation layer. A plurality of contact holes 181, 182, 183, 184, 185, and 186 are formed in the passivation layer 180a and 180b and / or the gate insulating layer 140, and the pixel electrodes 190 and the upper passivation layer are formed on the organic passivation layer 180b. 190, a plurality of contact assisting members 81 and 82, and a plurality of connecting legs 85 are formed.

The opposing display panel 200 includes an insulating substrate 210 and a common electrode 270 thereon.

The inner surfaces of the two display panels 100 and 200 are provided with alignment layers 11 and 21, and the outer surfaces of the display panels 100 and 200 are provided with polarization plates 12 and 22, and between the two display panels 100 and 200, a real material 330 and a liquid crystal layer ( 300 and the substrate 430 on which the signal line 420 is formed are attached to the thin film transistor array panel 100 by the anisotropic conductive film 410.

4 and 5, in the liquid crystal display according to the present exemplary embodiment, the color filter layer 230 is formed on the inorganic passivation layer 180a of the thin film transistor array panel 100 instead of the opposing display panel 200. The color filter layer 230 has three primary colors such as RGB (red, green, blue), and the edge of each color filter layer 230 is located between the sub data lines 171a and 171b and is inside the sub data lines 171a and 171b. The color filter layer 230 includes a plurality of contact holes 231 positioned only in the active region and exposing the edges of the inorganic passivation layer 180a of the contact hole 185. As described above, since the color filter layer 230 is on the thin film transistor array panel 100, the counter electrode 270 is formed directly on the glass substrate 210 as shown in FIG. 5. Accordingly, the opposing display panel 200 according to the present exemplary embodiment may be simply formed without a separate photo process.                     

Although the above has been described with reference to preferred embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

As described above, when each data line is formed as a pair of sub data lines parallel to each other, and pixel electrodes positioned on both sides of each sub data line overlap with adjacent sub data lines, and the light blocking member covers the data lines and the pixels therebetween. The parasitic capacitance generated between the electrodes can be minimized and the aperture ratio can be maximized. As a result, the image quality of the display device may be prevented from deteriorating due to the parasitic capacitance or the deviation thereof, and in particular, the stitch phenomenon caused by the parasitic capacitance variation may be minimized.

Claims (17)

A plurality of gate lines transferring scan signals, A plurality of data lines intersecting the gate lines and transferring image signals, each of the first and second sub data lines electrically connected to and separated from each other; A plurality of pixel electrodes electrically connected to the gate line and the data line through the thin film transistor and covering both edges of the adjacent first sub data line or the second sub data line; A protective film formed between the data line and the pixel electrode, and The light blocking member forming the same layer as the gate line and covering the first sub data line and the second sub data line. Thin film transistor array panel comprising a. In claim 1, The light blocking member overlaps the near edges of the first and second sub data lines and does not overlap the far edge. 3. The method of claim 2,  The passivation layer may include an inorganic insulating layer. In claim 1, The passivation layer is a thin film transistor array panel made of an organic insulating material. In claim 4, The passivation layer is a thin film transistor array panel made of a color filter. In claim 1, And a storage electrode overlapping the pixel electrode to form a storage capacitor. The thin film transistor array panel of claim 1, An opposing display panel facing the thin film transistor array panel and having an opposing electrode facing the pixel electrode; The liquid crystal layer formed between the thin film transistor array panel and the opposing display panel. Liquid crystal display comprising a. 8. The method of claim 7, And the liquid crystal layer has negative dielectric anisotropy and a long axis of liquid crystal molecules of the liquid crystal layer is oriented perpendicular to the surfaces of the two display panels. In claim 8, And said counter electrode and said pixel electrode have pixel dividing means for dividing and aligning liquid crystal molecules of said liquid crystal layer. The method of claim 9, And the pixel dividing means is a cutout or protrusion. 8. The method of claim 7, The thin film transistor of the thin film transistor array panel may include a gate electrode, a source electrode, a drain electrode, And a first semiconductor member positioned between the source electrode and the drain electrode. 12. The method of claim 11, And a second semiconductor member positioned below the data line. The method of claim 12, The second semiconductor member except for the channel portion between the source electrode and the drain electrode has the same shape as the data line and the drain electrode and is wider than the data line. A plurality of gate lines transferring scan signals, A plurality of data lines intersecting the gate lines and transferring image signals, each of the first and second sub data lines electrically connected to and separated from each other; A plurality of pixel electrodes electrically connected to the gate line and the data line through the thin film transistor and covering both edges of the adjacent first sub data line or the second sub data line; A color filter layer formed between the data line and the pixel electrode; And a light blocking member forming the same layer as the gate line and covering the first sub data line and the second sub data line. The method of claim 14,  A thin film transistor array panel further comprising an inorganic insulating layer disposed between the color filter layer and the data line. The method of claim 14, And a storage electrode overlapping the pixel electrode to form a storage capacitor. The method of claim 1 or 14, The pixel electrode is bent at least once.

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