KR101045687B1 - Alarm display signal detection device and method - Google Patents

Abstract

The present invention relates to an alarm indication signal detection method and apparatus for detecting an alarm indication signal (AIS) from an input signal according to an optical transmission network (OTN) transmission method. A signal converter for converting the signal into a signal; A signal generator configured to generate a comparison target signal for each of the input signals converted in the parallel form; And a detector configured to detect an input of the alarm display signal based on the parallel-type signal converted by the signal converter and the generated comparison target signal. The field programmable gate array (FPGA), which is currently commercially available in OTN systems, can detect alarm indication signals (AIS) in optical transmission network (OTN) signals with transmission rates of several tens of Gbps through parallel processing. have.

Description

Apparatus and Method for detecting AIS

The present invention relates to an alarm indication signal detection method and apparatus for detecting an alarm indication signal (AIS) from an input signal according to an optical transmission network (OTN) transmission scheme.

This study is derived from the research conducted as part of the IT source technology development project of the Ministry of Knowledge Economy and ICT. [National Control No.: 2008-F-017-01, Project Name: 100Gbps Ethernet and Optical Transmission Technology Development]

Recently, in the field of optical transmission, several tens of Gbps transmission systems are actively developed based on a new transmission method called an OTN (Optical Transport Network) following the synchronous transmission method. Therefore, in the future, the optical transmission system (OTN) transmission method is expected to be the mainstream. Currently, it is standardized to OTU3 having a transmission rate of 43Gbps and standardization is in progress to expand to 100Gbps.

As the capacity of the optical transmission system increases, the damage caused by the system failure may also increase, so the system operation and maintenance are important. Existing optical transmission systems have also used maintenance signals to compensate for this, and an alarm indication signal (AIS) is one such signal.

In case of a system failure, when an alarm indication signal (AIS) is sent to the other side, the other side can detect the alarm indication signal to determine whether there is a failure, and prevent the failure from propagating, so the operator can easily determine which node in the network has failed. Can be.

Although the alarm indication signal (AIS) is defined in the optical transmission network (OTN) transmission method, a new alarm indication signal (AIS) is defined because a signal pattern that is different from the alarm indication signal (AIS) type in the conventional transmission method is defined. Detection scheme is required. Furthermore, in order to implement AIS signals defined in optical transmission network (OTN) transmission methods that process signals of several tens of Gbps, using commercial FPGAs, alarm indication signals (AIS) can be detected in the form of multiple low-speed parallel signals. There is a need for detection techniques.

The present invention is derived from this background, and provides a low speed field programmable gate array (FPGA) for alert indication signal (AIS), which is essential for the operation and maintenance of an optical transmission network (OTN) optical transmission system. It is an object of the present invention to provide an alarm display signal detection apparatus and method that can detect using.

The technical problem is an alarm display signal detection device for detecting an alarm indication signal (AIS) from an input signal according to an optical transmission network (OTN) transmission method, converting a high-speed input signal into a low-speed parallel form signal A signal converter; A signal generator configured to generate a comparison target signal for each of the input signals converted in the parallel form; And a detector configured to detect an input of the alarm display signal based on the parallel type signal converted by the signal converter and the generated comparison target signal.

At this time, the number of bits to determine the number of bits of interest in the binary bit string included in the input signal input for a unit time and the number of bits of interest in the binary bit string included in the comparison target signal; The detector may be a predetermined number of bits or more in a binary bit string included in the input signal determined by the bit number determiner, and may include a binary bit string included in the comparison target signal determined by the bit number determiner. If the number of bits of interest is less than a predetermined number, the input of the alarm display signal is detected.

The bit number obtaining unit may further include: a counting unit counting the number of bits of interest included in a group of binary bits simultaneously inputted in parallel, and a counting result of the counting unit; And a cumulative adder for accumulating and adding the number of the bit strings of interest included in the bit strings.

The counting unit may include: a plurality of interest bit calculators for receiving a number of bits of binary bit groups simultaneously input in parallel, and calculating a number of bits of interest from the specific number of bits; And an interest bit adder that adds up all the number of interest bits calculated by the plurality of interest bit calculators.

On the other hand, the technical problem is an alarm indication signal detection method for detecting an alarm indication signal (AIS) from an input signal according to the optical transmission network (OTN) transmission method, a high-speed input signal to a low-speed parallel form signal Converting to; Generating a comparison target signal for each of the input signals converted into the parallel form; And detecting an input of the alarm display signal based on the converted parallel type signal and the generated comparison target signal.

And counting the number of bits of interest included in a group of binary bits simultaneously inputted in parallel for each of the input signal and the signal to be compared before the detecting; And accumulating the count result and accumulating and adding the number of bit strings of interest included in the binary bit string of the input signal inputted during a unit time. The detecting may include the input of determining the cumulative addition result. When the number of bits of interest in the binary bit string included in the signal is more than a predetermined number and the number of bits of interest in the binary bit string included in the comparison target signal is less than a predetermined number, the input of the alarm display signal may be detected.

The detecting may determine whether the number of bits of interest is a predetermined number or more according to the most significant bit (MSB) value of the cumulative addition result.

The detection and release of alarm indication signals (AIS) in optical transport network (OTN) systems play a very important role in the operation and maintenance of the system. According to the present invention, an alarm indication signal (AIS) in an optical transmission network (OTN) signal having a transmission rate of several tens of Gbps using a field programmable gate array (FPGA) currently commercially available in an optical transmission network (OTN) system. Can be detected through a parallel processing technique. It is also easy to apply to optical transmission networks (OTNs) with higher transmission rates.

The foregoing and further aspects of the present invention will become more apparent through the preferred embodiments described with reference to the accompanying drawings. Hereinafter, the present invention will be described in detail so that those skilled in the art can easily understand and reproduce the present invention through these embodiments.

1 is a diagram illustrating an OTU3 frame and an OTU3 AIS signal according to an embodiment.

OTU3 signal has a 43Gbps transmission rate among standardized OTN signals.

As shown in FIG. 1, an overhead signal is carried in the front part in the basic form of the OTU3 frame 10. In addition, a payload region in which actual input data is multiplexed and loaded is included in the middle region. In the latter part, a code including an error detection and correction function is included, and a forward error correction (FEC) code is performed before transmission without using a reverse channel. As shown in FIG. 1, the OTU3 AIS 15 signal type has a form in which a PN-11 signal pattern is inserted into an entire OTU3 frame region. Here, PN-11 means a pseudo random binary sequence (PRBS) composed of 11 registers. The composition is standardized in the recommendations of the ITU-T.

2 is a block diagram of an alarm display signal detection apparatus according to an embodiment.

As shown, it includes an alarm display signal generator 200 and an alarm display signal detector 210 according to an embodiment of the present invention.

The alarm display signal generator 200 includes eleven registers and one EXOR gate. In the present embodiment, the alarm display signal generator 200 may be implemented in the same manner as a general PRBS generator.

The alarm indication signal detector 210 includes eleven registers, two EXOR gates 213, and a determiner 215.

Typically, the detection and release of the alarm indication signal accumulates the number of input signal bits '1' by the determiner 215 of FIG. 2 at 8192 bit intervals of Din and D2. The determiner 215 generates an AIS when three intervals of less than 256 bits of '1' accumulated in D2 per unit time (8192 bit intervals) and more than 256 bits of '1' accumulated in Din are consecutive. It is determined that it is detected. In addition, the determiner 215 releases the AIS when the interval in which the number of bits of '1' accumulated in D2 per unit interval is 256 or more or the interval in which the number of bits of '1' accumulated in Din is less than 256 consecutive times is consecutive.

The method for detecting and releasing OTU3 AIS according to the configuration of FIG. 2 may be implemented as it is when signal processing speed is not high. However, in the case of the 43 Gbps OTU3 signal, the signal processing speed is too high, it is difficult to apply the existing configuration.

3 is a block diagram of an alarm display signal detection apparatus according to an embodiment of the present invention.

As shown, the alarm display signal detection apparatus according to an embodiment of the present invention converts a 43Gbps OTU3 signal into a low-speed 256 parallel signal and processes it. In this case, since the processing speed is about 168Mbps, it is possible to implement using a conventional field programmable gate array (FPGA).

As shown in FIG. 3, the alarm display signal detecting apparatus according to the exemplary embodiment of the present invention includes a signal converter 300, a signal generator 310, and a detector 380.

The signal converter 300 receives a 43Gbps OTU3 signal and converts the signal into a 256-bit low-speed parallel signal.

The signal generator 310 generates a comparison target signal for each of the signals converted in parallel in the signal converter. In the present embodiment, the signal to be compared is generated by an exclusive logical sum of the input signal Din and the signal which is delayed to each of the 9 and 11 of the 11 registers.

The detector 380 detects the alarm display signal AIS based on the parallel signal converted by the signal converter 300 and the comparison target signal generated by the signal generator 310.

In addition, the alarm display signal detection apparatus according to an embodiment of the present invention, the detection unit 380, the first counting unit 320, the first cumulative adder 340, the first to determine the detection value of the alarm display signal; The first temporary storage unit 360, the second counting unit 330, the second cumulative adding unit 350, and the second temporary storage unit 370 may be further included.

The first counting unit 320 counts the number of bits including "1" in each of the 256 input signals converted in parallel. In addition, the first cumulative adder 340 accumulates and adds the count result in the first counting unit 320, so that the total of bits including the bits of interest included in the input signal input during the unit time, that is, "1". Know the number. The unit time may be an input time of an 8192 bit signal. The first temporary storage unit 360 stores the addition result in the first cumulative adding unit 340. In the present embodiment, the first temporary storage unit 360 may be implemented as a register capable of storing three recent results. In this case, the first temporary storage unit 360 may store a combination result of the output value of the first cumulative adder 340 and the output value of the second cumulative adder 350.

In addition, the second counting unit 330 counts the number of bits including "1" in the comparison target signal generated by the signal generator. In this case, the second counting unit 330 also counts the number of bits including "1" in the 256 comparison signals generated for each of the 256 input signals converted in parallel. The second cumulative adder 350 accumulates and adds the count result of the second counter 330 to determine the total number of "1s" included in the comparison target signal generated during the unit time. The unit time may be an input time of an 8192 bit signal as described above. The second temporary storage unit 370 stores the addition result in the second cumulative adding unit 350. In the present embodiment, the second temporary storage unit 370 may be implemented as a register capable of storing three recent results. In this case, the second temporary storage unit 370 may store a combination result of the output value of the second cumulative adder 350 and the output value of the first cumulative adder 340.

The detector 380 detects an alarm indication signal AIS based on a result stored in the first temporary storage unit 360 and a result stored in the second temporary storage unit 370. In the present embodiment, the detection unit 380 is input according to the addition result in the first cumulative adder 340 based on the results stored in the first temporary storage unit 360 and the second temporary storage unit 370. The number of bits including '1' per unit time in the signal is less than 256, and the number of bits including '1' per unit time in the comparison target signal is 256 or more according to the addition result in the second cumulative adder 350. If it is successive three times, it is determined that the input of the alarm indication signal AIS has been detected. On the other hand, according to the addition result in the first cumulative adder 340, the number of bits including '1' per unit time in the input signal is 256 or more, and compared according to the addition result in the second cumulative adder 350. When the number of bits including '1' per unit time in the target signal is less than 256 consecutively, the information display signal AIS is released.

4 is a block diagram of a signal generator according to an exemplary embodiment of the present invention.

The comparison target signal D2 is an exclusive logical sum between the input signal Din and a signal delayed 9 and 11 times, respectively. In the present embodiment, the comparison target signal D2 may be obtained through the following combination. The input signal Din and the signal that is retimed once with a D flip-flop are referred to as P and the signal that is retimed once again with P.

P(K+9)

P(K+11), (0 ≤ k ≤ 244)D2 (k) = P (k)

P (K + 9)

P (K + 11), (0 ≤ k ≤ 244)

Q(K-245)

P(K+9), (245 ≤ k ≤ 246)D2 (k) = P (k)

Q (K-245)

P (K + 9), (245 ≤ k ≤ 246)

Q(K-245)

P(K+9), (0 ≤ k ≤ 244)D2 (k) = P (k)

Q (K-245)

P (K + 9), (0 ≤ k ≤ 244)

는 배타적 논리합(Exclusive OR) 게이트로 구현된다. here,

Is implemented as an exclusive OR gate.

As illustrated in FIG. 4, the signal generator 310 may generate a comparison target signal D2 for each of 256 input signals input in parallel.

5 is a block diagram of a counting unit according to an embodiment of the present invention.

The counting units 320 and 330 count the number of bits including '1' for 256 input signals input in parallel. In the present embodiment, the counting units 320 and 330 include 64 four-bit calculators 500 for dividing the 256 parallel signals by four and counting the number of bits including '1' of interest. The bit adder 510 may accumulate the number of '1's in 256 input signals by serially connecting adders A3, A4, A5, A6, A7, and A8 adding the output values. It includes. In addition, it is also possible to retime some of the multiple adders using a D flip-flop.

The 4-bit bit calculator 500 counts the number of bits of interest 1, that is, 1, in any 4-bit data. The result of the count is represented by three bits.

For example, since '0000' is 0, the output value is '000'. In the case of '0001, 0010, 0100, 1000', since the number of 1s is 1, the output value is '001'. In addition, since the number of 1 is' 0011, 0110, 1100, 0101, 1010, 1001 ', the output value is' 010', and the '0111, 1110, 1011, 1101' is 3, so the output value is' 011 'and' 1111 'are' 100 'because the number of 1's is 4's. That is, the number of bits including '1' in the 4-bit input value may be a value between 000 and 100.

After that, adding up all the values from the 64 4-bit calculators, we can finally determine the number of bits that contain '1' in all 256 parallel signals.

As described above, if the input is 4 bits, 1 can contain up to 4 bits. Therefore, the sum of two 4bit inputs is up to eight.

In the case of a general adder, if the input is 4 bits, since the input value is between 0 and 15 decimal, the sum of two inputs should be able to represent the maximum value from 0 to 31. However, in the embodiment according to the present invention, a simpler implementation is proposed to simply count the number of bits including '1'.

As shown in FIG. 5, A3, the first adder, receives two 3-bit inputs from two 4-bit bit calculators 500. Here, the number of bits including '1' in the 4 bit input value in all cases is a value between 000 and 100. That is, since values of 101 to 111 are not input, it is possible to count the number of bits including '1' using the most significant bit MSB as follows.

1.If MSB (A) = 1, MSB (B) = 1, Q (3: 0) = 1000

2.If MSB (A) = 1, MSB (B) = 0, Q (3: 2) = 01, Q (1: 0) = B (1: 0)

3.If MSB (A) = 0, MSB (B) = 1, Q (3: 2) = 01, Q (1: 0) = A (1: 0)

4.If MSB (A) = 0, MSB (B) = 0, Q (3) = 0, Q (2: 0) = A (1: 0) + B (1: 0)

Here, the most significant bit MSB (Most Significant Bit) of the input value input to the adder is 1, which means that the number of bits including '1' is 4 out of 4 bits. Thus, if the inputs A and B of adder A3 are MSB values for both, that is, MSB (A) = 1 and MSB (B) = 1, the sum is eight. If either MSB is 1 and the other MSB is 0, the number of '1' is 4, 4, 5, 6 and 7. This value can be obtained by the above equations (2) and (3). That is, in the case of Equation 2, the first two digits of the 4 bit output value Q (3: 2: 1: 0) are 01, and the second digit is the number of 1's in B. In the case of Equation 3, the first two digits of the 4 bit output value Q (3: 2: 1: 0) are 01, and the second digit is the number of 1's in A.

When all MSBs are 0, it means that A and B values are 0-3. Therefore, the maximum value of the output value is 6, which can be obtained by the above equation 4. In other words, the first one digit of the 4-bit output value Q (3: 2: 1: 0) is 0, and the last three digits are the sum of the number of 1s included in the value inputted by A and the number of 1s included in the value inputted by B to be.

This counting method makes it possible to implement the circuit configuration more simply and to increase the counting speed than to sum all the actual numbers.

The adder A3 shown in FIG. 5 receives 3 bit values from two 4 bit calculators and outputs 4 bit result values. The adder A4 receives 4 bit values from the two adders A3 and outputs a result of 5 bits. In this way, it is calculated sequentially. Finally, adder A8 receives two 8-bit values and outputs a 9-bit result.

Accordingly, the counting unit according to an embodiment of the present invention can obtain the number of bits including '1' from the 256-bit input signal Din input in parallel. In the present embodiment, the first counting unit 320 and the second counting unit 330 may be embodied in the same manner as the configuration of the counting unit described with reference to FIG. 5.

Thereafter, the first cumulative adder 340 and the second cumulative adder 350 include '1' accumulated based on the counting results of the first counter 320 and the second counter 330. The number of bits used.

As described above, the output values of the first counter 320 and the second counter 330 are 9-bit values. In this value, if MSB = 1, that is, the 9th bit, which is the most significant bit, is 1, there are 256 or more 1's.

Hereinafter, in order to describe the operations in the cumulative adders 340 and 350 in detail, Xa is the count result in the first counting unit 320, and the value accumulated in the first cumulative adder 340 is Xb. The MSB values of Xa and Xb are referred to as Xa (MSB) and Xb (MSB). Then, the result of counting in the second counter 330 is Ya, and the value accumulated in the second cumulative adder 350 is Yb, and the MSB values of Ya, Yb are Ya (MSB), Yb (MSB). do.

The first cumulative adder 340 fixes Xb (MSB) = 1 when Xa (MSB) = 1 or Xb (MSB) = 1. On the other hand, when neither the Xa (MSB) nor the Xb (MSB) value is '1', an addition function of the Xa value and the Xb value is performed. The second cumulative adder 350 also operates on the same principle as the first cumulative adder 340 depending on the values of Ya (MSB) and Yb (MSB). As a result, depending on whether the MSB values of Xb and Yb per unit time are '1', it may be determined whether the number of bits including the bits of interest, ie, '1', is 256 or more.

The number of bits including the bit of interest '1' accumulated in the comparison target signal D2 through the second cumulative adder 350 during the unit time is less than 256, and the first cumulative adder 340 is input from the input signal. The condition in the case where the number of bits including the accumulated bit of interest '1' is 256 or more is equal to Yb (MSB) = 0 and Xb (MSB) = 1. On the contrary, the number of bits including the bit of interest '1' accumulated in the comparison target signal D2 through the second cumulative adder 350 in the unit time is 256 or more, and the first cumulative adder 340 is removed from the input signal. The condition that the number of bits including the bit of interest '1' accumulates through less than 256 is equal to Yb (MSB) = 1 and Xb (MSB) = 0.

Values according to such a condition are stored in the temporary storage units 360 and 370, that is, three registers. When three '1' values are continuously stored based on the values stored in the temporary storage units 360 and 370, the detector 380 satisfies the condition three times in a unit time interval, and performs AIS input detection and release. can do. More specifically, the detector 380 detects an input of an alarm display signal when three '1' values are stored in the first temporary storage unit 360, and the '1' value is input to the second temporary storage unit 370. When these three are stored, the alarm display signal input release is detected.

6 is a flowchart illustrating a method for detecting an alarm display signal according to an embodiment of the present invention.

First, a 43Gbps OTU3 signal is input and converted into a low-speed 256 parallel signal form (S600). In operation S610, a comparison target signal is generated for each of the signals converted in parallel. In the present embodiment, the signal to be compared is generated by an exclusive logical sum of the input signal Din and the signal which is delayed to each of the 9 and 11 of the 11 registers.

After that, the number of bits of interest included in the parallel input signal and the signal to be compared are simultaneously counted (S620).

In the present embodiment, the parallel input is simultaneously performed simultaneously through 64 parallel input signals and 64 4-bit bit calculators, each of which is divided into 4 signals for comparison and counting the number of bits of interest, that is, '1'. The number of bits of interest included in the 256 signals is determined. In order to add all of the output values, a plurality of adders may be serially connected to finally accumulate the number of bits including '1' in 256 input signals.

At this time, it is possible to count the number of bits including '1' using the most significant bit (MSB) as follows.

1.If MSB (A) = 1, MSB (B) = 1, Q (3: 0) = 1000

2.If MSB (A) = 1, MSB (B) = 0, Q (3: 2) = 01, Q (1: 0) = B (1: 0)

3.If MSB (A) = 0, MSB (B) = 1, Q (3: 2) = 01, Q (1: 0) = A (1: 0)

4.If MSB (A) = 0, MSB (B) = 0, Q (3) = 0, Q (2: 0) = A (1: 0) + B (1: 0)

Here, the most significant bit MSB (Most Significant Bit) of the input value input to the adder is 1, which means that the number of bits including '1' is 4 out of 4 bits in total. Thus, if the inputs A and B of adder A3 are MSB values for both, that is, MSB (A) = 1 and MSB (B) = 1, the sum is eight. If either MSB is 1 and the other MSB is 0, the number of '1' is 4, 4, 5, 6 and 7. This value can be obtained by the above equations (2) and (3). That is, in the case of Equation 2, the first two digits of the 4 bit output value Q (3: 2: 1: 0) are 01, and the second digit is the number of 1's in B. In the case of Equation 3, the first two digits of the 4 bit output value Q (3: 2: 1: 0) are 01, and the second digit is the number of 1's in A.

When all MSBs are 0, it means that A and B values are 0-3. Therefore, the maximum value of the output value is 6, which can be obtained by the above equation 4. In other words, the first one digit of the 4-bit output value Q (3: 2: 1: 0) is 0, and the last three digits are the sum of the number of 1s included in the value inputted by A and the number of 1s included in the value inputted by B to be.

By counting methods reflecting the most significant bit, the circuit configuration can be implemented more simply and the counting speed can be increased than the sum of all the numbers.

The counted result is accumulated and added to determine the number of bits of interest included in each of the input signal and the comparison target signal during the unit time (S630). The unit time may be an input time of an 8192 bit signal.

Thereafter, an alarm indication signal (AIS) input is detected based on the converted parallel type input signal and the number of bits of interest included in the generated comparison target signal during unit time (S640).

In this case, depending on whether the most significant bit (MSB) value of the number of bits included in each of the input signal and the signal to be compared for each unit time is '1', whether the number of bits including the bits of interest, that is, '1' is 256 or more You can check.

On the other hand, the above-mentioned alarm display signal detection method can be created by a computer program. The program may also be embodied by being stored in a computer readable media and being read and executed by a computer. The storage medium includes a magnetic recording medium, an optical recording medium and the like.

So far I looked at the preferred embodiments of the present invention. Those skilled in the art will appreciate that the present invention can be implemented in a modified form without departing from the essential features of the present invention. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the present invention is shown in the claims, and all differences within the scope equivalent thereto should be construed as being included in the present invention.

1 is a block diagram of an OTU3 frame and an OTU3 AIS signal according to an embodiment;

2 is a block diagram of an alarm display signal detection apparatus according to an embodiment;

3 is a block diagram of an alarm display signal detection apparatus according to an embodiment of the present invention;

4 is a block diagram of a signal generator according to an embodiment of the present invention;

5 is a block diagram of a counting unit according to an embodiment of the present invention;

6 is a flowchart illustrating a method for detecting an alarm display signal according to an embodiment of the present invention.

Claims (10)

An alarm display signal detection apparatus for detecting an alarm indication signal (AIS) from an input signal according to an optical transmission network (OTN) transmission method, A signal converter for converting a high speed input signal into a low speed parallel signal; A signal generator configured to generate a comparison target signal for each of the input signals converted in the parallel form; And And a detector configured to detect the alarm display signal based on the parallel type signal converted by the signal converter and the generated comparison target signal. The method of claim 1, And a bit number determiner configured to determine the number of bits of interest in the binary bit string included in the input signal input for a unit time and the number of bits of interest in the binary bit string included in the comparison target signal. The detector is interested in the binary bit string included in the comparison target signal included in the binary bit string included in the input signal grasped by the bit number grasping unit. And if the number of bits is less than a predetermined number, detecting the input of the alarm display signal. The method of claim 2, wherein the bit number grasping unit, A counting unit for counting the number of bits of interest included in a group of binary bits simultaneously inputted in parallel; A cumulative adder configured to accumulate count results of the counting unit and accumulate and add the number of bit strings of interest included in the binary bit string of the input signal inputted during a unit time; Alarm display signal detection device comprising a. The method of claim 3, wherein the counting unit, A plurality of interest bit calculators for receiving a number of bits of the binary bit groups simultaneously input in parallel, and calculating the number of bits of interest in the specific number of bits; And And a bit of interest adder which sums all the number of bits of interest calculated by the plurality of bits of interest calculators. 5. The apparatus of claim 4, wherein the bit adder of interest comprises: And a plurality of adders arranged in stages so that the output of one adder becomes an input of the other adder so that the number of bits of interest are summed out. The method of claim 5, And the bit adder of interest performs addition on some bits of the input values according to a bit most significant bit (MSB) value for two input values. The method of claim 3, wherein And the detector determines whether the number of bits of interest is a predetermined number or more according to a value of a most significant bit (MSB) of a result value output from the cumulative adder. An alarm indication signal detection method for detecting an alarm indication signal (AIS) from an input signal according to an optical transmission network (OTN) transmission method, Converting a high speed input signal into a low speed parallel type signal; Generating a comparison target signal for each of the input signals converted into the parallel form; And And detecting the alarm indication signal based on the converted parallel type signal and the generated comparison target signal. The method of claim 8, wherein prior to the detecting step, Counting the number of bits of interest included in a group of binary bits that are simultaneously input in parallel with respect to each of the input signal and the signal to be compared; And Accumulating the count result and accumulating and adding the number of bit strings of interest included in a binary bit string of the input signal input for a unit time; The detecting may include: if the number of bits of interest is greater than or equal to a predetermined number of bits in the binary bit string included in the input signal determined as the cumulative addition result, and the number of bits of interest is less than or equal to a predetermined number of bits in the binary bit string included in the comparison target signal. And detecting an input of an alarm display signal. The method of claim 9, The detecting may include determining whether the number of bits of interest is a predetermined number or more according to a value of a most significant bit (MSB) of a cumulative addition result value in the form of an input bit string.

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