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KR101044382B1 - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

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KR101044382B1
KR101044382B1 KR1020040001528A KR20040001528A KR101044382B1 KR 101044382 B1 KR101044382 B1 KR 101044382B1 KR 1020040001528 A KR1020040001528 A KR 1020040001528A KR 20040001528 A KR20040001528 A KR 20040001528A KR 101044382 B1 KR101044382 B1 KR 101044382B1
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pattern
film
metal
via hole
film pattern
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KR20050073687A (en
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이달진
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/40—Resistors
    • H10D1/47—Resistors having no potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5228—Resistive arrangements or effects of, or between, wiring layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

금속 저항을 갖는 반도체 소자를 제조하기 위한 방법이 개시된다. 제1절연막 상에 제1금속막 및 반사 방지막을 형성한 후, 상기 반사 방지막 상에 제2절연막 패턴, 저항막 패턴 및 제3절연막 패턴을 형성한다. 그리고, 부분적으로 노출되는 반사 방지막 및 하부의 제1금속막을 순차적으로 식각하여 제1영역과 제2영역으로 분리된 구조를 갖는 반사 방지막 패턴 및 제1금속막 패턴을 형성한다. 이어서, 상기 분리된 구조의 제1금속막 패턴을 갖는 결과물 상에 제4절연막을 형성한 후, 상기 제4절연막을 식각하여 제1영역에는 저항막 패턴의 표면을 부분적으로 노출시키는 제1비아홀을 갖고, 제2영역에는 저항막 패턴의 표면을 부분적으로 노출시키는 제2비아홀 및 반사 방지막 패턴의 표면을 노출시키는 제3비아홀을 갖는 제4절연막 패턴을 형성하고, 상기 제1비아홀, 제2비아홀 및 제3비아홀에 금속 플러그를 형성한 후, 상기 금속 플러그와 연결되는 제2금속막 패턴을 형성한다. 이에 따라, 제1영역에는 반도체 소자의 금속 저항이 형성되고, 제2영역에는 반도체 소자의 커패시터가 형성된다.A method for manufacturing a semiconductor device having a metal resistance is disclosed. After forming the first metal film and the anti-reflection film on the first insulating film, a second insulating film pattern, a resistance film pattern and a third insulating film pattern are formed on the anti-reflection film. Subsequently, the partially exposed antireflection film and the lower first metal film are sequentially etched to form an antireflection film pattern and a first metal film pattern having a structure separated into a first region and a second region. Subsequently, after forming a fourth insulating layer on the resultant material having the first metal layer pattern having the separated structure, the fourth insulating layer is etched to form a first via hole that partially exposes the surface of the resistive layer pattern. And a fourth insulating film pattern having a second via hole partially exposing the surface of the resistive film pattern and a third via hole exposing the surface of the anti-reflection film pattern, and forming the first via hole, the second via hole, After forming a metal plug in the third via hole, a second metal film pattern connected to the metal plug is formed. Accordingly, a metal resistor of the semiconductor device is formed in the first region, and a capacitor of the semiconductor device is formed in the second region.

Description

반도체 소자의 제조 방법{method for forming a semiconductor device}Method for forming a semiconductor device

도 1a 내지 도 1f는 본 발명의 일 실시예에 따른 반도체 소자의 제조 방법을 설명하기 위한 단면도들이다.1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

10 : 기판 12 : 제1절연막10 substrate 12 first insulating film

14a : 제1금속막 패턴 16a : 반사 방지막 패턴14a: first metal film pattern 16a: antireflection film pattern

18a : 제2절연막 패턴 20a : 저항막 패턴18a: second insulating film pattern 20a: resistive film pattern

22a : 제3절연막 패턴 28 : 제4절연막 패턴22a: third insulating film pattern 28: fourth insulating film pattern

30 : 금속 플러그 32 : 제2금속막 패턴 30: metal plug 32: second metal film pattern

본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 보다 상세하게는 저항(resistor)을 갖는 반도체 소자를 제조하기 위한 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a resistor.

반도체 소자는 셀 영역과 주변 회로 영역을 포함한다. 상기 주변 회로 영역에는 주로 금속 배선, 저항, 증폭기 등과 같은 회로가 구성된다. 반도체 소자 중에서 특히, RF 소자는 무선 통신에 사용되는 부품이다. 그리고, RF 소자에 사용되는 저항의 경우에는 커패시터나 인덕터(inductor) 못지 않게 중요한 요소이다. 현재에는 상기 저항으로서 폴리 실리콘막으로 형성하는 폴리 저항을 주로 사용하고 있다. 그러나, 상기 폴리 저항은 고속 동작을 요구하는 반도체 소자 또는 무선 주파수를 요구하는 RF 소자와 같은 반도체 소자에 적용하기에는 그 한계가 있다. 특히, 상기 폴리 저항은 별도의 가공 공정을 거쳐야만 형성할 수 있다.The semiconductor device includes a cell region and a peripheral circuit region. In the peripheral circuit region, circuits such as metal wires, resistors, and amplifiers are mainly configured. Among semiconductor devices, in particular, RF devices are components used for wireless communication. In the case of a resistor used in an RF device, it is as important as a capacitor or an inductor. Currently, polyresist formed of a polysilicon film is mainly used as the resistor. However, the poly resistor has a limitation in application to semiconductor devices such as semiconductor devices requiring high speed operation or RF devices requiring radio frequency. In particular, the poly resistor can be formed only through a separate processing process.

따라서, 최근에는 간단한 공정의 실시와 아울러 고속 동작 및 무선 주파수를 요구하는 반도체 소자에 적극적으로 적용하기 위한 저항의 개발에 부단한 노력을 기울이고 있다.Therefore, in recent years, efforts have been made to develop resistors for active application to semiconductor devices that require high-speed operation and radio frequency as well as simple processes.

본 발명의 목적은 금속 저항과 커패시터를 동시에 형성할 수 있는 방법을 제공하는데 있다.It is an object of the present invention to provide a method for simultaneously forming a metal resistor and a capacitor.

상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자 제조 방법은, 제1절연막 상에 제1금속막 및 반사 방지막을 순차적으로 형성하는 단계; 상기 반사 방지막 상에 순차적으로 적층된 제2절연막 패턴, 저항막 패턴 및 제3절연막 패턴을 형성하는 단계; 상기 제3절연막 패턴을 갖는 결과물 상에 상기 반사 방지막의 표면을 부분적으로 노출시키는 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 식각 마스크로 사용한 식각으로 상기 노출된 반사 방지막 부분 및 그 하부의 제1금속막 부분을 순차적으로 식각하여 제1영역과 제2영역으로 분리된 구조를 갖는 반사 방지막 패턴 및 제1금속막 패턴을 형성하는 단계; 상기 식각 마스크로 사용한 포토레지스트 패턴을 제거하는 단계; 상기 포토레지스트 패턴이 제거된 결과물 상에 제4절연막을 형성하는 단계; 상기 제4절연막을 식각하여 제1영역에는 저항막 패턴의 표면을 부분적으로 노출시키는 제1비아홀을 갖고, 제2영역에는 저항막 패턴의 표면을 부분적으로 노출시키는 제2비아홀 및 반사 방지막 패턴의 표면을 노출시키는 제3비아홀을 갖는 제4절연막 패턴을 형성하는 단계; 상기 제1비아홀, 제2비아홀 및 제3비아홀 내에 금속 플러그를 형성하는 단계; 및 상기 제4절연막 패턴 상에 상기 금속 플러그와 연결되는 제2금속막 패턴을 형성하는 단계;를 포함한다.A semiconductor device manufacturing method according to the present invention for achieving the above object comprises the steps of sequentially forming a first metal film and an anti-reflection film on the first insulating film; Forming a second insulating film pattern, a resistance film pattern, and a third insulating film pattern sequentially stacked on the anti-reflection film; Forming a photoresist pattern partially exposing the surface of the anti-reflection film on the resultant having the third insulating film pattern; The anti-reflection film pattern and the first anti-reflective film pattern having a structure separated into a first region and a second region by sequentially etching the exposed anti-reflection film portion and the lower first metal film portion by etching using the photoresist pattern as an etching mask. Forming a metal film pattern; Removing the photoresist pattern used as the etching mask; Forming a fourth insulating layer on the resultant from which the photoresist pattern is removed; The fourth insulating layer is etched to have a first via hole partially exposing the surface of the resistive pattern in the first region, and a second via hole and anti-reflective layer pattern partially exposing the surface of the resistive pattern in the second region. Forming a fourth insulating film pattern having a third via hole exposing the light emitting layer; Forming a metal plug in the first via hole, the second via hole, and the third via hole; And forming a second metal film pattern connected to the metal plug on the fourth insulating film pattern.

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여기서, 상기 저항막 패턴은 금속막인 것이 바람직하고, 상기 제1금속막은 알루미늄막이고, 상기 금속 플러그는 텅스텐 플러그인 것이 바람직하다. 특히, 상기 제1영역에는 제1비아홀에 의해 연결되는 저항막 패턴과 제2금속막 패턴을 갖는 저항이 형성되고, 상기 제2영역에는 하부 전극으로서 반사 방지막 패턴을 갖고, 유전막으로서 제2절연막 패턴을 갖고, 상부 전극으로서 저항막 패턴을 갖는 커패시터가 형성된다. 아울러, 제2비아홀, 재3비아홀 및 제2금속막 패턴을 통하여 커패시터의 전기적 연결이 가능하다.Preferably, the resistive film pattern is a metal film, the first metal film is an aluminum film, and the metal plug is preferably a tungsten plug-in. In particular, a resistor having a resistive film pattern and a second metal film pattern connected by a first via hole is formed in the first region, the second region has an anti-reflection film pattern as a lower electrode, and a second insulating film pattern as a dielectric film. And a capacitor having a resistive film pattern as the upper electrode. In addition, the capacitor may be electrically connected through the second via hole, the third via hole, and the second metal film pattern.

이와 같이, 본 발명에 의하면, 반도체 소자의 금속 저항 및 커패시터를 동시에 형성할 수 있다.
As described above, according to the present invention, the metal resistor and the capacitor of the semiconductor element can be formed at the same time.

(실시예)(Example)

이하, 본 발명의 바람직한 실시예를 첨부한 도면에 따라서 더욱 상세히 설명하기로 한다.Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

도 1a 내지 도 1f는 본 발명의 일 실시예에 따른 반도체 소자의 제조 방법을 설명하기 위한 단면도들이다.1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 1a를 참조하면, 제1절연막(12)을 갖는 기판(10)을 마련한다. 그리고, 제1절연막(12) 상에 제1금속막(14) 및 반사 방지막(16)을 순차적으로 형성한다. 여기서, 제1금속막(14)은 알루미늄막이 주로 선택되고, 반사 방지막(16)은 주로 티타늄막, 질화 티타늄막 또는 이들의 다층막이 선택된다. 또한, 반사 방지막(16)은 후속되는 사진 식각 공정을 수행할 때 하부의 제1금속막(14)의 광반사로 인하여 발생하는 문제점을 줄이기 위하여 형성한다.Referring to FIG. 1A, a substrate 10 having a first insulating film 12 is prepared. The first metal film 14 and the anti-reflection film 16 are sequentially formed on the first insulating film 12. Here, the first metal film 14 is mainly selected from an aluminum film, and the antireflection film 16 is mainly selected from a titanium film, a titanium nitride film, or a multilayer film thereof. In addition, the anti-reflection film 16 is formed to reduce a problem caused by the light reflection of the lower first metal film 14 when performing the subsequent photolithography process.

도 1b 및 도 1c를 참조하면, 상기 반사 방지막(16) 상에 제2절연막(18), 저항막(20) 및 제3절연막(22)을 형성한다. 이때, 제2절연막(18)은 저항막(20)을 절연시키는 기능을 갖는다. 아울러, 제3절연막(22)은 후속 공정에서 비아홀을 형성할 때 식각 정지막의 기능을 갖는다. 특히, 기판 상에 형성되어 있는 박막들 중에서 제1금속막(14)과 반사 방지막(16), 제2절연막(18) 및 저항막(20)의 구조는 커패시터 즉, MIM(metal-insulator-metal) 커패시터와 거의 유사한 구조를 갖는다.1B and 1C, a second insulating film 18, a resistance film 20, and a third insulating film 22 are formed on the anti-reflection film 16. At this time, the second insulating film 18 has a function of insulating the resistive film 20. In addition, the third insulating layer 22 functions as an etch stop layer when the via hole is formed in a subsequent process. In particular, among the thin films formed on the substrate, the structures of the first metal film 14, the anti-reflection film 16, the second insulating film 18, and the resistive film 20 are capacitors, that is, metal-insulator-metal. ) Has a structure almost similar to a capacitor.

이어서, 제3절연막(22) 상에 포토레지스트막을 형성한다. 그리고, 포토레지스트막을 패터닝하여 포토레지스트 패턴(24)으로 형성한다. 계속해서, 포토레지스트 패턴(24)을 식각 마스크로 사용한 식각을 실시하여 제3절연막(22), 저항막(20) 및 제2절연막(18)을 순차적으로 식각한다. 그리고, 산소 플라즈마를 사용한 에싱(ashing)을 실시하여 기판(10) 상에 잔류하는 포토레지스트 패턴(24)을 완전히 제거한다. 이에 따라, 기판(10) 상에는 제2절연막 패턴(18a), 저항막 패턴(20a) 및 제3절연막 패턴(22a)이 순차적으로 형성된다.Next, a photoresist film is formed on the third insulating film 22. Then, the photoresist film is patterned to form a photoresist pattern 24. Subsequently, etching is performed using the photoresist pattern 24 as an etching mask to sequentially etch the third insulating film 22, the resistive film 20, and the second insulating film 18. Then, ashing using oxygen plasma is performed to completely remove the photoresist pattern 24 remaining on the substrate 10. Accordingly, the second insulating film pattern 18a, the resistive film pattern 20a, and the third insulating film pattern 22a are sequentially formed on the substrate 10.

도 1d 및 도 1e를 참조하면, 상기 제3절연막 패턴(22a)을 갖는 결과물 상에 포토레지스트막을 형성한다. 이어서, 사진 식각 공정을 실시하여 상기 반사 방지막(16)의 표면을 부분적으로 노출시키는 포토레지스트 패턴(26)을 형성한다. 즉, 상기 제3절연막 패턴(22a)을 갖는 결과물은 노출시키지 않고, 상기 반사 방지막(16)의 표면 일부분만을 노출시키도록 포토레지스트 패턴(26)을 형성하는 것이다.1D and 1E, a photoresist film is formed on the resultant having the third insulating film pattern 22a. Subsequently, a photolithography process is performed to form a photoresist pattern 26 partially exposing the surface of the anti-reflection film 16. That is, the photoresist pattern 26 is formed to expose only a portion of the surface of the anti-reflection film 16 without exposing the resultant having the third insulating film pattern 22a.

그리고, 부분적으로 노출된 반사 방지막(16) 및 하부의 제1금속막(14)을 순차적으로 식각하여 제1영역과 제2영역으로 분리되는 구조를 갖는 반사 방지막 패턴(16a) 및 제1금속막 패턴(14a)을 형성한다. 이어서, 산소 플라즈마를 사용한 에싱을 실시하여 기판 상에 잔류하는 포토레지스트 패턴(26)을 완전히 제거한다.In addition, the partially exposed antireflection film 16 and the lower first metal film 14 are sequentially etched to separate the antireflection film pattern 16a and the first metal film into a first region and a second region. The pattern 14a is formed. Subsequently, ashing using an oxygen plasma is performed to completely remove the photoresist pattern 26 remaining on the substrate.

도 1f를 참조하면, 상기 분리된 구조의 반사 방지막 패턴(16a) 및 제1금속막 패턴(14a)을 갖는 결과물 상에 제4절연막을 형성한다. 그리고, 포토레지스트 패턴을 식각 마스크로 사용하여 상기 제4절연막을 식각한다. 이에 따라, 제1영역에는 저항막 패턴(20a)의 표면을 부분적으로 노출시키는 제1비아홀(30a)을 갖고, 제2영역에는 저항막 패턴(20a)의 표면을 부분적으로 노출시키는 제2비아홀(30b) 및 반사 방지막 패턴(16a)의 표면을 노출시키는 제3비아홀(30c)을 갖는 제4절연막 패턴(28) 이 형성된다. 즉, 제1영역에는 반도체 소자의 저항과의 연결을 위한 제1비아홀(30a)이 형성되고, 제2영역에는 반도체 소자의 커패시터의 상부 전극과 하부 전극의 연결을 위한 제2비아홀(30b) 및 제3비아홀(30c)이 형성된다. 다시 말해, 제2영역의 하부 금속 배선인 반사 방지막 패턴(16a) 및 제1금속막 패턴(14a)이 하부 전극의 기능을 갖고, 제2절연막 패턴(18a)이 유전막의 기능을 갖고, 저항막 패턴(20a)이 상부 전극의 기능을 갖는데, 제2비아홀(30b) 및 제3비아홀(30c)을 통하여 상부 전극인 저항막 패턴(20a)과 하부 전극인 반사 방지막 패턴(16a)을 연결하는 것이다.Referring to FIG. 1F, a fourth insulating layer is formed on a resultant having the antireflection film pattern 16a and the first metal film pattern 14a having the separated structure. The fourth insulating layer is etched using the photoresist pattern as an etching mask. Accordingly, the first region has a first via hole 30a partially exposing the surface of the resistive pattern 20a and the second region partially exposing the surface of the resistive pattern 20a. A fourth insulating film pattern 28 having a third via hole 30c exposing 30b) and a surface of the anti-reflection film pattern 16a is formed. That is, a first via hole 30a is formed in the first region for connecting the resistor of the semiconductor device, and a second via hole 30b for connecting the upper electrode and the lower electrode of the capacitor of the semiconductor device is formed in the second region. The third via hole 30c is formed. In other words, the anti-reflection film pattern 16a and the first metal film pattern 14a, which are the lower metal wirings of the second region, have the function of the lower electrode, and the second insulating film pattern 18a has the function of the dielectric film, and the resistive film. The pattern 20a has a function of an upper electrode, which connects the resistive film pattern 20a as the upper electrode and the anti-reflection film pattern 16a as the lower electrode through the second via hole 30b and the third via hole 30c. .

이어서, 제1비아홀(30a), 제2비아홀(30b) 및 제3비아홀(30c)에 텅스텐으로 이루어지는 금속 플러그(30)를 형성한다. 금속 플러그(30)의 형성은 적층 및 연마에 의해 달성되는 것이 일반적이다. 계속해서, 금속 플러그(30)와 연결되는 제2금속막 패턴(32)을 형성한다. 제2금속막 패턴(32)의 형성은 적층 및 식각에 의해 달성되는 것이 일반적이다. Subsequently, a metal plug 30 made of tungsten is formed in the first via hole 30a, the second via hole 30b and the third via hole 30c. Formation of the metal plug 30 is generally achieved by lamination and polishing. Subsequently, the second metal film pattern 32 connected to the metal plug 30 is formed. Formation of the second metal film pattern 32 is generally achieved by lamination and etching.

이와 같이, 제1영역에는 제1비아홀(30a)에 의해 저항막 패턴(20a)과 제2금속막 패턴(32)이 연결되는 반도체 소자의 금속 저항이 형성되고, 제2영역에는 제2비아홀(30b) 및 제3비아홀(30c)에 의해 상부 전극과 하부 전극이 연결되는 반도체 소자의 커패시터가 형성된다.As described above, a metal resistance of the semiconductor device to which the resistive film pattern 20a and the second metal film pattern 32 are connected is formed by the first via hole 30a in the first region, and the second via hole is formed in the second region. 30b) and the third via hole 30c form a capacitor of the semiconductor device to which the upper electrode and the lower electrode are connected.

이와 같이, 본 발명에 의하면 간단한 공정을 통하여 금속 저항과 커패시터를 동시에 형성할 수 있다. 때문에, 최근의 반도체 소자 특히, RF 소자에 본 발명의 방법을 적극적으로 적용할 수 있다.As described above, according to the present invention, a metal resistor and a capacitor can be simultaneously formed through a simple process. Therefore, the method of the present invention can be actively applied to recent semiconductor devices, particularly to RF devices.

상기에서는 본 발명의 바람직한 실시예를 참조하여 설명하였지만, 해당 기술 분야의 숙련된 당업자는 하기의 특허 청구의 범위에 기재된 본 발명의 사상 및 영역으로부터 벗어나지 않는 범위내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

Claims (3)

제1절연막 상에 제1금속막 및 반사 방지막을 순차적으로 형성하는 단계;Sequentially forming a first metal film and an anti-reflection film on the first insulating film; 상기 반사 방지막 상에 순차적으로 적층된 제2절연막 패턴, 저항막 패턴 및 제3절연막 패턴을 형성하는 단계; Forming a second insulating film pattern, a resistance film pattern, and a third insulating film pattern sequentially stacked on the anti-reflection film; 상기 제3절연막 패턴을 갖는 결과물 상에 상기 반사 방지막의 표면을 부분적으로 노출시키는 포토레지스트 패턴을 형성하는 단계; Forming a photoresist pattern partially exposing the surface of the anti-reflection film on the resultant having the third insulating film pattern; 상기 포토레지스트 패턴을 식각 마스크로 사용한 식각으로 상기 노출된 반사 방지막 부분 및 그 하부의 제1금속막 부분을 순차적으로 식각하여 제1영역과 제2영역으로 분리된 구조를 갖는 반사 방지막 패턴 및 제1금속막 패턴을 형성하는 단계; The anti-reflection film pattern and the first anti-reflective film pattern having a structure separated into a first region and a second region by sequentially etching the exposed anti-reflection film portion and the lower first metal film portion by etching using the photoresist pattern as an etching mask. Forming a metal film pattern; 상기 식각 마스크로 사용한 포토레지스트 패턴을 제거하는 단계; Removing the photoresist pattern used as the etching mask; 상기 포토레지스트 패턴이 제거된 결과물 상에 제4절연막을 형성하는 단계; Forming a fourth insulating layer on the resultant from which the photoresist pattern is removed; 상기 제4절연막을 식각하여 제1영역에는 저항막 패턴의 표면을 부분적으로 노출시키는 제1비아홀을 갖고, 제2영역에는 저항막 패턴의 표면을 부분적으로 노출시키는 제2비아홀 및 반사 방지막 패턴의 표면을 노출시키는 제3비아홀을 갖는 제4절연막 패턴을 형성하는 단계; The fourth insulating layer is etched to have a first via hole partially exposing the surface of the resistive pattern in the first region, and a second via hole and anti-reflective layer pattern partially exposing the surface of the resistive pattern in the second region. Forming a fourth insulating film pattern having a third via hole exposing the light emitting layer; 상기 제1비아홀, 제2비아홀 및 제3비아홀 내에 금속 플러그를 형성하는 단계; 및Forming a metal plug in the first via hole, the second via hole, and the third via hole; And 상기 제4절연막 패턴 상에 상기 금속 플러그와 연결되는 제2금속막 패턴을 형성하는 단계;Forming a second metal film pattern connected to the metal plug on the fourth insulating film pattern; 를 포함하는 반도체 소자의 제조 방법.Wherein the semiconductor device is a semiconductor device. 제1항에 있어서, 상기 저항막 패턴은 금속막인 것을 특징으로 하는 반도체 소자의 제조 방법.The method of claim 1, wherein the resistive film pattern is a metal film. 제1항에 있어서, 상기 제1금속막은 알루미늄막이고, 상기 금속 플러그는 텅스텐 플러그인 것을 특징으로 하는 반도체 소자의 제조 방법.The method of claim 1, wherein the first metal film is an aluminum film, and the metal plug is a tungsten plug-in.
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KR20020081799A (en) * 2001-04-19 2002-10-30 주식회사 하이닉스반도체 Method for manufacturing of capacitor of semiconductor device
KR20030055797A (en) * 2001-12-27 2003-07-04 주식회사 하이닉스반도체 a method for manufacturing capacitor of semiconductor device
KR20040001486A (en) * 2002-06-28 2004-01-07 주식회사 하이닉스반도체 Method for forming mim capacitor
KR20040001754A (en) * 2002-06-28 2004-01-07 동부전자 주식회사 Method for manufacturing capacitor

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* Cited by examiner, † Cited by third party
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KR20020081799A (en) * 2001-04-19 2002-10-30 주식회사 하이닉스반도체 Method for manufacturing of capacitor of semiconductor device
KR20030055797A (en) * 2001-12-27 2003-07-04 주식회사 하이닉스반도체 a method for manufacturing capacitor of semiconductor device
KR20040001486A (en) * 2002-06-28 2004-01-07 주식회사 하이닉스반도체 Method for forming mim capacitor
KR20040001754A (en) * 2002-06-28 2004-01-07 동부전자 주식회사 Method for manufacturing capacitor

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