KR101037124B1 - Solar cell and manufacturing method - Google Patents

Abstract

A solar cell and a method of manufacturing the same are disclosed. Solar cell according to the invention the substrate 100; A lower electrode 200a formed on the substrate 100; An optoelectronic device portion 300a including a first polycrystalline semiconductor layer 311, a second polycrystalline semiconductor layer 312, and a third amorphous semiconductor layer 313 sequentially stacked on the lower electrode 200a; And an upper electrode 500 formed on the optoelectronic device portion 300a.

Description

SOLAR CELL AND METHOD FOR FABRICATING THE SAME

The present invention relates to a solar cell and a method of manufacturing the same. In more detail, in the stacked semiconductor layer (photoelectric element), only the semiconductor layer on the light-receiving side is formed amorphous and the other semiconductor layer is formed of polycrystal to obtain a uniform photoelectric conversion efficiency and a solar cell and a method of manufacturing the same. It is about.

In general, a thin film solar cell using amorphous silicon (a-Si) has a very low diffusion length of a carrier compared to single crystal or polycrystalline silicon due to the characteristics of the amorphous silicon material itself. Therefore, when manufactured with a pn junction structure, the collection efficiency of electron-hole pairs generated by light is very low, and when exposed to light for a long time, deterioration occurs and the photoelectric conversion efficiency decreases with time. Have

In order to solve this problem, an amorphous silicon pin structure formed between p-type and n-type having a high impurity doping concentration by using an intrinsic semiconductor layer containing no impurity as a light absorbing layer, and heat treatment at high temperature ( For example, a solar cell having a polycrystalline silicon pin structure which crystallizes to polycrystalline silicon (p-si) at 600 degrees or more) is proposed.

However, in such a polycrystalline silicon p-i-n structure, a high temperature of 600 ° C. or more is required for a long time in order to crystallize all three layers of amorphous silicon, which may cause a problem in that the substrate is deformed (for example, substrate warpage). In addition, the laminated polycrystalline silicon layer also has a limitation in that it is difficult to obtain a uniform photoelectric conversion efficiency due to a difference in the amount of light reception between layers depending on the direction in which light is received.

On the other hand, a technique has been developed to implement a good photoelectric conversion efficiency by electrically connecting a plurality of optoelectronic devices in series. Looking at a conventional solar cell of the series connection method, Figure 1 is a view showing the configuration of a conventional solar cell.

Referring to FIG. 1, a conventional solar cell is provided with a substrate 10 including a plurality of unit cell regions a ′ and a wiring region b ′ positioned between the unit cell regions a ′. In this case, the lower electrode 11 is formed in the unit cell region a` on the substrate 10, and the optoelectronic device 20 having the semiconductor layer stacked thereon is formed on the lower electrode 11.

Subsequently, the upper electrode 30 is formed on the optoelectronic device 20 to form one solar cell unit cell, and the upper electrode 30 is interconnected with an upper portion of the lower electrode 11 of another neighboring unit cell a ′. They are connected on area b` and connected electrically in series.

However, in the conventional series solar cell, when the connection between the unit cells of the solar cell is made in the wiring area b`, the side surface of the photoelectric device 20 and the upper electrode 30 are short-circuited (short circuit SC) to prevent unnecessary leakage. Current may occur. In addition, an n-type or p-type semiconductor layer having a low resistance is formed between the lower electrodes 11 of neighboring unit cells due to the doping of impurities in the semiconductor layer of the optoelectronic device 20. Circuit) may cause a decrease in the photoelectric conversion efficiency.

In particular, in the conventional solar cell, after the first pattern of the lower electrode 11 is formed by the laser scribing method, the photovoltaic device 20 is formed, and only the optoelectronic device 20 is formed by the laser scribing method. do. Subsequently, the upper electrode 30 may be formed, and the upper electrode 30 and the photoelectric device 20 may be third patterned by a laser scribing method to implement a solar cell.

Therefore, the conventional solar cell requires at least three laser scribing processes, which increases the processing time and cost, and reduces the area ratio of the unit cell area (that is, by increasing the wiring (dead) area of the solar cell). The photoelectric conversion efficiency is lowered. In this case, in the case of the third pattern, since the upper electrode 30 and the photoelectric device 20 are formed of different materials, there is a problem that it is difficult to collectively remove them by laser scribing.

Accordingly, the present invention has been made to solve the above problems of the prior art, it is possible to obtain a uniform photoelectric conversion efficiency by increasing the energy band gap of the semiconductor layer of the light receiving side in a polycrystalline optoelectronic device It is an object to provide a solar cell and a method of manufacturing the same.

Another object of the present invention is to provide a solar cell and a method of manufacturing the same, which can reduce the number of pattern processes by collectively patterning a lower electrode and a semiconductor layer.

In addition, an object of the present invention is to provide a solar cell and a method of manufacturing the same that can implement a series connection structure in a simpler and more cost-saving process by removing only the upper electrode.

The object of the present invention is a substrate; A lower electrode formed on the substrate; An optoelectronic device portion including a first polycrystalline semiconductor layer, a second polycrystalline semiconductor layer, and a third amorphous semiconductor layer sequentially stacked on the lower electrode; And an upper electrode formed on the optoelectronic device portion.

In addition, the object of the present invention is a substrate including a plurality of unit cell region and a plurality of wiring region located between the unit cell region; A lower electrode formed on the unit cell area on the substrate; A lower connection electrode formed on the wiring area on the substrate and connected to the same layer as one side of the lower electrode; An optoelectronic device portion formed on the lower electrode and including first and second polycrystalline semiconductor layers and a third amorphous semiconductor layer sequentially stacked; A dummy photoelectric device formed on the lower connection electrode in the same layer as the photoelectric device part; And an upper electrode formed on the optoelectronic device portion, the upper electrode being formed on the dummy photoelectric device at a predetermined interval and electrically connected to the optoelectronic device portion of a neighboring unit cell region. do.

In this case, the optoelectronic device portion, the upper first amorphous semiconductor layer formed on the third amorphous semiconductor layer; An upper second amorphous semiconductor layer formed on the upper first amorphous semiconductor layer; And an upper third amorphous semiconductor layer formed on the upper second amorphous semiconductor layer.

The first and second polycrystalline semiconductor layers may be p-type and i-type semiconductor layers, and the third amorphous semiconductor layer may be an n-type semiconductor layer.

The lower electrode and the optoelectronic device portion may be collectively patterned.

A sidewall insulating layer may be further formed on the wiring area on the substrate and disposed between the lower electrode and the side surface of the optoelectronic device portion and the upper electrode.

In addition, the object of the present invention is to provide a substrate; Forming a lower electrode on the substrate; Forming a first amorphous semiconductor layer on the lower electrode; forming a second amorphous semiconductor layer on the first amorphous semiconductor layer; Crystallizing the first and second amorphous semiconductor layers into first and second polycrystalline semiconductor layers; Forming a third amorphous semiconductor layer on the second polycrystalline semiconductor layer; And it is also achieved by the method of manufacturing a solar cell comprising the step of forming an upper electrode on the third amorphous semiconductor layer.

In addition, the object of the present invention is to provide a substrate including a plurality of unit cell region and a plurality of wiring region located between the unit cell region; Sequentially forming a semiconductor layer including a lower conductive layer, a first polycrystalline semiconductor layer, and a third amorphous semiconductor layer on an entire surface of the substrate; Firstly patterning the lower conductive layer and the semiconductor layer on the wiring region on the substrate; Forming an upper conductive layer on an entire surface of the substrate; And second patterning the upper conductive layer on the wiring region on the substrate.

In this case, forming an upper first amorphous semiconductor layer on the third amorphous semiconductor layer; Forming an upper second amorphous semiconductor layer on the upper first amorphous semiconductor layer; And forming an upper third amorphous semiconductor layer on the upper second amorphous semiconductor layer.

The first patterning may be performed using laser scribing.

The second patterning may be performed using laser scribing or mechanical scribing.

The first and second polycrystalline semiconductor layers may be p-type and i-type semiconductor layers, and the third amorphous semiconductor layer may be an n-type semiconductor layer.

The method may further include forming a sidewall insulating layer contacting a side surface of the patterned lower conductive layer and the patterned semiconductor layer on the wiring area on the substrate.

According to the present invention, a semiconductor layer (photoelectric element) on the side where light is received (in particular, an n-type semiconductor layer having the least resistance among p, i, and n-types) is formed amorphous to obtain good photoelectric conversion efficiency. Can be.

In addition, according to the present invention, the lower electrode and the semiconductor layer may be collectively patterned to reduce the number of pattern processes, the process time, and the process cost, and to increase the area of the unit cell region.

In addition, according to the present invention, a semiconductor layer (especially an n-type semiconductor layer having the smallest resistance among p, i, and n-type resistors) of the light-receiving side of the semiconductor layer is formed in an amorphous manner to remove only the upper electrode in series. It is possible to effectively prevent a short circuit occurring at the time of.

1 is a view showing the configuration of a conventional solar cell.
2 to 4 are views sequentially showing a manufacturing process of a solar cell according to an embodiment of the present invention.
5 is a view showing another type of solar cell according to an embodiment of the present invention.
6 to 10 are views sequentially illustrating a manufacturing process of a series solar cell according to an embodiment of the present invention.

DETAILED DESCRIPTION The following detailed description of the invention refers to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different but need not be mutually exclusive. For example, certain features, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the invention in connection with an embodiment. It is also to be understood that the position or arrangement of the individual components within each disclosed embodiment may be varied without departing from the spirit and scope of the invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention, if properly described, is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled. In the drawings, like reference numerals refer to the same or similar functions throughout the several aspects, and length, area, thickness, and the like may be exaggerated for convenience.

DETAILED DESCRIPTION Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.

Unit cell  Solar cell

2 to 4 are views sequentially showing a manufacturing process of a solar cell according to an embodiment of the present invention.

Hereinafter, for convenience of description, the solar cell on the substrate 100 will be described based on a cross section of the unit cell region a.

First, referring to FIG. 2, a substrate 100 may be provided. The material of the substrate 100 may be a transparent glass substrate, but is not limited thereto, and may be a transparent material such as glass or plastic or silicon or metal [for example, SUS (Stainless Steel) according to a direction in which solar cells receive light. All opaque materials such as)] can be used.

In this case, texturing may be performed on the surface of the substrate 100. Texturing in the present invention is intended to prevent the phenomenon that the characteristics of the light is reduced by reflecting the light incident on the substrate surface of the solar cell is optically lost. In other words, the surface of the substrate is roughened to form an uneven pattern (not shown) on the surface of the substrate. For example, if the surface of the substrate is roughened by texturing, the light reflected once from the surface may be reflected back toward the solar cell, thereby reducing the loss of light and increasing the amount of light trapping to increase the photoelectric conversion efficiency of the solar cell. Can be improved.

In this case, a sand blasting method may be used as a representative texturing method. Sand blasting in the present invention includes both dry blasting for etching by etching the etching particles with compressed air and wet blasting for etching by etching the etching particles together with the liquid. On the other hand, the etching particles used in the sand blasting of the present invention can be used without limitation, particles that can form irregularities on the substrate by physical impact, such as sand, small metal.

Subsequently, an antireflection layer (not shown) may be formed on the substrate 100. The anti-reflection layer serves to prevent a phenomenon of decreasing the efficiency of the solar cell by being reflected directly to the outside rather than being absorbed by the photovoltaic device incident to the photovoltaic device. The material of the anti-reflection layer may be silicon oxide (SiO _x ) or silicon nitride (SiN _x ), but is not limited thereto.

The method of forming the reflective ring layer may include low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), and the like.

Subsequently, a lower electrode 200a of a conductive material may be formed on the substrate 100. The material of the lower electrode 200a may be any transparent or opaque conductive material depending on the direction in which light is received. For example, TCO (Transparent Conductive Oxide), which is a transparent electrode having a low contact resistance and having a transparent property, may be used. For example, AZO (ZnO: Al), ITO (Indium-Tin-Oxide), or GZO (ZnO: Ga ), BZO (ZnO: B), and SnO ₂ (SnO ₂ : F). In addition, any one of opaque molybdenum (Mo), tungsten (W), molybdenum tungsten (MoW) or an alloy thereof may be included.

The lower electrode 200a may be formed by physical vapor deposition (PVD), LPCVD, PECVD, metal organic chemistry such as thermal evaporation, E-beam evaporation, sputtering, or the like. Chemical Vapor Deposition (CVD), such as Metal Organic Chemical Vapor Deposition (MOCVD).

Meanwhile, a reflective layer (not shown) of a transparent conductive material may be further formed on the lower electrode 200a. That is, the reflective layer is positioned between the lower electrode 200a and the semiconductor layer 300 to be formed later (meaning the optoelectronic device portion 300a in the unit cell region). The reflective layer may improve the photoelectric conversion efficiency of the solar cell by reflecting sunlight incident from the upper side of the substrate 100 while being electrically connected to the lower electrode 200a. The reflective layer is preferably AZO (ZnO: Al) in which Al is added to ZnO, but is not limited thereto. Indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), SnO may include a small amount of FSO (SnO: F) doped with F. The method of forming the reflective layer may include physical vapor deposition such as sputtering and chemical vapor deposition such as LPCVD, PECVD, and MOCVD.

In addition, the surface of the lower electrode 200a may be textured as described above in order to improve photoelectric conversion efficiency of the solar cell, similar to the surface of the substrate 100.

Subsequently, the semiconductor layer 300 having p-type and n-type conductivity may be stacked on the lower electrode 200a, or the p-type, i-type, and n-type semiconductor layers 300 may be stacked. An embodiment of the present invention will be described assuming that p-type, i-type, and n-type silicon layers 300: 311, 312, and 313 are stacked as silicon (Si) that is commonly used as an example. At this time, the silicon layer on the light-receiving side of the silicon layer 300 may be formed of amorphous silicon, and the other silicon layer may be formed of polycrystalline silicon. In particular, n-type having the smallest resistance among p, i, and n-types It may be desirable to form the silicon layer from amorphous silicon.

This is because the light-receiving rate of the i-type and p-type silicon layers received later than the n-type silicon layer where light is received first is lowered, so that the energy band gap of the n-type silicon layer having the smallest energy band gap (amorphous silicon layer than the polycrystalline silicon layer) The energy band gap of the large) can be increased to make the photoelectric conversion efficiency between the silicon layers uniform.

In more detail, the first amorphous silicon layer 311a may be formed on the lower electrode 200a, and then the second amorphous silicon layer 312a may be formed on the first amorphous silicon layer 311a. The first and second amorphous silicon layers 311a and 312a may be formed using a chemical vapor deposition method such as PECVD or LPCVD.

Next, referring to FIG. 3, the first and second amorphous silicon layers 311a and 312a may be crystallized. That is, the first amorphous silicon layer 311a may be crystallized into the first polycrystalline silicon layer 311 and the second amorphous silicon layer 312a may be crystallized into the second polycrystalline silicon layer 312.

In this case, the method of crystallizing amorphous silicon is any one of solid phase crystallization (SPC), excimer laser annealing (ELA), sequential lateral solidification (SLS), metal induced crystallization (MIC), and metal induced lateral crystallization (MIL) Can be used. Since the crystallization method of the amorphous silicon is a known technique, a detailed description thereof will be omitted herein.

In the above description, the lower first and second amorphous silicon layers 311a and 312a are formed, and the layers are simultaneously crystallized, but the present invention is not limited thereto. For example, a crystallization process may be performed separately for each lower amorphous silicon layer.

In addition, the defect removal process may be further performed on the first polycrystalline silicon layer 311 and the second polycrystalline silicon layer 312 in order to further improve various characteristics of the polycrystalline silicon layer. In the present invention, the polycrystalline silicon layer may be subjected to high temperature heat treatment or hydrogen plasma treatment to remove defects (eg, impurities and dangling bonds) present in the polycrystalline silicon layer.

Next, referring to FIG. 4, an amorphous silicon layer 313 may be formed on the second polycrystalline silicon layer 312. As a result, the optoelectronic device portion 300a including one optoelectronic device including the first and second polycrystalline silicon layers and the third amorphous silicon layers 311, 312, and 313 may be formed on the lower electrode 200a. . Such an optoelectronic device may have a structure of a p-i-n diode in which p-type, i-type, and n-type polycrystalline silicon layers, which may generate power with photovoltaic power generated by receiving light, are sequentially stacked. Where i means intrinsic without impurities.

On the other hand, n-type or p-type doping is preferably doped in the in situ (in situ) method when forming the amorphous silicon layer. It is common to use boron (B) as an impurity in P-type doping and phosphorus (P) or arsenic (As) as an impurity in n-type doping, but it is not limited to this, and well-known techniques can be used without limitation.

Subsequently, an upper electrode 500 of a transparent conductive material may be formed on the third amorphous semiconductor layer 313. The material of the upper electrode 500 is preferably one of ITO, ZnO, IZO, AZO (ZnO: Al), and FSO (SnO: F), but is not necessarily limited thereto. The method of forming the upper electrode 500 may include a physical vapor deposition method such as sputtering and a chemical vapor deposition method such as LPCVD, PECVD, and MOCVD.

Tandem  Solar cell

5 is a view showing another type of solar cell according to an embodiment of the present invention.

Another optoelectronic device may be further formed on the optoelectronic device 310 including the first, second polycrystalline silicon layer and the third amorphous silicon layer 311, 312, and 313 described above. It may be an amorphous optoelectronic device 320 in which a silicon layer is stacked. As described above, according to the exemplary embodiment of the present invention, the optoelectronic device portion 300a in which the optoelectronic devices 310 and 320 have a tandem structure may be implemented. On the other hand, such a tandem structure may mean a multi-junction structure in which the photoelectric device is stacked in triple or more.

Referring to FIG. 5, an upper first amorphous silicon layer 321 is formed on the third amorphous silicon layer 313, and then an upper second amorphous silicon layer 322 is formed on the upper first amorphous silicon layer 321. Subsequently, an upper third amorphous silicon layer 323 is formed on the upper second amorphous silicon layer 322 to form an amorphous photoelectric device 320 having a pin diode structure. In this case, the upper first, second, and third amorphous silicon layers 321, 322, and 323 may be formed using chemical vapor deposition such as PECVD or LPCVD.

As a result, the optoelectronic device portion including the optoelectronic device 310 made of the polycrystalline silicon layer and the amorphous silicon layer and the amorphous optoelectronic device 320 made of only the amorphous silicon layer is employed in the tandem solar cell according to an embodiment of the present invention. 300a can be obtained.

Although not shown, a connection layer of a transparent conductive material may be further formed between the third amorphous silicon layer 313 and the upper first amorphous silicon layer 321. In this connection layer, a tunnel junction is formed between the third amorphous silicon layer 313 and the upper first amorphous silicon layer 321, so that better photoelectric conversion efficiency of the solar cell can be expected. The material of the connection layer is preferably any one of ITO, ZnO, IZO, AZO (ZnO: Al), FSO (SnO: F), but is not necessarily limited thereto. The formation method of the connection layer may include a physical vapor deposition method such as sputtering and a chemical vapor deposition method such as LPCVD, PECVD, and MOCVD.

Series connected solar cell

In the present specification, the unit cell region (a) refers to a region in which a photoelectric device (semiconductor layer) is positioned in the solar cell to perform photoelectric conversion.

In addition, in the present specification, the wiring area (b) refers to an area that is located between the unit cell areas (a) and performs a function of electrically connecting (eg, a series connection method) while separating the unit cells. Meaning, it can be understood as a dead region since substantially no photoelectric conversion occurs.

In the following detailed description, a configuration and a manufacturing method of a series-connected solar cell including a plurality of solar cell unit cells according to an embodiment of the present invention described above will be described. In this case, the configuration of the unit cell region a of the series-connected solar cell is the same as that of the unit cell solar cell. Therefore, detailed description of components included in the unit cell area a is omitted in order to avoid duplication of description.

6 to 10 are views sequentially illustrating a manufacturing process of a series solar cell according to an embodiment of the present invention.

First, referring to FIG. 6, a substrate 100 including a plurality of unit cell regions a and a plurality of wiring regions b positioned between the unit cell regions a may be provided.

Subsequently, a lower conductive layer 200 of a conductive material may be formed on the substrate 100. The lower conductive layer 200 may be formed of the same material and method as the lower electrode 200a of the solar cell.

Subsequently, the silicon layer 300 including the first and second polycrystalline silicon layers and the third amorphous silicon layers 311, 312, and 313 may be formed on the entire upper surface of the lower conductive layer 200. The silicon layer 300 may be formed of the same material and method as the photoelectric device unit 300a of the solar cell.

Next, referring to FIG. 7, the lower conductive layer 200 and the silicon layer 300 are collectively first patterned 10 in the wiring region b to form a predetermined unit pattern separated from each other (isolated). Can be.

The first patterning 10 may be performed using a laser scribing method, which is an etching method using a laser light source. The laser may use an infrared ray-nanosecond (IR-ns) or infrared ray-picosecond (IR-ps) laser. Patterning may be simultaneously performed through a mechanism for popping the silicon layer 300 during blow-up of the lower conductive layer 200 by laser irradiation. In this case, the irradiation direction of the laser may be irradiated directly from the top, it may be irradiated from the bottom through the substrate 100. However, the present invention is not limited thereto, and an etching method including a known photolithography method may be used without limitation.

In the following description, the patterned lower conductive layer 200 is a lower electrode 200a on the unit cell region a and the lower connection electrode 200b on the wiring region b in order to be equivalently described with the driving circuit of the solar cell. Explain separately. In the same principle, the patterned silicon layer 300 is divided into the optoelectronic device portion 300a on the unit cell region a and the dummy photoelectric device 300b on the wiring region b.

The photoelectric device unit 300a generates photovoltaic power (power) while electrons and holes generated by receiving light move to the lower electrode 200a and the upper electrode 500 to be formed later. On the other hand, the dummy photoelectric device 300b is electrically separated from the photoelectric device unit 300a (the upper electrode is patterned) by a subsequent process (see FIG. 10), thereby substantially preventing power generation.

The lower connection electrode 200b has a function of connecting the lower electrode 200a of the unit cell region a with the upper electrode 500 of another unit cell region a adjacent thereto to implement a series connection structure of a solar cell. Can be performed.

Next, referring to FIG. 8, a sidewall insulating layer 400 may be formed on the side surfaces of the optoelectronic device portion 300a and the lower electrode 200a and the wiring area b. The sidewall insulating layer 400 may be any one of a silicon nitride film (SiN _x ) or a silicon oxide film (SiO _x ) or a laminated film thereof. In addition, the sidewall insulating layer 400 may be various known materials such as resin and polymer. By the sidewall insulating layer 400, good electrical insulating properties between solar cell unit cells may be obtained.

The method of forming the sidewall insulating layer 400 may use ink jet printing in which ink is sprayed through a head configured as a nozzle, but is not limited thereto, and the photolithography method is not limited thereto. Can be used.

Next, referring to FIG. 9, an upper conductive layer 510 made of a conductive material may be formed on the entire upper surface of the substrate 100. The material of the upper conductive layer 510 may be formed of the same material and method as the upper electrode 500 of the solar cell described above.

Next, referring to FIG. 10, only the upper conductive layer 510 on the wiring area b may be second patterned 20 to form the upper electrode 500 and the dummy photoelectric device 300b, respectively.

The second patterning 20 may be performed using a laser scribing method, which is an etching method using a laser light source. In this case, the irradiation direction of the laser may be directly irradiated directly on the substrate 100. . In addition, in the present invention, the second patterning 20 may be performed by using a mechanical scribing method instead of the laser scribing method, in which a known mechanical scribing method may be used without limitation. Can be. However, the present invention is not limited thereto, and an etching method including a known photolithography method may be used without limitation.

In more detail, by removing only the upper conductive layer 510, the second patterning 20 process and the series connection structure of the solar cell can be simplified. Meanwhile, the upper electrode 500 is formed on the optoelectronic device portion 300a, and is formed on the dummy photoelectric device 300b at regular intervals by the second patterning 20 so that the adjacent unit cell regions a are adjacent to each other. May be electrically connected in series with the optoelectronic device portion 300a.

At this time, the dummy photoelectric device 300b is formed on the lower connection electrode 200b in the same layer as the photoelectric device part 300a and is physically the same layer, but since the upper electrode 500 is electrically patterned, the photoelectric device part It can be interpreted as being electrically isolated from 300a.

In addition, the upper electrode 500 may function as an electrode of the optoelectronic device portion 300a on the unit cell region a, and another optoelectronic device portion adjacent to the optoelectronic device portion 300a on the wiring region b. The wire may be connected to the 300a (ie, to connect the solar cell unit cells in series). In the present invention, the upper surface of the lower connection electrode 200b of the other wiring region b adjacent to the upper surface of the photoelectric device portion 300a of the unit cell region a is electrically connected through the upper electrode 500.

As described above, the solar cell according to the exemplary embodiment of the present invention may reduce the number of pattern processes compared to the conventional three times by performing only two pattern processes 10 and 20 in total. That is, since the solar cell of the present invention patterns the lower conductive layer 200 and the silicon layer 300 collectively, the area of the unit cell region a is relatively increased (that is, the wiring (dead) region b). ) Area can be reduced], excellent photoelectric conversion efficiency can be obtained.

In addition, only the upper electrode 500 may be removed to simplify the manufacturing process and the series connection structure of the solar cell, and at the same time, it may effectively prevent a short circuit occurring when the series connection is performed in the related art. This is because an n-type semiconductor layer having a lower energy band gap and a lower resistance than a relatively conductive polycrystalline silicon layer is formed of an n-type amorphous semiconductor layer having a large energy band gap and a high resistance.

As a result, in the present invention, by forming an amorphous n-type silicon layer having a relatively low resistance among the dummy photoelectric device 300b, a series connection structure of a solar cell can be implemented in a simple and cost-saving manner without patterning the silicon layer. have.

In the foregoing detailed description, the present invention has been described by specific embodiments such as specific components and the like, but the embodiments and drawings are provided only to help a more general understanding of the present invention, and the present invention is limited to the above embodiments. However, one of ordinary skill in the art can make various modifications and variations from this description. Therefore, the spirit of the present invention should not be construed as being limited to the above-described embodiments, and all of the equivalents or equivalents of the claims, as well as the following claims, I will say.

100: substrate
200: lower conductive layer
200a: lower electrode
200b: lower connection electrode
300: semiconductor layer (silicon layer)
300a: photoelectric element
300b: dummy photoelectric device
310: photoelectric device
311: first polycrystalline silicon layer
312: second polycrystalline silicon layer
313: third amorphous silicon layer
320: amorphous photoelectric device
400: sidewall insulation layer
500: upper electrode
510: upper conductive layer

Claims (13)

Board;
A lower electrode formed on the substrate;
An optoelectronic device portion including a first polycrystalline semiconductor layer, a second polycrystalline semiconductor layer, and a third amorphous semiconductor layer sequentially stacked on the lower electrode; And
An upper electrode formed on the optoelectronic device portion
Solar cell comprising a. A substrate including a plurality of unit cell regions and a plurality of wiring regions positioned between the unit cell regions;
A lower electrode formed on the unit cell area on the substrate;
A lower connection electrode formed on the wiring area on the substrate and connected to the same layer as one side of the lower electrode;
An optoelectronic device portion formed on the lower electrode and including first and second polycrystalline semiconductor layers and a third amorphous semiconductor layer sequentially stacked;
A dummy photoelectric device formed on the lower connection electrode in the same layer as the photoelectric device part; And
An upper electrode formed on the optoelectronic device portion, the upper electrode being formed on the dummy photoelectric device at a predetermined interval and electrically connected to the optoelectronic device portion of a neighboring unit cell region
Solar cell comprising a. The method according to claim 1 or 2,
The optoelectronic device portion,
An upper first amorphous semiconductor layer formed on the third amorphous semiconductor layer;
An upper second amorphous semiconductor layer formed on the upper first amorphous semiconductor layer; And
An upper third amorphous semiconductor layer formed on the upper second amorphous semiconductor layer
Solar cell further comprising a. The method according to claim 1 or 2,
The first and second polycrystalline semiconductor layers are p-type and i-type semiconductor layers, and the third amorphous semiconductor layer is an n-type semiconductor layer. The method of claim 2,
And the lower electrode and the optoelectronic device portion are collectively patterned. The method of claim 2,
And a sidewall insulating layer disposed on the wiring region on the substrate and positioned between the side surface of the lower electrode and the optoelectronic device portion and the upper electrode. Providing a substrate;
Forming a lower electrode on the substrate;
Forming a first amorphous semiconductor layer on the lower electrode;
Forming a second amorphous semiconductor layer on the first amorphous semiconductor layer;
Crystallizing the first and second amorphous semiconductor layers into first and second polycrystalline semiconductor layers;
Forming a third amorphous semiconductor layer on the second polycrystalline semiconductor layer; And
Forming an upper electrode on the third amorphous semiconductor layer
Method for manufacturing a solar cell comprising a. Providing a substrate including a plurality of unit cell regions and a plurality of wiring regions positioned between the unit cell regions;
Sequentially forming a semiconductor layer including a lower conductive layer, a first polycrystalline semiconductor layer, and a third amorphous semiconductor layer on an entire surface of the substrate;
Firstly patterning the lower conductive layer and the semiconductor layer on the wiring region on the substrate;
Forming an upper conductive layer on an entire surface of the substrate; And
Second patterning the upper conductive layer on the wiring region on the substrate
Method for manufacturing a solar cell comprising a. The method according to claim 7 or 8,
Forming an upper first amorphous semiconductor layer on the third amorphous semiconductor layer;
Forming an upper second amorphous semiconductor layer on the upper first amorphous semiconductor layer; And
Forming an upper third amorphous semiconductor layer on the upper second amorphous semiconductor layer
Method for manufacturing a solar cell further comprising a. The method of claim 8,
The first patterning method of manufacturing a solar cell, characterized in that performed using laser scribing. The method of claim 8,
The second patterning method of manufacturing a solar cell, characterized in that performed using laser scribing or mechanical scribing. The method according to claim 7 or 8,
The first and second polycrystalline semiconductor layers are p-type and i-type semiconductor layers, and the third amorphous semiconductor layer is an n-type semiconductor layer. The method of claim 8,
And forming a sidewall insulating layer in contact with a side surface of the patterned lower conductive layer and the patterned semiconductor layer on the wiring region on the substrate.

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