KR101030524B1 - Manufacturing Method of TFT Array Substrate - Google Patents

Abstract

The present invention is to reduce the burden on the use of the stripper and to simplify the process by forming an overcoat layer through a non-exposure process, such as the Detachment Method (Flowing Method) and the Flowing Method that does not require the use of a stripper A method of manufacturing a TFT array substrate, the method comprising: forming a gate wiring and a gate electrode on a substrate; forming a gate insulating film on the entire surface including the gate wiring; and forming an active layer on the gate insulating film on the gate electrode. Forming a data line; forming a data line perpendicular to the gate line and a source / drain electrode branched from the data line; forming a protective film on the entire surface including the data line; After applying the layer, the contact hole was formed by a flow method or a detachment method. Comprising the steps of: sex, it characterized in that the step of removing the protective film that is exposed through the contact hole, to the top overcoat layer comprises a step of forming a pixel electrode which contacts the drain electrode through the contact hole.

Overcoat Layer, Stripper, Detachment Method, Flowing Method

Description

Method for Fabricating The Array Substrate Of Thin Film Transistor

1A to 1C are process cross-sectional views of a TFT array substrate according to the prior art.

2A to 2E are cross-sectional views illustrating a method of manufacturing a TFT array substrate according to the present invention.

3A to 3E are cross-sectional views illustrating a detachment method.

4A to 4E are process cross-sectional views illustrating the flow method.

* Explanation of symbols on the main parts of the drawings

111 substrate 112a gate electrode

113: gate insulating film 114: active layer

115: data wiring 115a: source electrode

115b: data electrode 116: protective film

117: pixel electrode 118: overcoat layer

120: contact hole 190: mold frame

280: pressure roller

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device (LCD), and more particularly, to a method of manufacturing a TFT array substrate for a liquid crystal display device, characterized by patterning an overcoat layer without using a stripper.

BACKGROUND ART Liquid crystal display devices, which have recently been spotlighted as flat panel display devices, have been actively researched due to their high contrast ratio, suitable for gradation display or moving picture display, and low power consumption.

In particular, it can be manufactured with a thin thickness so that it can be used as an ultra-thin display device such as a wall-mounted TV in the future, and is light in weight and consumes significantly less power than a CRT CRT. It is being used as a next generation display device.

In general, the liquid crystal display device includes a thin film transistor array substrate having a thin film transistor (TFT) and a pixel electrode formed in each pixel region defined by a gate wiring and a data wiring, and a color filter layer array substrate having a color filter layer. Arranged so as to face each other, a liquid crystal having dielectric anisotropy is formed therebetween, and a voltage is applied to the pixel by switching a thin film transistor added to hundreds of thousands of pixels through a pixel selection address wiring. It is driven in a way.

Hereinafter, a manufacturing method of a TFT array substrate for a liquid crystal display device according to the prior art will be described with reference to the accompanying drawings.                         

1A to 1C are process cross-sectional views of a TFT array substrate according to the prior art.

First, as shown in FIG. 1A, after depositing a low resistance metal material on the glass substrate 11, a plurality of gate wiring layers, that is, gate wirings (not shown) and gate electrodes 12a using photolithography techniques, are deposited. ) And the storage lower electrode 32.

Next, an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx) is deposited at a high temperature on the entire surface including the gate wiring 12 to form a gate insulating layer 13.

Subsequently, an island shape semiconductor layer 14 is formed on the gate insulating layer 13 so as to overlap the gate electrode 12a.

In this case, the gate insulating layer 13 and the semiconductor layer 14 are usually deposited by plasma enhanced chemical vapor deposition (PECVD).

Subsequently, a low resistance metal material is deposited on the entire surface including the semiconductor layer 14 and patterned by photolithography to form a data wiring layer. The data wiring layer includes a data wiring 15 intersecting the gate wiring 12 to define a unit pixel region, and a source electrode 15a and a drain electrode 15b overlapping edges of the semiconductor layer 14. do.

The gate electrode 12a, the gate insulating layer 13, the semiconductor layer 14, and the source / drain electrodes 15a and 15b stacked as described above may include a thin film transistor that controls on / off of a voltage applied to a unit pixel. The thin film transistor is formed at an intersection point of the gate line 12 and the data line 15.

Next, a protective film 16 is formed by depositing an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx) at a high temperature on the entire surface including the data line 15.

As shown in FIG. 1B, an organic insulating material such as BCB or acrylic resin is coated on the protective layer 16 to form an overcoat layer 18 to planarize the surface. Subsequently, the photoresist 19 having photosensitive properties is applied thereon, and then the photoresist is exposed by selectively irradiating light with a mask having a specific pattern formed on the photoresist.

Next, the photoresist 19 is patterned by removing the photoresist of the lighted portion using a developer, and the drain electrode is sequentially removed by removing the overcoat layer 18 and the protective film 16 of the exposed portions between the patterned photoresist. A contact hole 20 is formed in which 15b is exposed.

As described above, after the contact hole 20 is formed by a photoetching technique using an exposure apparatus, the photoresist 19 is stripped using a stripper.

Subsequently, as shown in FIG. 1C, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited on the entire surface including the overcoat layer 18 and patterned by using photoetch technology. The pixel electrode 17 is electrically connected to the drain electrode 15b through the contact hole 20. In this case, the pixel electrode 17 is formed to overlap the storage lower electrode 32 to form a storage capacitor.                         

This completes the TFT array substrate.

The manufacturing method of the TFT array substrate according to the prior art has the following problems.

That is, when the pattern is formed by the photoetching technique, the photoresist must be stripped, but the photoresist is not easily stripped by the mass produced stripper.

In addition, such a problem occurs not only in the photo etching technique but also in the patterning process by the printing technique, since the printing technique includes the process of stripping the resist.

In order to solve the above problems, the present invention forms an overcoat layer through a non-exposure process such as a detachment method and a flow method, which eliminates the need for using a stripper. It is an object of the present invention to provide a method of manufacturing a TFT array substrate, which is intended to reduce the burden and simplify the process.

A method of manufacturing a TFT array substrate of the present invention for achieving the above object comprises the steps of forming a gate wiring and a gate electrode on the substrate, forming a gate insulating film on the front surface including the gate wiring, and the gate electrode Forming an active layer on an upper gate insulating layer, forming a data line perpendicular to the gate line and a source / drain electrode branched from the data line, and forming a protective film on the entire surface including the data line Forming a contact hole by applying an overcoat layer on the passivation layer, followed by a flow method or a detachment method, and removing the passivation layer exposed through the contact hole; Forming a pixel electrode contacting the drain electrode through the contact hole; It is characterized by.

As described above, the present invention is characterized by patterning the overcoat layer without using a stripper by forming the overcoat layer through a non-exposure process such as a detachment method or a flow method.

As described above, in order to secure the reliability of the back-channel, a liquid crystal display in which a protective film is formed of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) on a thin film transistor and an overcoat layer is formed thereon. The present invention is particularly applicable to the device, but of course, the present invention may be applied to any liquid crystal display device in which an overcoat layer patterning is required.

Hereinafter, a method of manufacturing a TFT array substrate for a liquid crystal display device according to the present invention will be described in detail with reference to the accompanying drawings.

2A to 2E are process cross-sectional views of the TFT array substrate according to the present invention, and Figs. 3A to 3E are process cross-sectional views showing the detachment method, and Figs. 4A to 4E are process cross-sectional views showing the flow method.

First, as shown in FIG. 4A, copper (Cu), aluminum (Al), and aluminum alloy (AlNd) having low resistivity of 15 μΩcm ⁻¹ or less for preventing signal delay on the transparent and excellent heat resistant substrate 111. : Gate wiring by depositing and patterning a first low resistance metal layer such as aluminum neodymium, molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta), and molybdenum-tungsten (MoW) The gate electrode 112a and the storage lower electrode 132 are formed.

Next, an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) is deposited on the entire surface including the gate electrode 112a by PECVD to form a gate insulating layer 113.

Subsequently, the semiconductor layer 114 is formed by sequentially depositing amorphous silicon (a-Si) and an ohmic contact layer (n + a-Si) in which impurities are implanted into the amorphous silicon on the entire surface of the gate insulating layer 113. The second low resistance metal layer 125, which is a data wiring material, is deposited thereon.

After applying a photoresist 152, which is a UV curable resin, to the second low resistance metal layer 125, a diffraction pattern is formed on the photoresist 152. The mask is exposed by exposure to UV or x-ray wavelength, and then the exposed photoresist 152 is developed.

In this case, a diffraction mask is used to have the pattern of the photoresist 152 have a double step, and the photoresist between the source electrode (115a in FIG. 4B) and the drain electrode (115b in FIG. 4B) to be formed later. Has a lower step.                     

Next, after collectively etching the second low resistance metal layer 125 and the active layer 114 exposed between the photoresist 152, the photoresist 152 until the low stepped photoresist 152 is removed. Ashing

The second low resistance metal layer 125 partially exposed between the photoresist 152 is etched. In this case, n + a-Si, which is an ohmic contact layer, may be simultaneously etched.

As a result, as shown in FIG. 4B, a data line (not shown) perpendicular to the gate line, source / drain electrodes 115a and 115b formed on the gate electrode 112a, and the source / The semiconductor layer 114 disposed under the drain electrodes 115a and 115b is formed.

The thin film transistor TFT may include a stacked layer of the gate electrode 112a, the gate insulating layer 113, the semiconductor layer 114, and the source / drain electrodes 115a and 115b.

Subsequently, after the remaining photoresist is stripped, an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) is deposited on the entire surface including the data line 115 to form a protective film 116.

As such, the reason why the inorganic insulating material is used as the passivation layer 116 is to ensure the reliability of the channel layer of the semiconductor layer 114.

That is, the back-channel layer in which the channel layer is exposed to the outside may adversely affect the thin film transistor characteristics due to unstable energy states and etching residues, so that an inorganic insulating material such as silicon nitride or silicon oxide is deposited to form a protective film. do. The inorganic insulating material has high transmittance, moisture resistance, and durability characteristics to protect the channel layer from moisture or scratch resistance that may occur in subsequent processes.

Next, as shown in Figure 4c, the front surface including the protective film 116

The overcoat layer 118 is formed by applying an organic insulating material such as benzocyclobutene (BCB) or acryl resin, by a spin method, a roll coating method, or the like. The overcoat layer material as described above has a high opening ratio characteristic and has a feature that can be transferred to a soft mold frame, but there is a problem in that it is not removed from a stripper in mass production.

Thus, the present invention proposes to pattern the overcoat layer 118 without using strippers. Thus, it is not necessary to develop a new overcoat layer material that is removed by the current mass-producing stripper or develop a new stripper that can remove the current overcoat layer.

That is, the soft mold frame 190 having the relief formed on the overcoat layer 118 is pressurized, and then the overcoat layer 118 is transferred to the mold frame 190 to be patterned. As described above, the overcoat layer 118 may be exposed and patterned without developing (strip) using a stripper.

Thereafter, the protective film 116 exposed between the patterned overcoat layer 118 is dry etched to form a contact hole 120 through which a predetermined portion of the drain electrode 115b is exposed, as shown in FIG. 4D. .

Here, look at the patterning process of the overcoat layer by the detachment method in more detail as follows.

First, as shown in FIG. 5A, after the protective film 116 is deposited on the substrate 111, the overcoat layer 118 is applied, and then about 60 to 70 to remove the solvent of the overcoat layer 118. Dry at C and solidify.

After the overcoat layer 118 is solidified to some extent, as shown in FIGS. 5B and 5C, the soft mold frame 190 is disposed on the overcoat layer 118 and then pressed by the pressure roller 280. . At this time, while applying heat to the overcoat layer 118 to create fluidity, the overcoat layer 118 in contact with the relief of the mold frame 190 to be adsorbed to the mold frame 190.

Therefore, when the mold frame 190 is removed, only the overcoat layer 118 of the portion corresponding to the intaglio of the mold frame 190 remains, as shown in FIG. 5D. That is, the portion corresponding to the relief of the mold frame 190 becomes the contact hole 120.

Finally, as shown in FIG. 5E, the contact hole 120 is completed by removing the protective layer 116 exposed between the overcoat layer 118 as a mask.

As described above, the detachment method is a method of patterning the overcoat layer by adsorbing the solidified overcoat layer on the relief of the mold frame. The process is simplified and the unit cost is greatly reduced by not using an exposure apparatus including a mask. The advantage is that the overcoat layer can be patterned without the use of a stripper.

On the other hand, the overcoat layer 116 can also be patterned by a flow method without using a stripper. Looking at the patterning process by the flow method in more detail as follows.

First, as shown in FIG. 6A, after the protective film 116 is deposited on the substrate 111, an overcoat layer 118 of the liquid polymer precursor type is coated thereon.

6b and 6c, the mold frame 190 is disposed on the liquid overcoat layer 118 and then pressed downward. At this time, the liquid overcoat layer 118 positioned at the embossed portion of the mold frame 190 flows into the intaglio portion of the mold frame 190. Thereafter, the overcoat layer 118 is cross-linked by baking by heating or curing by irradiating UV rays.

Thereafter, as shown in FIG. 6D, when the mold frame 190 is removed, the overcoat layer 118 remains only in a portion corresponding to the intaglio of the mold frame 190, and thus the contact hole may be formed in the portion corresponding to the relief. 120) is formed.

Finally, as shown in FIG. 6E, when the protective layer 116 exposed between the overcoat layer 118 is removed as a mask, the contact hole 120 exposing the drain electrode is completed.

As such, the flow method is a method in which a liquid overcoat layer flows into the intaglio of the mold frame to complete the pattern. The process is simplified and the unit cost is greatly reduced by not using an exposure apparatus including a mask. There is an advantage in that the overcoat layer can be patterned without having to.

For reference, as the mold frame used in the detachment method and the flow method, it is preferable to use a material having elastic properties such as PDMS (Poly Demethyl Siloxane), PU (Poly Urethane), etc. It is not limited to this.

After forming the contact hole 120 exposing the drain electrode 115b, as shown in FIG. 4D, indium tin oxide (ITO) or indium tin oxide (IZO) is formed on the entire surface including the overcoat layer 118. A transparent conductive film such as zinc oxide is deposited by a sputtering method, and then patterned by a photoetch process to form a pixel electrode 117 connected to the drain electrode 115b through the contact hole 120.

The pixel electrode 117 may overlap the upper portion of the storage lower electrode 132 to form a storage capacitor. The storage capacitor maintains the voltage charged in the liquid crystal capacitor in the turn-off period of the corresponding thin film transistor in order to prevent image quality deterioration due to parasitic capacitance.

This makes it possible to complete a thin film array substrate without using a stripper for removing the overcoat layer.

Although not shown, the thin film array substrate having the structure has a liquid crystal layer bonded to the opposite substrate and disposed between the two substrates. The opposite substrate includes a black matrix for preventing light leakage and an R, G between the black matrix. And a color filter layer in which B color resists are formed in a predetermined order, an overcoat layer for protecting the color filter layer on the color filter layer and planarizing the surface of the color filter layer, and a pixel electrode formed on the overcoat layer. In addition, a common electrode for forming an electric field is formed.                     

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

That is, the technical concept is applicable to a thin film transistor array substrate in various modes, such as twisted nematic (TN), inplane switting (IPS), and vertical alias (VA) mode.

The method of manufacturing a TFT array substrate of the present invention as described above has the following effects.

By applying non-exposure processes such as the Detachment Method and the Flowing Method to pattern the overcoat layer, the overcoat layer can be patterned without using a stripper.

Thus, there is no need to develop a new overcoat layer material that is stripped by the current mass-produced stripper, or a new stripper capable of removing the current mass-produced overcoat layer.

As a result, the burden on the stripper can be reduced, and the material cost can be reduced.

In addition, by patterning the overcoat layer without using an exposure apparatus, the process simplification lowers the probability of process error and reduces the process cost due to mask fabrication.

Claims (6)

Forming a gate wiring and a gate electrode on the substrate; Forming a gate insulating film on the entire surface including the gate wiring; Forming an active layer on the gate insulating layer on the gate electrode; Forming a data line perpendicular to the gate line and a source / drain electrode branched from the data line; Forming a protective film on the entire surface including the data line; Forming a contact hole by applying an overcoat layer on the passivation layer by a flow method or a detachment method; Removing the protective film exposed through the contact hole; And forming a pixel electrode contacting the drain electrode through the contact hole on the overcoat layer, wherein the removal method comprises: depositing an etch layer and an etch resist on a substrate, and forming the etch resist. Solidifying, adsorbing the etch resist to the relief of the mold frame by heating while contacting the relief of the etch resist and the mold frame, removing the etching layer between the etch resist after removing the mold frame, and Removing the etch resist; The method of claim 1, wherein the protective film is formed of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx). delete The method of claim 1, The flow method, Depositing an etched layer and an etch resist on the substrate, Pressurizing and then placing a mold frame on the etch resist; Curing the etch resist; Removing the etching layer between the etch resist after removing the mold frame; And removing the etch resist. The method of claim 1, wherein the overcoat layer is formed of an organic insulating material such as benzocyclobutene (BCB) or acryl resin. The method of manufacturing a TFT array substrate according to claim 1, wherein a thin film transistor comprising said gate electrode, a gate insulating film, a semiconductor layer, and a source / drain electrode is formed at the intersection of said gate wiring and data wiring.

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