KR101024253B1 - Delayed fixed loop circuit and its driving method - Google Patents

Abstract

A technique related to a delay locked loop circuit capable of correcting a duty ratio is disclosed. According to this technique, the common control unit for selecting one of the comparison signal and the detection signal in response to the operation control signal and outputs the delay control signal; A delay unit delaying an external clock in response to the delay control signal to output first and second internal clocks, and controlling a delay amount of the first internal clock only in an enable period of the operation control signal; A phase comparator for comparing the phases of the external clock and the feedback clock to output the comparison signal; A replica unit configured to receive the first internal clock and output the feedback clock; And correcting the duty ratios of the first and second internal clocks according to the difference between the delay amounts of the first and second internal clocks to output the first and second corrected internal clocks, and the first and second compensation internal clocks. And a duty ratio correction circuit configured to detect a duty ratio of a clock and output the detection signal.

Duty ratio, locking, feedback clock

Description

DELAY LOCKED LOOP CIRCUIT AND THE METHOD FOR OPERATING THE SAME}

The present invention relates to a delay locked loop circuit and a driving method thereof, and more particularly, to a delay locked loop circuit capable of correcting a duty ratio and a driving method thereof.

1 is a configuration diagram of a delay locked loop circuit for correcting a duty ratio in the related art.

As shown in FIG. 1, the conventional delay lock loop circuit includes a delay lock 101 and a duty ratio correction circuit 115.

The delay fixing unit 101 outputs the first and second internal clocks CLK_OUT1 and CLK_OUT2 by delaying the external clock EXT_CLK. The delay fixing unit 101 further outputs a second internal clock CLK_OUT2 for the duty ratio correction operation of the duty ratio correction circuit 115. The duty ratio correction circuit 115 is enabled or disabled in response to predetermined edges of the first and second internal clocks CLK_OUT1 and CLK_OUT2 and has a duty ratio of 50:50 for the first and second compensation internal clocks CLK_CC1 and CLK_CC2 ) Here, the fact that the clock or signal is enabled or disabled is a logic level state of high or low, and the logic level can be changed according to design.

The operation of the duty ratio correction circuit 115 will be described in detail with reference to FIG. 2.

2 is a diagram for describing an operation of the duty ratio correction circuit 115. As shown in FIG. 2, the duty ratio correction circuit 115 is enabled high in response to the rising edge of the first internal clock CLK_OUT1 and responds to the rising edge of the second internal clock CLK_OUT2. A first compensation internal clock CLK_CC1 that is disabled as a low is output. The duty ratio correction circuit 115 is disabled low in response to the rising edge of the first internal clock CLK_OUT1 and is enabled in the second compensation internal clock high in response to the rising edge of the second internal clock CLK_OUT2. Outputs (CLK_CC2).

The delay lock 101 outputs the second internal clock CLK_OUT2 by inverting the external clock EXT_CLK and according to the duty ratios of the first and second internal clocks CLK_OUT1 and CLK_OUT2. Adjust the delay amount.

As illustrated, when the high level section of the first internal clock CLK_OUT1 is narrower than the low level section, the delay fixing unit 101 increases the delay amount of the second internal clock CLK_OUT2. Therefore, the high level section of the first compensation internal clock CLK_CC1 increases and the low level section decreases by the increased delay amount DD of the second internal clock CLK_OUT2, and the low level of the second compensation internal clock CLK_CC2. The interval increases and the high level interval decreases.

As a result, the duty ratio correction circuit 115 may output the first and second correction internal clocks CLK_CC1 and CLK_CC2 having a 50:50 duty ratio.

Returning to FIG. 1 again, the delay fixing unit 101 and the duty ratio correction circuit unit 115 will be described in more detail. The delay fixing unit 101 may include a phase comparison unit 103, a first delay control unit 105, and a second delay control unit 105. 109), first and second delay parts 107 and 111, and replica 113. As shown in FIG. The duty ratio correction circuit 115 includes a duty ratio corrector 117 and a duty ratio detector 119.

The phase comparison unit 103 compares the phase of the feedback clock FB_CLK output from the external clock EXT_CLK and the replica unit 113 and includes information on the phase difference between the external clock EXT_CLK and the feedback clock FB_CLK. The comparison signal CMP is output. A clock delay component inside the semiconductor device is modeled in the replica unit 113, and the replica unit 113 receives the first compensation internal clock CLK_CC1 and outputs a feedback clock FB_CLK.

Each of the first and second delay controllers 105 and 109 may respond to the first and second internal clocks CLK_OUT1 and CLK_OUT2 in response to the comparison signal CMP and the detection signal DCC output by the duty ratio detector 119. The first and second delay control signals DD_CTRL1 and DD_CTRL2 for adjusting the delay amount of the signal are output. The detection signal DCC includes information on duty ratios of the first and second correction internal clocks CLK_CC1 and CLK_CC2.

Each of the first and second delay units 107 and 111 delays the external clocks EXT_CLK in response to the first and second delay control signals DD_CTRL1 and DD_CTRL2, thereby causing the first and second internal clocks CLK_OUT1 and CLK_OUT2. Outputs The bubble at the output terminal of the second delay unit 109 means inversion, and as described above, the second delay unit 111 inverts and outputs the external clock EXT_CLK.

The first compensation inner clock CLK_CC1 is input to the replica unit 113. When the above process is repeated, the phase of the feedback clock FB_CLK and the external clock EXT_CLK are delayed locked.

Meanwhile, each of the first and second delay control units 105 and 109 decodes the comparison signal CMP and the detection signal DCC and outputs the first and second delay control signals DD_CTRL1 and DD_CTRL2, respectively.

For example, when the duty ratio is corrected to 50:50 only when the delay amount of the second internal clock CLK_OUT2 is increased as illustrated in FIG. 2, the second delay control unit 109 determines that the delay amount of the second internal clock CLK_OUT2 is increased. The second delay control signal DD_CTRL2 is outputted so as to be increased. At this time, since the duty ratios of the first and second corrected internal clocks CLK_CC1 and CLK_CC2 may be corrected when the delay amount of the first internal clock CLK_OUT1 does not increase, the first delay controller 105 may determine the first internal clock CLK_OUT1. The first delay control signal DD_CTRL1 is output so that the delay amount of? Is not increased.

That is, each of the first and second delay controllers 105 and 109 decodes the comparison signal CMP and the detection signal DCC to determine whether to adjust the delay amounts of the first and second internal clocks CLK_OUT1 and CLK_OUT2. As a result, the duty ratios of the first and second correction internal clocks CLK_CC1 and CLK_CC2 can be effectively corrected.

Although not shown in the drawing, the delay fixing unit 101 may further include a pulse generator that generates a plurality of pulse signals that are sequentially enabled. The delay fixing unit 101 sequentially performs a series of delay fixing operations for comparing phases and adjusting delay amounts in response to the plurality of pulse signals sequentially enabled. That is, when the second pulse signal among the plurality of pulse signals is enabled, the comparison signal CMP reflecting the phase comparison result is output, and when the seventh pulse signal enabled later than the second pulse signal is enabled. First and second delay control signals DD_CTRL1 and DD_CTRL2 reflecting the decoding result may be output.

As described above, the first and second delay control units 105 and 109 decode the comparison signal CMP and the detection signal DCC to generate the first and second delay control signals DD_CTRL1 and DD_CTRL2. In order to accomplish this, since a plurality of logic elements are generally used, a predetermined delay occurs in the decoding process. The predetermined delay delays the delay lock operation of the delay lock loop circuit. That is, in the delay lock operation, since the decoding of the comparison signal CMP and the detection signal DCC are performed several times, the delay lock operation may be delayed because the predetermined delay is accumulated in the conventional delay lock loop circuit. There is.

In addition, each of the first and second delay control units 105 and 109 receives and decodes the comparison signal CMP and the detection signal DCC, but the first and second delay control signals DD_CTRL1 and DD_CTRL2 are different decoding results. Since there is a difference in the circuit configuration of the first and second delay control unit 105, 109. The difference in the circuit configuration of the first and second delay controllers 105 and 109 causes a difference in a predetermined delay occurring during the decoding process of the first and second delay controllers 105 and 109. Therefore, there is a time difference until the decoding result is reflected in each of the first and second delay control signals DD_CTRL1 and DD_CTRL2.

For example, as shown in FIG. 3, when the seventh pulse signal is enabled, a delay locked loop circuit is configured such that the first and second delay control signals DD_CTRL1 and DD_CTRL2 reflecting the decoding result are output. The delay control signal to which the decoding result is not reflected may be output. That is, when the time until the decoding result is reflected in the second delay control signal DD_CTRL2 is longer, the second delay control signal DD_CTRL2 may be output without reflecting the decoding result, and the delay locked loop circuit may malfunction. can do.

The present invention has been proposed to solve the above problems, and an object thereof is to provide a delayed fixed loop circuit and a delayed fixed loop circuit driving method capable of improving an operation speed and preventing a malfunction.

The present invention for achieving the above object is a common control unit for selecting one of the comparison signal and the detection signal in response to the operation control signal and outputting the delay control signal; A delay unit delaying an external clock in response to the delay control signal to output first and second internal clocks, and controlling a delay amount of the first internal clock only in an enable period of the operation control signal; A phase comparator for comparing the phases of the external clock and the feedback clock to output the comparison signal; A replica unit configured to receive the first internal clock and output the feedback clock; And correcting the duty ratios of the first and second internal clocks according to the difference between the delay amounts of the first and second internal clocks to output the first and second corrected internal clocks, and the first and second compensation internal clocks. A delay locked loop circuit including a duty ratio correction circuit unit configured to detect a duty ratio of a clock and output the detected signal.

In addition, the present invention for achieving the above object comprises the steps of selecting one of the comparison signal and the detection signal in response to the operation control signal and outputting the delay control signal; Outputting a second internal clock by delaying an external clock in response to the delay control signal; Outputting a first internal clock by delaying the external clock only in an enable period of the operation control signal; Outputting the comparison signal by comparing phases of the external clock and the feedback clock; Receiving the first internal clock and outputting the feedback clock; Outputting first and second corrected internal clocks by correcting a duty ratio of the first and second internal clocks according to a difference between the delay amounts of the first and second internal clocks; And sensing the duty ratios of the first and second correction internal clocks and outputting the detection signals.

According to the present invention, the delay fixing operation and the duty ratio correction operation may be mutually exclusively performed according to a predetermined control signal without a decoding process for performing the delay fixing operation and the duty ratio correction operation exclusively. Therefore, the operation speed of the delay locked loop circuit is increased, and there is an effect that a malfunction due to the delay difference of the decoding process can be prevented.

DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

4 is a diagram illustrating a delay locked loop circuit according to an exemplary embodiment of the present invention.

As shown in FIG. 4, the delay lock loop circuit according to the present invention outputs one of the comparison signal CMP and the detection signal DCC as a delay control signal DD_CTRL in response to the operation control signal OP_CTRL. (403); In response to the delay control signal DD_CTRL, the external clock EXT_CLK is delayed to output the first and second internal clocks CLK_OUT1 and CLK_OUT2, but only in the enable period of the operation control signal OP_CTRL. A delay unit 405 for adjusting the delay amount of the < RTI ID = 0.0 > A phase comparison unit 401 for comparing the phases of the external clock EXT_CLK and the feedback clock FB_CLK and outputting a comparison signal CMP; A replica unit 407 which receives the first internal clock CLK_OUT1 and outputs a feedback clock FB_CLK; And correcting the duty ratios of the first and second internal clocks CLK_OUT1 and CLK_OUT2 according to the difference between the delay amounts of the first and second internal clocks CLK_OUT1 and CLK_OUT2. ) And a duty ratio correction circuit unit 409 which detects the duty ratios of the first and second correction internal clocks CLK_CC1 and CLK_CC2 and outputs a detection signal DCC.

In FIG. 4, the case where the operation control signal OP_CTRL is a clock that toggles at a predetermined period is described as an embodiment.

The phase comparison unit 401 compares the phase of the feedback clock FB_CLK output from the external clock EXT_CLK and the replica unit 407 and includes information on the phase difference between the external clock EXT_CLK and the feedback clock FB_CLK. The comparison signal CMP is output to the common control unit 403. The replica unit 407 models a clock delay component inside the semiconductor device, and the replica unit 407 receives the first compensation internal clock CLK_CC1 and outputs a feedback clock FB_CLK.

The duty ratio correction circuit 409 detects the duty ratios of the first and second compensation internal clocks CLK_CC1 and CLK_CC2 by receiving feedback from the first and second compensation internal clocks CLK_CC1 and CLK_CC2. The detection signal DCC including the duty ratio information of the correction internal clocks CLK_CC1 and CLK_CC2 is output to the common controller 403.

The common controller 403 outputs one of the comparison signal CMP and the detection signal DCC as a delay control signal DD_CTRL in response to the operation control signal OP_CTRL. That is, unlike the first and second delay control units 105 and 109, the common control unit 403 does not decode the comparison signal CMP and the detection signal DCC, but enables the operation control signal OP_CTRL. Selects the comparison signal CMP, selects the detection signal DCC in the disable period of the operation control signal OP_CTRL, and outputs the delayed control signal DD_CTRL. Therefore, the common control unit 403 may reduce a predetermined time that occurs in decoding the comparison signal CMP and the detection signal DCC.

The delay unit 405 and the duty ratio correction circuit unit 409 also operate to correspond to the common control unit 403 outputting one of the comparison signal CMP and the detection signal DCC as the delay control signal DD_CTRL. The delay unit 405 and the duty ratio correction circuit unit 409 will be described.

The delay unit 405 outputs the first and second internal clocks CLK_OUT1 and CLK_OUT2 by delaying the external clock EXT_CLK in response to the delay control signal DD_CTRL, and the delay amount of the first internal clock CLK_OUT1 is Only the enable period of the operation control signal OP_CTRL is adjusted and the delay amount of the second internal clock CLK_OUT2 is adjusted in response to the delay control signal DD_CTRL regardless of the enable period of the operation control signal OP_CTRL. That is, the first internal clock CLK_OUT1 adjusts the delay amount only in response to the comparison signal CMP, and the second internal clock CLK_OUT2 adjusts the delay amount in response to the comparison signal CMP and the detection signal DCC.

As described above, the second internal clock CLK_OUT2 is a clock used to correct the duty ratio of the first internal clock CLK_OUT1, and the delay unit 405 has a detection signal DCC as the delay control signal DD_CTRL. Only the second internal clock CLK_OUT2 is delayed in the disable period of the output operation control signal OP_CTRL. Accordingly, when the duty ratios of the first and second internal clocks CLK_OUT1 and CLK_OUT2 are corrected to output the first and second correction internal clocks CLK_CC1 and CLK_CC2, the first and second internal clocks CLK_CC1 and CLK_CC2 are outputted. The duty ratios of the first and second internal clocks CLK_OUT1 and CLK_OUT2 can be prevented from being adjusted.

The duty ratio correction circuit 409 includes a duty ratio corrector 411 and a duty ratio detector 413.

The duty ratio corrector 411 is enabled in response to a predetermined edge of the first internal clock CLK_OUT1 and is disabled in response to the predetermined edge of the second internal clock CLK_OUT2. CLK_CC1 and CLK_CC2) are output. The predetermined edge may be a rising edge or a falling edge. Hereinafter, the case where the predetermined edge is a rising edge is described as an embodiment.

Since the delay unit 405 outputs the second internal clock CLK_OUT2 by inverting the external clock EXT_CLK, the rising edge of the first internal clock CLK_OUT1 to the rising edge of the second internal clock CLK_OUT2 is the first. And an enable period or a disable period of the second compensation inner clocks CLK_CC1 and CLK_CC2. Therefore, the width of the enable period or the disable period of the first and second compensation internal clocks CLK_CC1 and CLK_CC2 is adjusted according to the delay amount of the second internal clock CLK_OUT2, and the first and second compensation internal clocks CLK_CC1, The duty ratio of CLK_CC2) is corrected.

The duty ratio detector 413 receives the first and second correction internal clocks CLK_CC1 and CLK_CC2 and outputs a detection signal DCC. The duty ratio detector 413 may generate the detection signal DCC using a charge pump charged and discharged according to the duty ratios of the first and second correction internal clocks CLK_CC1 and CLK_CC2.

The duty ratio detector 413 is charged and discharged according to the duty ratios of the first and second compensation internal clocks CLK_CC1 and CLK_CC2 in the enable period of the operation control signal OP_CTRL, and the first and second compensation internal clocks CLK_CC1. , To detect the duty ratio of CLK_CC2). The duty ratio detector 413 generates a detection signal DCC according to the detection result in the disable period of the operation control clock OP_CTRL. Accordingly, the delay unit 405 may adjust the delay amount of the second internal clock CLK_OUT2 in response to the delay control clock DD_CTRL generated from the detection signal DCC in the disable period of the operation control signal OP_CTRL. The detection signal DCC is preferably generated when the operation control signal OP_CTRL is disabled. A more detailed description of the duty ratio detector 413 will be described later with reference to FIG. 5.

The first compensation inner clock CLK_CC1 is input to the replica unit 407. When the above process is repeated, the phase of the feedback clock FB_CLK and the external clock EXT_CLK are delayed locked. The first and second correction internal clocks CLK_CC1 and CLK_CC2 having a duty ratio of 50:50 are generated.

In summary, the common control unit 403 outputs one of the comparison signal CMP and the detection signal DCC as the delay control signal DD_CTRL in response to the operation control signal OP_CTRL without additional decoding. The delay unit 405 also generates a first internal clock CLK_OUT1 in response to the operation control signal DD_CTRL and generates a second internal clock CLK_OUT2 in response to the delay control signal DD_CTRL by the comparison signal CMP. Is generated in response to the delay control signal DD_CTRL by the comparison signal CMP and the detection signal DCC. Also, the duty ratio detector 413 detects the duty ratios of the first and second correction internal clocks CLK_CC1 and CLK_CC2 when the common controller 403 outputs the comparison signal CMP as the delay control signal DD_CTRL. When the common controller 403 outputs the detection signal DCC as the delay control signal DD_CTRL, the common control unit 403 outputs the detection signal DCC.

That is, the delay lock loop according to the present invention can perform the delay lock operation and the duty ratio correction operation without the delay caused by the decoding of the first and second delay controllers 105 and 111 which are conventional problems without decoding.

On the other hand, the delay locked loop circuit according to the present invention may be configured to further include the above-described pulse generator (not shown). In this case, the delay lock loop according to the present invention performs a delay lock operation and a duty ratio correction operation in response to a plurality of sequentially enabled pulse signals generated by the pulse generator. That is, the delay locked loop circuit according to the present invention sequentially compares the phases of the external clock EXT_CLK and the feedback clock FB_CLK in response to a plurality of pulse signals that are sequentially enabled, and performs first and second internal clocks. CLK_OUT1 and CLK_OUT2 are output, and the first and second correction internal clocks CLK_CC1 and CLK_CC2 are output.

In this case, since the delay lock operation and the duty ratio correction operation are performed for one period of the plurality of pulse signals, it is preferable that the operation control signal OP_CTRL is enabled and disabled in synchronization with the first pulse signal of the plurality of pulse signals. .

When the delay locked loop circuit according to the present invention operates with the pulse generator, the delay is performed without generating the first and second delay control signals DD_CTRL1 and DD_CTRL2, which may have a difference in time of occurrence as in the prior art. Since only the control signal DD_CTRL is generated, a malfunction may be prevented.

FIG. 5 is a detailed configuration diagram of the delay unit 405 of FIG. 4.

As shown in FIG. 5, the delay unit 405 includes a first shift register 501, a first delay line 503, a second shift register 505, and a second delay line 507.

The first shift register 501 receives a first control code CODE_1 <1: N> including a plurality of bit signals in response to the delay control signal DD_CTRL and the operation control signal OP_CTRL. Will output The first delay line 503 outputs the first internal clock CLK_OUT1 by delaying the external clock EXT_CLK in response to the first control code CODE_1 <1: N>.

The first shift register 501 adjusts the value of the first control code CODE_1 <1: N> in response to the delay control signal DD_CTRL, but in the disable period of the operation control signal OP_CTRL, the delay control signal ( The value of the first control code CODE_1 <1: N> is maintained without responding to the DD_CTRL. That is, in the enable period of the operation control signal OP_CTRL, the first control code CODE_1 <1: N> has a code value of '001', '011', or '111' according to the delay control signal DD_CTRL. Changes. In the disable period of the operation control signal OP_CTRL, the control code CODE_1 <1: N> maintains the previous code value so that the delay amount of the first internal clock CLK_OUT1 is not adjusted according to the delay control signal DD_CTRL. .

The first delay line 503 receives an external clock EXT_CLK and is composed of a plurality of delay units connected in series. The delay unit outputs the delayed input signal by a predetermined delay amount. The number of delay units through which the external clock EXT_CLK passes varies according to the first control code CODE_1 <1: N>. Therefore, the first internal clock CLK_OUT1 depends on the first control code CODE_1 <1: N>. Delay is controlled.

 The second shift register 505 outputs the second control code CODE_2 <1: N> composed of a plurality of bit signals to the second delay line 507 in response to the delay control signal DD_CTRL. The line 507 outputs the second internal clock CLK_OUT2 by delaying the external clock EXT_CLK in response to the second control code CODE_2 <1: N>.

Since the second internal clock CLK_OUT2 adjusts the delay amount even in the disable period of the operation control signal OP_CTRL, the second shift register 505 does not respond to the operation control signal OP_CTRL.

The second delay line 507 also includes a plurality of delay units connected in series, and outputs the second internal clock CLK_OUT2 by delaying the external clock EXT_CLK according to the second control code CODE_2 <1: N>. . The bubble at the output terminal of the second delay line 507 means inversion. As described above, the second internal clock CLK_OUT2 is generated by inverting the external clock EXT_CLK.

Meanwhile, as will be described later with reference to FIG. 7, the duty ratio detection unit 413 may be configured to start a sensing operation in response to a detection enable signal DCC_EN. In this case, the second shift register 505 may be a second shift register. It can operate in response to the control signal SHIFT_CTRL.

FIG. 6 is a detailed configuration diagram of the duty ratio detector 413 of FIG. 4.

In FIG. 6, an example in which the duty ratio detector 413 starts an operation in response to the detection enable signal DCC is described as an embodiment.

The duty ratio detector 413 charges and discharges according to the duty ratios of the first and second compensation internal clocks CLK_CC1 and CLK_CC2, and transfers the first and second transition signals INC and DEC that transition to different logic levels. Create The comparator (not shown) included in the duty ratio detector 413 detects a logic level difference between the first and second transition signals INC and DEC, and outputs a detection signal DCC. That is, the comparator outputs the detection signal DCC according to which one of the first and second transition signals INC and DEC has a higher logic level.

When the sensing enable signal DCC_EN is enabled high, since the second and fourth NMOS transistors 603 and 607 are turned on to form a current path, the duty ratio detector 413 may start to operate. .

Since the charge is charged to the first and second capacitors 609 and 611 by the power supply voltage VDD while the sensing enable signal DCC_EN is low, the first and second transition signals INC and DEC are charged. Logic level is high. Subsequently, when the sensing enable signal DCC_EN is enabled high, the first and third NMOS transistors 601 and 605 are turned on according to the duty ratios of the first and second compensation internal clocks CLK_CC1 and CLK_CC2. The difference occurs. The NMOS transistor that receives the correction internal clock whose width of the high level section is wider than the width of the low level section has a turn on time longer than the turn off time, and thus discharges the charge charged in the capacitor.

For example, when the width of the high level section of the first compensation inner clock CLK_CC1 is narrower than the width of the low level section, the width of the high level section of the second compensation inner clock CLK_CC2 is wider than the width of the low level section. Accordingly, charge is charged in the first capacitor 609 so that the first transition signal INC transitions to a high level, and in the second capacitor 611, the charge is discharged and the second transition signal DEC transitions to a low level. .

When the operation control signal OP_CTRL is disabled, the reset switch 613 is turned on, and the first capacitor 609 and the second capacitor 611 are connected in parallel to each other so that the first and second transition signals INC and DEC may be connected. The logic level is the same. That is, the first and second transition signals INC and DEC are reset. When the operation control signal OP_CTRL is enabled as high, the reset switch 613 is turned off, so that the first and second transition signals INC and DEC are charged and discharged according to the charging and discharging of the first and second capacitors 609 and 611. To transition.

As a result, the duty ratio detector 413 detects the duty ratios of the first and second compensation internal clocks CLK_CC1 and CLK_CC2 in the enable period of the operation control signal OP_CTRL, and detects the duty ratios of the first and second compensation internal clocks. The first and second transition signals INC and DEC that transition according to the duty ratios of CLK_CC1 and CLK_CC2 are output. The duty ratio detector 413 outputs a detection signal DCC in which the duty ratio detection result is reflected when the operation control signal OP_CTRL is disabled.

7 is a detailed configuration diagram of the common control unit 403 of FIG. 4.

As shown in FIG. 7, the common control unit 403 includes a selection unit 701 and a second shifter register control unit 703.

The selecting means 701 selects one of the comparison signal CMP and the detection signal DCC according to the operation control signal OP_CTRL and outputs the delay control signal DD_CTRL.

The second shifter register control means 703 outputs the second shifter register control signal SHIFT_CTRL, which is always enabled, when the sensing enable signal DCC is enabled to the second shifter register 505. When the sensing enable signal DCC is high, the second shift register control signal SHIFT_CTRL having the same waveform as the operation control signal OP_CTRL is output.

Therefore, when the sensing enable signal DCC_EN is enabled, the second shifter register 503 may correspond to the delay control signal DD_CTRL by the comparison signal CMP and the delay control signal DD_CTRL by the sensing signal DCC. In response, the value of the second control code CODE_2 <1: N> is adjusted.

On the other hand, the delay lock loop according to the present invention is a filter unit (not shown) to perform the delay lock operation and the duty ratio correction operation when the comparison signal (CMP) and the detection signal (DCC) maintain a constant value for a predetermined period It may further include. Since the phase comparing unit 401 and the duty ratio detecting unit 413 may output an incorrect comparison signal CMP and a detection signal DCC due to external noise, the filter unit may compare the comparison signal CMP and the detection signal DCC. In the case where the predetermined value is not maintained for a predetermined period, the operation control signal OP_CTRL and the second shifter register control signal SHIFT_CTRL may be disabled by outputting a filtering signal that is disabled. In this case, the delay unit 405 may adjust the delay amounts of the first and second internal clocks CLK_OUT1 and CLK_OUT2 only when the filtering signal is enabled.

FIG. 8 is a diagram for describing an operation of the delay locked loop circuit of FIG. 4.

In FIG. 8, the phase comparator 401 outputs the comparison signal CMP disabled low and the duty ratio detector 413 outputs the detection signal DCCC enabled high. It is explained. In FIG. 8, the second transition signal DEC is indicated by a dotted line.

As shown in FIG. 8, the operation control signal OP_CTRL is a clock that toggles at a predetermined period.

Each of the first and second transition signals INC and DEC generated by the duty ratio detector 413 transitions to the high level and the low level in the enable period of the operation control signal OP_CTRL, and the operation control signal OP_CTRL. Reset in the disable period.

The duty ratio detector 413 detects a logic level difference between the first and second transition signals INC and DEC, and outputs a high level detection signal DCC in a disable period of the operation control signal OP_CTRL.

The common control unit 403 selects and outputs the comparison signal CMP that is low disabled in the enable period of the operation control signal OP_CTRL, and detects the signal that is high enabled in the disable period of the operation control signal OP_CTRL. Select (DCC) to print.

As a result, the delay locked loop circuit according to the present invention responds to the delay control signal DD_CTRL by the comparison signal CMP in the enable period of the operation control signal OP_CTRL, in response to the first and second sub-clocks CLK_OUT1 and CLK_OUT2. The delay amount of the second internal clock CLK_OUT2 is adjusted in response to the delay control signal DD_CTRL by the detection signal DCC in the disable period of the operation control signal OP_CTRL.

Although the above has been described by the device aspect of the present invention, the operation of each component constituting the delay locked loop circuit according to the present invention can be easily understood from the process point of view. Therefore, the operation of each component constituting the delay locked loop circuit according to the present invention can be understood as each step constituting the driving method of the delay locked loop circuit in accordance with the principles of the present invention. Hereinafter, a driving method of the delay locked loop circuit will be described with reference to FIGS. 4 to 8.

In accordance with another aspect of the present invention, a method of driving a delay locked loop circuit may include selecting one of a comparison signal CMP and a detection signal DCC in response to an operation control signal OP_CTRL and outputting the delayed control signal DD_CTRL; Outputting the second internal clock CLK_OUT2 by delaying the external clock EXT_CLK in response to the delay control signal DD_CTRL; Outputting the first internal clock CLK_OUT1 by delaying the external clock EXT_CLK only in the enable period of the operation control signal OP_CTRL; Outputting a comparison signal CMP by comparing the phases of the external clock EXT_CLK and the feedback clock FB_CLK; Receiving a first internal clock CLK_OUT1 and outputting a feedback clock FB_CLK; The duty ratios of the first and second internal clocks CLK_OUT1 and CLK_OUT2 are corrected according to the difference between the delay amounts of the first and second internal clocks CLK_OUT1 and CLK_OUT2, and the first and second correction internal clocks CLK_CC1 and CLK_CC2 are corrected. Outputting; And detecting a duty ratio of the first and second correction internal clocks CLK_CC1 and CLK_CC2 and outputting a detection signal DCC.

The operation control signal OP_CTRL may be a clock that toggles at a predetermined period. In the step of outputting the delay control signal DD_CTRL, the comparison signal CMP is selected in the enable period of the operation control signal OP_CTRL and the detection signal DCC is selected in the disable period of the operation control signal OP_CTRL. . In the outputting of the detection signal DCC, the duty ratios of the first and second internal clocks CLK_OUT1 and CLK_OUT2 are detected in the enable period of the operation control signal OP_CTRL, and the enable period of the operation control signal OP_CTRL is detected. The detection signal DCC reflecting the duty ratio detection result is output.

In the disable period of the operation control signal OP_CTRL, only the delay amount of the second internal clock CLK_OUT2 is adjusted, and according to the delay locked loop circuit driving method according to the present invention, the delay amount of the second internal clock CLK_OUT2 is determined according to the delay amount of the second internal clock CLK_OUT2. The duty ratios of the first and second internal clocks CLK_OUT1 and CLK_OUT2 may be adjusted.

Although the present invention has been described by means of limited embodiments and drawings, the present invention is not limited thereto and is intended to be equivalent to the technical idea and claims of the present invention by those skilled in the art to which the present invention pertains. Of course, various modifications and variations are possible.

1 is a configuration diagram of a delayed fixed loop circuit for correcting a conventional duty ratio;

2 is a view for explaining the operation of the duty ratio correction circuit 115;

3 is a view for explaining the problem of the conventional delay lock loop;

4 is a diagram illustrating a delay locked loop circuit according to an exemplary embodiment of the present invention;

5 is a detailed configuration diagram of the delay unit 405 of FIG. 4.

FIG. 6 is a detailed configuration diagram of the duty ratio detecting unit 413 of FIG. 4.

7 is a detailed configuration diagram of the common control unit 403 of FIG. 4,

FIG. 8 is a diagram for describing an operation of the delay locked loop circuit of FIG. 4.

Claims (16)

A common control unit selecting one of the comparison signal and the detection signal in response to the operation control signal and outputting the delayed control signal; A delay unit for delaying an external clock in response to the delay control signal to output first and second internal clocks, and controlling a delay amount of the first internal clock only in a section in which the comparison signal is selected; A phase comparator for comparing the phases of the external clock and the feedback clock to output the comparison signal; A replica unit configured to receive the first internal clock and output the feedback clock; And The first and second correction internal clocks are output by correcting the duty ratios of the first and second internal clocks according to the difference between the delay amounts of the first and second internal clocks. A duty ratio correction circuit unit for detecting a duty ratio of the output unit and outputting the detected signal Delay fixed loop circuit comprising a. The method of claim 1, The operation control signal is Clock that toggles at Delayed fixed loop circuit. The method of claim 1, The common control unit Selecting the comparison signal in an enable period of the operation control signal and selecting the detection signal in a disable period of the operation control signal Delayed fixed loop circuit. The method of claim 1, The delay unit Outputting the second internal clock by inverting the external clock; Delayed fixed loop circuit. The method of claim 1, The delay unit The delay amount of the second internal clock is adjusted in response to the delay control signal regardless of whether the operation control signal is enabled. Delayed fixed loop circuit. The method of claim 1, The delay unit A first shift register enabled to the operation control signal to adjust a value of a first control code in response to the delay control signal; A first delay line configured to output the first internal clock by delaying the external clock in response to the first control code; A second shift register configured to adjust a value of a second control code in response to the delay control signal; And A second delay line configured to delay and invert the external clock in response to the second control code to output the second internal clock; Delay fixed loop circuit comprising a. The method of claim 1, The duty ratio correction circuit unit Detecting the duty ratio in an enable period of the operation control signal and outputting the detection signal reflecting the duty ratio detection result in a disable period of the operation control signal; Delayed fixed loop circuit. The method of claim 1, The duty ratio correction circuit unit, A duty ratio for generating first and second transition signals charged and discharged according to the duty ratios of the first and second correction internal clocks, and detecting the level difference between the first and second transition signals to output the detection signal. Sensing unit; And A duty ratio correction unit configured to output the first and second correction internal clocks enabled in response to a predetermined edge of the first internal clock and disabled in response to a predetermined edge of the second internal clock. Delay fixed loop circuit comprising a. The method of claim 8, The duty ratio detector Resetting the first and second transition signals in a disable period of the operation control signal; Delayed fixed loop circuit. 3. The method of claim 2, Generating a plurality of pulse signals that are sequentially enabled in half of the predetermined period and controls the operation of the delay lock loop circuit A delay locked loop circuit further comprising a pulse generator. The method of claim 10, The operation control signal is Synchronized with a first pulse signal of the plurality of pulse signals Delayed fixed loop circuit. The method of claim 1, The delay locked loop circuit A filter unit for outputting a filtering signal for enabling the common control unit when the logic level of the comparison signal is equal to a predetermined interval so that the delay unit operates in response to the delay control signal. Delay fixed loop circuit further comprising. Selecting one of a comparison signal and a detection signal in response to the operation control signal and outputting the delayed control signal; Outputting a second internal clock by delaying an external clock in response to the delay control signal; Outputting a first internal clock by delaying the external clock only in an enable period of the operation control signal; Outputting the comparison signal by comparing phases of the external clock and the feedback clock; Receiving the first internal clock and outputting the feedback clock; Outputting first and second corrected internal clocks by correcting a duty ratio of the first and second internal clocks according to a difference between the delay amounts of the first and second internal clocks; And Sensing the duty ratio of the first and second compensation internal clocks and outputting the detection signal; Delay fixed loop circuit driving method comprising a. The method of claim 13, The operation control signal is Clock that toggles at Method for driving delayed fixed loop circuit. The method of claim 13, The step of outputting the delay control signal is Selecting the comparison signal in an enable period of the operation control signal and selecting the detection signal in a disable period of the operation control signal Method for driving delayed fixed loop circuit. The method of claim 13, The step of outputting the detection signal is Detecting the duty ratio in the enable period of the operation control signal and outputting the detection signal reflecting the duty ratio detection result in the enable period of the operation control signal Method for driving delayed fixed loop circuit.

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